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TARGET_STM32F1 astyle

pull/7351/head
jeromecoutant 2018-06-27 14:31:04 +02:00
parent 6066e68ec6
commit c8313901fb
11 changed files with 125 additions and 120 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c
View File

@ -172,12 +172,12 @@ const PinMap PinMap_SPI_SSEL[] = {
const PinMap PinMap_CAN_RD[] = {
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)},
{PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)},
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)},
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
{PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
{NC, NC, 0}
};

2
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h
View File

@ -45,7 +45,7 @@ typedef enum {
} DACName;
typedef enum {
UART_1 = (int)USART1_BASE,
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
UART_3 = (int)USART3_BASE
} UARTName;

4
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h
View File

@ -174,13 +174,13 @@ typedef enum {
SPI_CS = PB_12,
PWM_OUT = PB_8,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PD_0,
RCC_OSC_OUT = PD_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

2
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h
View File

@ -49,7 +49,7 @@ struct gpio_irq_s {
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
PinDirection direction;
__IO uint32_t *reg_in;
__IO uint32_t *reg_out;
};

4
targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c
View File

@ -109,8 +109,8 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1
{PB_0 , PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3
{PB_1 , PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4
{PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3
{PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 // Connected to SWO
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2

6
targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h
View File

@ -154,17 +154,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PD_0,
RCC_OSC_OUT = PD_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

2
targets/TARGET_STM/TARGET_STM32F1/flash_api.c
View File

@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
} else { /* case where data is aligned, so let's avoid any copy */
while ((address < (StartAddress + size)) && (status == 0)) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) {
address = address + MIN_PROG_SIZE;
data = data + MIN_PROG_SIZE;
} else {

73
targets/TARGET_STM/TARGET_STM32F1/pin_device.h
View File

@ -58,40 +58,40 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af
if (afnum > 0) {
switch (afnum) {
case 1: // Remap SPI1
__HAL_AFIO_REMAP_SPI1_ENABLE();
break;
case 2: // Remap I2C1
__HAL_AFIO_REMAP_I2C1_ENABLE();
break;
case 3: // Remap USART1
__HAL_AFIO_REMAP_USART1_ENABLE();
break;
case 4: // Remap USART2
__HAL_AFIO_REMAP_USART2_ENABLE();
break;
case 5: // Partial Remap USART3
__HAL_AFIO_REMAP_USART3_PARTIAL();
break;
case 6: // Partial Remap TIM1
__HAL_AFIO_REMAP_TIM1_PARTIAL();
break;
case 7: // Partial Remap TIM3
__HAL_AFIO_REMAP_TIM3_PARTIAL();
break;
case 8: // Full Remap TIM2
__HAL_AFIO_REMAP_TIM2_ENABLE();
break;
case 9: // Full Remap TIM3
__HAL_AFIO_REMAP_TIM3_ENABLE();
break;
case 1: // Remap SPI1
__HAL_AFIO_REMAP_SPI1_ENABLE();
break;
case 2: // Remap I2C1
__HAL_AFIO_REMAP_I2C1_ENABLE();
break;
case 3: // Remap USART1
__HAL_AFIO_REMAP_USART1_ENABLE();
break;
case 4: // Remap USART2
__HAL_AFIO_REMAP_USART2_ENABLE();
break;
case 5: // Partial Remap USART3
__HAL_AFIO_REMAP_USART3_PARTIAL();
break;
case 6: // Partial Remap TIM1
__HAL_AFIO_REMAP_TIM1_PARTIAL();
break;
case 7: // Partial Remap TIM3
__HAL_AFIO_REMAP_TIM3_PARTIAL();
break;
case 8: // Full Remap TIM2
__HAL_AFIO_REMAP_TIM2_ENABLE();
break;
case 9: // Full Remap TIM3
__HAL_AFIO_REMAP_TIM3_ENABLE();
break;
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
__HAL_AFIO_REMAP_CAN1_2();
break;
case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
__HAL_AFIO_REMAP_CAN1_2();
break;
#endif
default:
break;
default:
break;
}
}
}
@ -102,19 +102,22 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
switch (pull_config) {
case GPIO_PULLUP:
if (function == LL_GPIO_MODE_FLOATING)
if (function == LL_GPIO_MODE_FLOATING) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
}
LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
break;
case GPIO_PULLDOWN:
if (function == LL_GPIO_MODE_FLOATING)
if (function == LL_GPIO_MODE_FLOATING) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
}
LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
break;
default:
/* Input+NoPull = Floating for F1 family */
if (function == LL_GPIO_MODE_INPUT)
if (function == LL_GPIO_MODE_INPUT) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_FLOATING);
}
break;
}
}

3
targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM1_BASE)
{PWM_1, PWMOUT_ON_APB2},
#endif

116
targets/TARGET_STM/TARGET_STM32F1/serial_device.c
View File

@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
@ -97,7 +97,7 @@ static void uart3_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -214,7 +214,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -234,7 +234,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -256,7 +256,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -264,9 +264,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -313,7 +313,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -327,28 +327,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -358,14 +358,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -386,18 +386,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -407,8 +407,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -420,10 +420,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -436,20 +436,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
@ -471,49 +473,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -521,7 +523,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -535,11 +537,11 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
return return_event;
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -549,17 +551,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -576,20 +578,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -619,9 +621,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -651,7 +653,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

29
targets/TARGET_STM/TARGET_STM32F1/spi_api.c
View File

@ -37,31 +37,32 @@
#include "PeripheralPins.h"
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
int spi_hz = 0;
/* Get source clock depending on SPI instance */
/* Get source clock depending on SPI instance */
switch ((int)spiobj->spi) {
case SPI_1:
/* SPI_1. Source CLK is PCKL2 */
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
case SPI_2:
/* SPI_2. Source CLK is PCKL1 */
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
default:
error("CLK: SPI instance not set");
/* SPI_1. Source CLK is PCKL2 */
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
case SPI_2:
/* SPI_2. Source CLK is PCKL1 */
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
default:
error("CLK: SPI instance not set");
break;
}
return spi_hz;