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Update psoc6pdl to version 1.4.0

pull/12167/head
Dustin Crossman 2019-12-17 12:37:23 -08:00
parent 6ef5fb19bd
commit f53e10e330
284 changed files with 1705 additions and 4915 deletions
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6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler
ALIGN
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
View File

@ -310,10 +310,6 @@ intvec_copy
STR r0, [r1]
dsb
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler
ALIGN
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
View File

@ -190,15 +190,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -236,23 +207,6 @@ Internal7_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

28
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct
View File

@ -3,8 +3,8 @@
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cyb06xxa_cm4_dual.sct
;* \version 2.60
;* \file cyb06xxa_cm4.sct
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -43,7 +43,7 @@
;******************************************************************************/
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000400
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001CFC00
#define MBED_ROM_SIZE 0x001D0000
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
@ -71,25 +71,20 @@
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x000D8000
#define MBED_RAM_SIZE 0x000EA000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE
@ -97,6 +92,9 @@
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
@ -138,7 +136,7 @@
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
{
* (RESET, +FIRST)
}
@ -168,15 +166,13 @@ LR_IROM1 FLASH_START FLASH_SIZE
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
; Used for the digital signature of the secure application and the

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler
ALIGN
END

23
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xxa_cm4_dual.ld
* \version 2.60
* \file cyb06xxa_cm4.ld
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000400
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001CFC00
#define MBED_ROM_SIZE 0x001D0000
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
@ -69,16 +69,19 @@ ENTRY(Reset_Handler)
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x000D8000
#define MBED_RAM_SIZE 0x000EA000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* The size of the MCU boot header area at the start of FLASH */
BOOT_HEADER_SIZE = 0x400;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
@ -93,11 +96,6 @@ EXTERN(Reset_Handler)
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
@ -159,8 +157,9 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
.text ORIGIN(flash) + BOOT_HEADER_SIZE :
{
/* Cortex-M4 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))

21
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xxa_cm4_dual.icf
* \version 2.60
* \file cyb06xxa_cm4.icf
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000400;
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x001CFC00;
define symbol MBED_ROM_SIZE = 0x001D0000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
@ -70,7 +70,7 @@ if (!isdefinedsymbol(MBED_RAM_START)) {
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x000D8000;
define symbol MBED_RAM_SIZE = 0x000EA000;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
@ -82,11 +82,6 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
@ -162,6 +157,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
}
/**** End of ICF editor section. ###ICF###*/
/* The size of the MCU boot header area at the start of FLASH */
define symbol BOOT_HEADER_SIZE = 0x400;
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -192,7 +191,7 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -236,23 +207,6 @@ Internal7_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler
ALIGN
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

11
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx5_cm0plus.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -78,7 +78,7 @@
#define MBED_PUBLIC_RAM_SIZE 0x200
#endif
; Size of the stack section at the end of CM0+ SRAM
; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -236,23 +207,6 @@ Internal7_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx5_cm0plus.ld
* \version 2.50
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -76,7 +76,7 @@ ENTRY(Reset_Handler)
#define MBED_PUBLIC_RAM_SIZE 0x200
#endif
/* Size of the stack section at the end of CM0+ SRAM */
/* The size of the stack section at the end of CM0+ SRAM */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx5_cm0plus.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly};
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application */

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx5_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
; Used for the digital signature of the secure application and the

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -668,23 +639,6 @@ cpuss_interrupts_dw1_31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx5_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx5_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -236,23 +207,6 @@ Internal7_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
; Used for the digital signature of the secure application and the

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler
ALIGN
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
View File

@ -331,10 +331,6 @@ intvec_copy
STR r0, [r1]
dsb
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
; Used for the digital signature of the secure application and the

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler
ALIGN
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
View File

@ -310,10 +310,6 @@ intvec_copy
STR r0, [r1]
dsb
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
View File

@ -190,15 +190,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct
View File

@ -3,8 +3,8 @@
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cyb06xx7_cm4_dual.sct
;* \version 2.60
;* \file cyb06xx7_cm4.sct
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -43,7 +43,7 @@
;******************************************************************************/
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000400
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000CFC00
#define MBED_ROM_SIZE 0x000D0000
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
@ -71,25 +71,20 @@
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00020000
#define MBED_RAM_SIZE 0x0002A000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE
@ -97,6 +92,9 @@
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
@ -138,7 +136,7 @@
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
{
* (RESET, +FIRST)
}

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler
ALIGN
END

23
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xx7_cm4_dual.ld
* \version 2.60
* \file cyb06xx7_cm4.ld
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000400
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000CFC00
#define MBED_ROM_SIZE 0x000D0000
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
@ -69,16 +69,19 @@ ENTRY(Reset_Handler)
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00020000
#define MBED_RAM_SIZE 0x0002A000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* The size of the MCU boot header area at the start of FLASH */
BOOT_HEADER_SIZE = 0x400;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
@ -93,11 +96,6 @@ EXTERN(Reset_Handler)
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
@ -159,8 +157,9 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
.text ORIGIN(flash) + BOOT_HEADER_SIZE :
{
/* Cortex-M4 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))

21
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xx7_cm4_dual.icf
* \version 2.60
* \file cyb06xx7_cm4.icf
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000400;
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x000CFC00;
define symbol MBED_ROM_SIZE = 0x000D0000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
@ -70,7 +70,7 @@ if (!isdefinedsymbol(MBED_RAM_START)) {
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x00020000;
define symbol MBED_RAM_SIZE = 0x0002A000;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
@ -82,11 +82,6 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
@ -162,6 +157,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
}
/**** End of ICF editor section. ###ICF###*/
/* The size of the MCU boot header area at the start of FLASH */
define symbol BOOT_HEADER_SIZE = 0x400;
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -192,7 +191,7 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
View File

@ -23,7 +23,6 @@
; * limitations under the License.
; */
PRESERVE8
THUMB
@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler
ALIGN
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -54,8 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#else
uint32_t cy_BleEcoClockFreqHz = 0UL;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -160,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -222,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -42,7 +42,7 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
@ -82,7 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
; Used for the digital signature of the secure application and the

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -661,23 +632,6 @@ pass_interrupt_dacs_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.60
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -40,7 +40,7 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -41,7 +41,7 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {

228
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -50,24 +51,9 @@
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
/** Default FastClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/* IPC_STRUCT7->DATA configuration */
#define CY_STARTUP_CM0_DP_STATE (0x2uL)
#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
/*******************************************************************************
* SystemCoreClockUpdate (void)
@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -192,6 +157,17 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
CY_STARTUP_IPC7_DP_OFFSET);
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
@ -250,10 +226,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
* \version 2.70
*
* \brief Device system header file.
*
@ -320,6 +320,28 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>
* </tr>
* <tr>
* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
* <td>Provided support for SysPM driver updates.</td>
* </tr>
* <tr>
* <td>Updated the linker scripts.</td>
* <td>Reserved FLASH area for the MCU boot headers.</td>
* </tr>
* <tr>
* <td>Added System Pipe initialization for all devices. </td>
* <td>Improved PDL usability according to user experience.</td>
* </tr>
* <tr>
* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
* <td>Defect fixing.</td>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
@ -439,12 +461,6 @@ extern "C" {
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
@ -460,44 +476,6 @@ extern "C" {
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs;
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz;
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* Backward compatibility macros. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz;
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
#define cy_delayFreqHz (SystemCoreClock)
/** \endcond */

11
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm0plus.sct
;* \version 2.60
;* \version 2.70
;*
;* Linker file for the ARMCC.
;*
@ -78,7 +78,7 @@
#define MBED_PUBLIC_RAM_SIZE 0x200
#endif
; Size of the stack section at the end of CM0+ SRAM
; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
* (STACK)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
View File

@ -23,36 +23,6 @@
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -62,8 +32,9 @@ __heap_limit
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
@ -284,23 +255,6 @@ NvicMux31_IRQHandler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm0plus.ld
* \version 2.50
* \version 2.70
*
* Linker file for the GNU C compiler.
*
@ -76,7 +76,7 @@ ENTRY(Reset_Handler)
#define MBED_PUBLIC_RAM_SIZE 0x200
#endif
/* Size of the stack section at the end of CM0+ SRAM */
/* The size of the stack section at the end of CM0+ SRAM */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm0plus.icf
* \version 2.60
* \version 2.70
*
* Linker file for the IAR compiler.
*
@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly};
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application */

230
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm0plus.c
* \version 2.60
* \version 2.70
*
* The device system-source file.
*
@ -27,6 +27,7 @@
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
@ -37,7 +38,6 @@
#if defined(CY_DEVICE_PSOC6ABLE2)
#include "cy_flash.h"
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
@ -54,21 +54,6 @@
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@ -92,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
uint32_t cy_BleEcoClockFreqHz = 0UL;
/*******************************************************************************
@ -116,37 +99,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
/*******************************************************************************
@ -194,15 +154,11 @@ void SystemInit(void)
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
@ -256,10 +212,7 @@ void SystemInit(void)
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
@ -295,8 +248,7 @@ __WEAK void Cy_SystemInit(void)
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
* Gets core clock frequency and updates \ref SystemCoreClock.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
@ -304,155 +256,19 @@ __WEAK void Cy_SystemInit(void)
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t slowClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
if (0UL != locHf0Clock)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
cy_Hfclk0FreqHz = locHf0Clock;
cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
/* Sets clock frequency for Delay API */
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Slow Clock Divider */
slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
pathFreqHz = pathFreqHz / periClkDiv;
cy_PeriClkFreqHz = pathFreqHz;
pathFreqHz = pathFreqHz / slowClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}

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