From f53e10e33045a09e31750bfecaec76a502e49a8c Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Tue, 17 Dec 2019 12:37:23 -0800 Subject: [PATCH] Update psoc6pdl to version 1.4.0 --- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 6 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 6 +- .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 4 - .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 6 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 6 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- ...cyb06xxa_cm4_dual.sct => cyb06xxa_cm4.sct} | 32 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 2 - .../{cyb06xxa_cm4_dual.ld => cyb06xxa_cm4.ld} | 23 +- ...cyb06xxa_cm4_dual.icf => cyb06xxa_cm4.icf} | 23 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 6 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 6 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S | 50 +-- .../TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf | 5 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct | 12 +- .../TOOLCHAIN_ARM/startup_psoc6_03_cm4.S | 50 +-- .../TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf | 6 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 12 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 6 +- .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.S | 4 - .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 14 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 6 +- .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 4 - .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- ...cyb06xx7_cm4_dual.sct => cyb06xx7_cm4.sct} | 26 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 2 - .../{cyb06xx7_cm4_dual.ld => cyb06xx7_cm4.ld} | 23 +- ...cyb06xx7_cm4_dual.icf => cyb06xx7_cm4.icf} | 23 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 6 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 6 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 8 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 27 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 12 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 50 +-- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 6 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 50 +-- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 5 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 232 ++--------- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 12 +- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 50 +-- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 6 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 228 ++-------- .../device/system_psoc6.h | 80 ++-- .../TARGET_PSOC6/psoc6pdl/README.md | 4 + .../TARGET_PSOC6/psoc6pdl/RELEASE.md | 36 +- .../devices/include/cyb06445lqi_s3d42.h | 4 +- .../include/gpio_psoc6_01_104_m_csp_ble.h | 4 +- .../include/gpio_psoc6_01_104_m_csp_ble_usb.h | 4 +- .../include/gpio_psoc6_01_116_bga_ble.h | 4 +- .../include/gpio_psoc6_01_116_bga_usb.h | 4 +- .../devices/include/gpio_psoc6_01_124_bga.h | 4 +- .../include/gpio_psoc6_01_124_bga_sip.h | 4 +- .../devices/include/gpio_psoc6_01_43_smt.h | 4 +- .../include/gpio_psoc6_01_68_qfn_ble.h | 4 +- .../devices/include/gpio_psoc6_01_80_wlcsp.h | 4 +- .../psoc6pdl/drivers/include/cy_ble_clk.h | 7 +- .../psoc6pdl/drivers/include/cy_flash.h | 29 +- .../psoc6pdl/drivers/include/cy_sar.h | 23 +- .../psoc6pdl/drivers/include/cy_scb_common.h | 11 +- .../psoc6pdl/drivers/include/cy_scb_ezi2c.h | 2 +- .../psoc6pdl/drivers/include/cy_scb_i2c.h | 2 +- .../psoc6pdl/drivers/include/cy_scb_spi.h | 2 +- .../psoc6pdl/drivers/include/cy_scb_uart.h | 2 +- .../psoc6pdl/drivers/include/cy_seglcd.h | 45 +- .../psoc6pdl/drivers/include/cy_smif.h | 38 +- .../drivers/include/cy_smif_memslot.h | 2 +- .../psoc6pdl/drivers/include/cy_sysclk.h | 11 +- .../psoc6pdl/drivers/include/cy_syslib.h | 393 +----------------- .../psoc6pdl/drivers/include/cy_syspm.h | 26 +- .../psoc6pdl/drivers/include/cy_trigmux.h | 72 ++-- .../psoc6pdl/drivers/include/cy_wdt.h | 27 +- .../source/TOOLCHAIN_ARM/cy_syslib_mdk.S | 2 +- .../TOOLCHAIN_A_Clang/cy_syslib_a_clang.S | 2 +- .../source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S | 2 +- .../source/TOOLCHAIN_IAR/cy_syslib_iar.S | 2 +- .../psoc6pdl/drivers/source/cy_ble_clk.c | 14 +- .../psoc6pdl/drivers/source/cy_flash.c | 6 +- .../psoc6pdl/drivers/source/cy_sar.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_common.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_ezi2c.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_i2c.c | 2 +- .../psoc6pdl/drivers/source/cy_scb_spi.c | 4 +- .../psoc6pdl/drivers/source/cy_scb_uart.c | 48 ++- .../psoc6pdl/drivers/source/cy_seglcd.c | 10 +- .../psoc6pdl/drivers/source/cy_smif.c | 4 +- .../psoc6pdl/drivers/source/cy_smif_memslot.c | 17 +- .../psoc6pdl/drivers/source/cy_sysclk.c | 10 +- .../psoc6pdl/drivers/source/cy_syslib.c | 2 +- .../psoc6pdl/drivers/source/cy_syspm.c | 385 +++++++---------- .../psoc6pdl/drivers/source/cy_trigmux.c | 2 +- .../psoc6pdl/drivers/source/cy_wdt.c | 3 +- .../connectivity_wifi-1.0.cypersonality | 38 +- .../peripheral/csd-2.0.cypersonality | 3 +- .../peripheral/seglcd-1.1.cypersonality | 3 +- .../platform/power-1.2.cypersonality | 4 +- .../Connectivity/43012/hobto/ipblocks.cydata | Bin 531 -> 0 bytes .../udd/devices/Connectivity/43012/info.xml | 5 - .../43012C0/CYW43012TC0EKUBG/base/view.xml | 17 + .../43012C0/CYW43012TC0EKUBG/info.xml | 6 + .../CYW43012TC0EKUBG}/studio/presentation | 0 .../43012C0/CYW43012TC0EKUBG/studio/view.xml | 23 + .../CYW43012TC0KFFBH/base/view.xml | 0 .../CYW43012TC0KFFBH/info.xml | 0 .../CYW43012TC0KFFBH}/studio/presentation | 0 .../CYW43012TC0KFFBH/studio/view.xml | 2 +- .../CYW43012WKWBG/base/view.xml | 0 .../{43012 => 43012C0}/CYW43012WKWBG/info.xml | 0 .../43012C0/CYW43012WKWBG/studio/presentation | 2 + .../CYW43012WKWBG/studio/view.xml | 2 +- .../43012C0/hobto/ipblocks.cydata | Bin 0 -> 531 bytes .../{43012 => 43012C0}/hobto/view.xml | 0 .../udd/devices/Connectivity/43012C0/info.xml | 5 + .../{43012 => 43012C0}/studio/view.xml | 0 .../Connectivity/43438/hobto/ipblocks.cydata | Bin 531 -> 0 bytes .../udd/devices/Connectivity/43438/info.xml | 5 - .../CYW43438KUBG/base/view.xml | 0 .../{43438 => 4343A1}/CYW43438KUBG/info.xml | 0 .../CYW43438KUBG/studio/presentation | 0 .../CYW43438KUBG/studio/view.xml | 2 +- .../CYW4343WKUBG/base/view.xml | 0 .../{4343W => 4343A1}/CYW4343WKUBG/info.xml | 0 .../CYW4343WKUBG/studio/presentation | 0 .../CYW4343WKUBG/studio/view.xml | 2 +- .../CYW4343WKWBG/base/view.xml | 0 .../{4343W => 4343A1}/CYW4343WKWBG/info.xml | 0 .../CYW4343WKWBG/studio/presentation | 0 .../CYW4343WKWBG/studio/view.xml | 2 +- .../Connectivity/4343A1/hobto/ipblocks.cydata | Bin 0 -> 531 bytes .../{43438 => 4343A1}/hobto/view.xml | 0 .../udd/devices/Connectivity/4343A1/info.xml | 5 + .../{43438 => 4343A1}/studio/view.xml | 0 .../Connectivity/4343W/hobto/ipblocks.cydata | Bin 531 -> 0 bytes .../devices/Connectivity/4343W/hobto/view.xml | 4 - .../udd/devices/Connectivity/4343W/info.xml | 5 - .../Connectivity/4343W/studio/view.xml | 1 - .../studio/connectivity/43xxx_bt_v1.cydata | Bin 275 -> 275 bytes .../studio/connectivity/43xxx_coex_v1.cydata | Bin 275 -> 275 bytes .../studio/connectivity/43xxx_wifi_v1.cydata | Bin 275 -> 275 bytes .../CYB0644ABZI-S2D44/studio/view.xml | 2 +- .../MXS40/PSoC6A2M/hobto/amuxbus.cydata | Bin 2779 -> 2785 bytes .../MXS40/PSoC6A2M/hobto/clocks.cydata | Bin 1511 -> 1547 bytes .../devices/MXS40/PSoC6A2M/hobto/dsi.cydata | Bin 275 -> 275 bytes .../MXS40/PSoC6A2M/hobto/interrupts.cydata | Bin 2543 -> 2687 bytes .../MXS40/PSoC6A2M/hobto/ipblocks.cydata | Bin 16443 -> 16423 bytes .../devices/MXS40/PSoC6A2M/hobto/pins.cydata | Bin 16443 -> 32827 bytes .../MXS40/PSoC6A2M/hobto/triggers.cydata | Bin 16443 -> 16423 bytes .../PSoC6A2M/studio/analogResourceMap.txt | 1 - .../MXS40/PSoC6A2M/studio/clocks.cysem | 20 +- .../MXS40/PSoC6A2M/studio/clocks.cyvis | 2 +- .../MXS40/PSoC6A2M/studio/product_links.list | 1 + .../CYB06445LQI-S3D42/base/view.xml | 2 +- .../CYB06445LQI-S3D42/studio/view.xml | 4 +- .../MXS40/PSoC6A512K/hobto/amuxbus.cydata | Bin 1671 -> 1675 bytes .../MXS40/PSoC6A512K/hobto/clocks.cydata | Bin 1167 -> 1183 bytes .../devices/MXS40/PSoC6A512K/hobto/dsi.cydata | Bin 275 -> 275 bytes .../MXS40/PSoC6A512K/hobto/interrupts.cydata | Bin 2169 -> 2291 bytes .../MXS40/PSoC6A512K/hobto/ipblocks.cydata | Bin 16443 -> 16423 bytes .../MXS40/PSoC6A512K/hobto/pins.cydata | Bin 16443 -> 16423 bytes .../MXS40/PSoC6A512K/hobto/triggers.cydata | Bin 16443 -> 16423 bytes .../MXS40/PSoC6A512K/studio/clocks.cysem | 16 +- .../MXS40/PSoC6A512K/studio/clocks.cyvis | 2 +- .../PSoC6A512K/studio/product_links.list | 1 + .../CYB06447BZI-BLD53/studio/presentation | 2 +- .../CYB06447BZI-BLD53/studio/view.xml | 4 +- .../CYB06447BZI-BLD54/studio/presentation | 2 +- .../CYB06447BZI-BLD54/studio/view.xml | 4 +- .../CYB06447BZI-D54/studio/presentation | 2 +- .../CYB06447BZI-D54/studio/view.xml | 4 +- .../MXS40/PSoC6ABLE2/hobto/amuxbus.cydata | Bin 2873 -> 2877 bytes .../MXS40/PSoC6ABLE2/hobto/clocks.cydata | Bin 1529 -> 1565 bytes .../devices/MXS40/PSoC6ABLE2/hobto/dsi.cydata | Bin 7193 -> 7273 bytes .../MXS40/PSoC6ABLE2/hobto/interrupts.cydata | Bin 2229 -> 2447 bytes .../MXS40/PSoC6ABLE2/hobto/ipblocks.cydata | Bin 16443 -> 16423 bytes .../MXS40/PSoC6ABLE2/hobto/pins.cydata | Bin 32867 -> 32827 bytes .../MXS40/PSoC6ABLE2/hobto/triggers.cydata | Bin 16443 -> 16423 bytes .../MXS40/PSoC6ABLE2/studio/analog.cysem | 11 +- .../MXS40/PSoC6ABLE2/studio/analog.cyvis | 10 +- .../PSoC6ABLE2/studio/analogResourceMap.txt | 2 +- .../studio/modules/module_43-SMT.cydata | Bin 1643 -> 1655 bytes .../PSoC6ABLE2/studio/product_links.list | 1 + .../psoc6pdl/udd/devices/MXS40/hobto/view.xml | 1 - .../studio/connectivity/m4cpuss_v1-dw0.cydata | Bin 531 -> 531 bytes .../studio/connectivity/m4cpuss_v1-dw1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/m4cpuss_v1.cydata | Bin 1703 -> 1713 bytes .../connectivity/m4cpuss_ver2_v1-dmac.cydata | Bin 531 -> 531 bytes .../connectivity/m4cpuss_ver2_v1-dw0.cydata | Bin 531 -> 531 bytes .../connectivity/m4cpuss_ver2_v1-dw1.cydata | Bin 531 -> 531 bytes .../connectivity/m4cpuss_ver2_v1.cydata | Bin 1823 -> 1837 bytes .../studio/connectivity/mxaudioss_v1.cydata | Bin 1331 -> 1339 bytes .../studio/connectivity/mxbless_v1.cydata | Bin 1131 -> 1137 bytes .../studio/connectivity/mxcan_s40s_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxcsdv2_v1.cydata | Bin 1919 -> 1935 bytes .../studio/connectivity/mxefuse_v1.cydata | Bin 275 -> 275 bytes .../MXS40/studio/connectivity/mxlcd_v1.cydata | Bin 1199 -> 1199 bytes .../studio/connectivity/mxlcd_ver2_v1.cydata | Bin 1243 -> 1243 bytes .../studio/connectivity/mxlpcomp_s40.cydata | Bin 1481 -> 1505 bytes .../studio/connectivity/mxperi_v1.cydata | Bin 1113 -> 1145 bytes .../studio/connectivity/mxperi_ver2_v1.cydata | Bin 1145 -> 1177 bytes .../studio/connectivity/mxprofile_v1.cydata | Bin 531 -> 531 bytes .../connectivity/mxs40ioss_v1-port.cydata | Bin 4113 -> 4133 bytes .../studio/connectivity/mxs40ioss_v1.cydata | Bin 1749 -> 1767 bytes .../connectivity/mxs40ioss_v2-port.cydata | Bin 4121 -> 4141 bytes .../studio/connectivity/mxs40ioss_v2.cydata | Bin 1855 -> 1875 bytes .../connectivity/mxs40pass_v1-ctbm.cydata | Bin 2697 -> 2737 bytes .../connectivity/mxs40pass_v1-sar.cydata | Bin 1595 -> 1617 bytes .../connectivity/mxs40pass_v1-sarmux.cydata | Bin 2487 -> 2555 bytes .../studio/connectivity/mxs40pass_v1.cydata | Bin 2837 -> 2855 bytes .../connectivity/mxs40srss_v1-power.cydata | Bin 0 -> 531 bytes .../connectivity/mxs40srss_v1-sysclk.cydata | Bin 1941 -> 1961 bytes .../studio/connectivity/mxs40srss_v1.cydata | Bin 2289 -> 2221 bytes .../MXS40/studio/connectivity/mxscb_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxsdhc_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxsmif_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxtcpwm_v1.cydata | Bin 1707 -> 1711 bytes .../connectivity/mxttcanfd_s40s_v1.cydata | Bin 1067 -> 1081 bytes .../MXS40/studio/connectivity/mxudb_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxusbfs_v1.cydata | Bin 531 -> 531 bytes .../udd/devices/MXS40/studio/features.mk | 9 +- .../TARGET_PSOC6/psoc6pdl/udd/version.dat | 2 +- .../TARGET_PSOC6/psoc6pdl/udd/version.xml | 2 +- .../TARGET_PSOC6/psoc6pdl/version.xml | 2 +- 284 files changed, 1705 insertions(+), 4915 deletions(-) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/{cyb06xxa_cm4_dual.sct => cyb06xxa_cm4.sct} (91%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/{cyb06xxa_cm4_dual.ld => cyb06xxa_cm4.ld} (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/{cyb06xxa_cm4_dual.icf => cyb06xxa_cm4.icf} (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/{cyb06xx7_cm4_dual.sct => cyb06xx7_cm4.sct} (92%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/{cyb06xx7_cm4_dual.ld => cyb06xx7_cm4.ld} (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/{cyb06xx7_cm4_dual.icf => cyb06xx7_cm4.icf} (94%) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/hobto/ipblocks.cydata delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/info.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012/CYW43012TC0KFFBH => 43012C0/CYW43012TC0EKUBG}/studio/presentation (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/CYW43012TC0KFFBH/base/view.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/CYW43012TC0KFFBH/info.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012/CYW43012WKWBG => 43012C0/CYW43012TC0KFFBH}/studio/presentation (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/CYW43012TC0KFFBH/studio/view.xml (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/CYW43012WKWBG/base/view.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/CYW43012WKWBG/info.xml (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/CYW43012WKWBG/studio/view.xml (94%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/hobto/ipblocks.cydata rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/hobto/view.xml (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/info.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43012 => 43012C0}/studio/view.xml (100%) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/hobto/ipblocks.cydata delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/info.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43438 => 4343A1}/CYW43438KUBG/base/view.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43438 => 4343A1}/CYW43438KUBG/info.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43438 => 4343A1}/CYW43438KUBG/studio/presentation (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43438 => 4343A1}/CYW43438KUBG/studio/view.xml (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKUBG/base/view.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKUBG/info.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKUBG/studio/presentation (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKUBG/studio/view.xml (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKWBG/base/view.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKWBG/info.xml (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKWBG/studio/presentation (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{4343W => 4343A1}/CYW4343WKWBG/studio/view.xml (94%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/hobto/ipblocks.cydata rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43438 => 4343A1}/hobto/view.xml (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/info.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/{43438 => 4343A1}/studio/view.xml (100%) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/ipblocks.cydata delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/view.xml delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/info.xml delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/studio/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/product_links.list create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/product_links.list create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/product_links.list delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/hobto/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ceea77c834..4ff5ccb454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 13693b21e0..0f7f5fe0df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 4ab15c0903..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641ea4f..9be3c4aa3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379863..b405a8b603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S index 75747c4fac..f4ca47b457 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -310,10 +310,6 @@ intvec_copy STR r0, [r1] dsb - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ceea77c834..4ff5ccb454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 13693b21e0..0f7f5fe0df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 4ab15c0903..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641ea4f..9be3c4aa3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379863..b405a8b603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index ab9fd9468d..b16001ceba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -190,15 +190,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S index 47553fba55..2ebb953cfd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -236,23 +207,6 @@ Internal7_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct similarity index 91% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 2e5ebd339d..0a03d5c5b6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -3,8 +3,8 @@ ; to pass a scatter file through a C preprocessor. ;******************************************************************************* -;* \file cyb06xxa_cm4_dual.sct -;* \version 2.60 +;* \file cyb06xxa_cm4.sct +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -43,7 +43,7 @@ ;******************************************************************************/ #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif ;* MBED_APP_START is being used by the bootloader build script and @@ -55,7 +55,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001CFC00 + #define MBED_ROM_SIZE 0x001D0000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -71,25 +71,20 @@ #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000D8000 + #define MBED_RAM_SIZE 0x000EA000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. ; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; RAM #define RAM_START MBED_RAM_START #define RAM_SIZE MBED_RAM_SIZE @@ -97,6 +92,9 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -138,7 +136,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -168,17 +166,15 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) - } - + } + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S index 88eb1f471d..114d71efb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld index ac40c265d1..6bc500fffd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xxa_cm4_dual.ld -* \version 2.60 +* \file cyb06xxa_cm4.ld +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif /* MBED_APP_START is being used by the bootloader build script and @@ -53,7 +53,7 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001CFC00 + #define MBED_ROM_SIZE 0x001D0000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -69,16 +69,19 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000D8000 + #define MBED_RAM_SIZE 0x000EA000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -93,11 +96,6 @@ EXTERN(Reset_Handler) MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE @@ -159,8 +157,9 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { + /* Cortex-M4 flash vector table */ . = ALIGN(4); __Vectors = . ; KEEP(*(.vectors)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf index dad660234a..22ac13a47f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xxa_cm4_dual.icf -* \version 2.60 +* \file cyb06xxa_cm4.icf +* \version 2.70 * * Linker file for the IAR compiler. * @@ -42,7 +42,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000400; + define symbol MBED_ROM_START = 0x10000000; } /* MBED_APP_START is being used by the bootloader build script and @@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) { } if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x001CFC00; + define symbol MBED_ROM_SIZE = 0x001D0000; } /* MBED_APP_SIZE is being used by the bootloader build script and @@ -70,7 +70,7 @@ if (!isdefinedsymbol(MBED_RAM_START)) { } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x000D8000; + define symbol MBED_RAM_SIZE = 0x000EA000; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { @@ -82,11 +82,6 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; @@ -95,7 +90,7 @@ define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -162,6 +157,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + define memory mem with size = 4G; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; @@ -192,7 +191,7 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ /* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 0a3875cd81..f5a99814fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S index 47553fba55..2ebb953cfd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -236,23 +207,6 @@ Internal7_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 4ed4dc146b..620923dcae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S index 88eb1f471d..114d71efb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 964fb03e80..ffbeca9b8e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 7f2b290955..3080c25daa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index 1ae3cb2355..d9f249300a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S index cd5bc7d28c..ba67c4bd39 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -236,23 +207,6 @@ Internal7_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld index 1147ac7c82..5611270447 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index 669e6ede37..68b322da34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 9a43a228d2..4f8eeead26 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S index e3f3cbf4da..f4739ec195 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -668,23 +639,6 @@ cpuss_interrupts_dw1_31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index be9d6bd87c..f6fbe4ad7b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf index fc2074aff6..07f3242517 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 0a3875cd81..f5a99814fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S index 47553fba55..2ebb953cfd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -236,23 +207,6 @@ Internal7_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 5537046ec5..620923dcae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S index 88eb1f471d..114d71efb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 964fb03e80..ffbeca9b8e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 7f2b290955..3080c25daa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S index ade874af4d..3257b6f20c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S @@ -331,10 +331,6 @@ intvec_copy STR r0, [r1] dsb - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ceea77c834..4ff5ccb454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 55753228b5..0f7f5fe0df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -179,17 +179,15 @@ LR_IROM1 FLASH_START FLASH_SIZE { * (.noinit) } - + ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 4ab15c0903..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641ea4f..9be3c4aa3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379863..b405a8b603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S index 75747c4fac..f4ca47b457 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -310,10 +310,6 @@ intvec_copy STR r0, [r1] dsb - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 0a23502c75..1a7e1db522 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -190,15 +190,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index ae0dda1f42..77d3f7112a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -3,8 +3,8 @@ ; to pass a scatter file through a C preprocessor. ;******************************************************************************* -;* \file cyb06xx7_cm4_dual.sct -;* \version 2.60 +;* \file cyb06xx7_cm4.sct +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -43,7 +43,7 @@ ;******************************************************************************/ #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif ;* MBED_APP_START is being used by the bootloader build script and @@ -55,7 +55,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000CFC00 + #define MBED_ROM_SIZE 0x000D0000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -71,25 +71,20 @@ #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00020000 + #define MBED_RAM_SIZE 0x0002A000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. ; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; RAM #define RAM_START MBED_RAM_START #define RAM_SIZE MBED_RAM_SIZE @@ -97,6 +92,9 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -138,7 +136,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -175,8 +173,8 @@ LR_IROM1 FLASH_START FLASH_SIZE ; Stack region growing down ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - } - + } + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 4ab15c0903..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld index 0a81d0b541..da76487fb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xx7_cm4_dual.ld -* \version 2.60 +* \file cyb06xx7_cm4.ld +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif /* MBED_APP_START is being used by the bootloader build script and @@ -53,7 +53,7 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000CFC00 + #define MBED_ROM_SIZE 0x000D0000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -69,16 +69,19 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00020000 + #define MBED_RAM_SIZE 0x0002A000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -93,11 +96,6 @@ EXTERN(Reset_Handler) MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE @@ -159,8 +157,9 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { + /* Cortex-M4 flash vector table */ . = ALIGN(4); __Vectors = . ; KEEP(*(.vectors)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf index f6322dc7bc..076a8ff914 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xx7_cm4_dual.icf -* \version 2.60 +* \file cyb06xx7_cm4.icf +* \version 2.70 * * Linker file for the IAR compiler. * @@ -42,7 +42,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000400; + define symbol MBED_ROM_START = 0x10000000; } /* MBED_APP_START is being used by the bootloader build script and @@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) { } if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x000CFC00; + define symbol MBED_ROM_SIZE = 0x000D0000; } /* MBED_APP_SIZE is being used by the bootloader build script and @@ -70,7 +70,7 @@ if (!isdefinedsymbol(MBED_RAM_START)) { } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00020000; + define symbol MBED_RAM_SIZE = 0x0002A000; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { @@ -82,11 +82,6 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; @@ -95,7 +90,7 @@ define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -162,6 +157,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + define memory mem with size = 4G; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; @@ -192,7 +191,7 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ /* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ceea77c834..4ff5ccb454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 13693b21e0..0f7f5fe0df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 4ab15c0903..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641ea4f..9be3c4aa3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379863..b405a8b603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ceea77c834..4ff5ccb454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index f2929e050a..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -54,8 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#else - uint32_t cy_BleEcoClockFreqHz = 0UL; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -160,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -222,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 7ccd6c547d..0f7f5fe0df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 5bd2271438..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -661,23 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641ea4f..9be3c4aa3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379863..b405a8b603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ff0e80b840..4ff5ccb454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029f52..09d6b4ccfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index b8339aa0ea..a9d28573c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3b98b65c35..3a0414efa3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 9164b15dd6..18cc197563 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -37,7 +38,6 @@ #if defined(CY_DEVICE_PSOC6ABLE2) #include "cy_flash.h" #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ @@ -54,21 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -92,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -116,37 +99,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -194,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -256,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -295,8 +248,7 @@ __WEAK void Cy_SystemInit(void) * Function Name: SystemCoreClockUpdate ****************************************************************************//** * -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* Gets core clock frequency and updates \ref SystemCoreClock. * * Updates global variables used by the \ref Cy_SysLib_Delay(), \ref * Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). @@ -304,155 +256,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t slowClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Slow Clock Divider */ - slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - - pathFreqHz = pathFreqHz / periClkDiv; - cy_PeriClkFreqHz = pathFreqHz; - pathFreqHz = pathFreqHz / slowClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 7ccd6c547d..0f7f5fe0df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 5bd2271438..fa2247ebe9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -661,23 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641ea4f..9be3c4aa3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379863..b405a8b603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50a4d..7800d6b2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h index 423361f58a..8dd97ffb7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md index 05b54d123d..5f1875379b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md @@ -6,6 +6,10 @@ The PDL integrates device header files, startup code, and peripheral drivers into a single package. The drivers abstract the hardware functions into a set of easy-to-use APIs. These are fully documented in the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html). +This version of the PDL is compatible with ModusToolbox. It is not compatible +with PSoC Creator. The most recent PSoC Creator-compatible version of the PDL +is [available here](https://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl). + ### Features * Includes all the updates made to the peripheral drivers for ModusToolboxâ„¢ software * Contains standard set of PSoC® 6 digital and analog peripheral drivers that enable rapid peripheral software development in third-party IDEs diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md index 2eb1fec50e..246c6bdffd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md @@ -1,19 +1,37 @@ -# PSoC 6 Peripheral Driver Library v1.3.1 +# PSoC 6 Peripheral Driver Library v1.4.0 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library. ### New Features +* The structure of BSP startup templates directory (devices/templates) is updated to match the BSP layout. +* The updated core-lib is reused - see [SysLib changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) for details. +* Removed redundant legacy PSoC Creator-compatibility macros. +* The startup code reuses sysclk driver API - see [Startup changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) for details. + +Updated Personalities +* CSD +* Power +* SegLCD +* WiFi +Updated the configurators launch parameters in CSD and SegLCD personalities: switched from GUI to console applications for regenerating the source code without opening the configurator itself. This improves the user experience, performance, and enables using machines without a GUI. +The Power personality code generation is corrected due to the customer's request. +The TCP Keepalive Offload feature support is added to the WiFi Low Power Assistant (LPA) personality. + Updated Drivers -* [SysInt 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysint.html) -* [SysPm 4.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) -* [USBFS 2.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html) +* [BLE_CLK 3.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) +* [SCB 2.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__scb.html) +* [Startup 2.70](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) +* [SysClk 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) +* [SysLib 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) +* [SysPm 4.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) +* [WDT 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html) Drivers with patch version updates -* [CAN FD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) -* [Flash 3.30.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) -* [Prot 1.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) -* [SysClk 1.40.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) - +* [Flash 3.30.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) +* [SAR 1.20.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sar.html) +* [SegLCD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__seglcd.html) +* [SMIF 1.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) +* [TrigMux 1.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__trigmux.html) ### Known Issues None diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h index 8b23c5c8b2..fac6b9fe3d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h @@ -5,7 +5,7 @@ * CYB06445LQI-S3D42 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.5.0.1314 * ******************************************************************************** * \copyright @@ -423,7 +423,7 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00040000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00080000UL +#define CY_FLASH_SIZE 0x00070000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL #define CY_XIP_BASE 0x18000000UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h index 0dbcf02996..ab43a2f532 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h index 0c56c6d92a..cc8661211b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h index 6682218daf..2c9b4f4532 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 116-BGA-BLE package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h index 77a07a4c54..08e39964d2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 116-BGA-USB package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h index 2816a3c9b2..f1f07c9a78 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 124-BGA package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h index c5c91adcf7..15c7230c50 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 124-BGA-SIP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h index 7bb2963cf8..fca88f2943 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 43-SMT package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h index d85ef68542..2719e9bda0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 68-QFN-BLE package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h index 2b4230ab79..09f3677beb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 80-WLCSP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h index c540486d6d..b75868e107 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.20 +* \version 3.30 * * The header file of the BLE ECO clock driver. * @@ -70,6 +70,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h index ad3c50820e..f39679c5a6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.h -* \version 3.30.2 +* \version 3.30.3 * * Provides the API declarations of the Flash driver. * @@ -66,7 +66,7 @@ * * \subsection group_flash_config_intro Introduction: * The PSoC 6 MCU user-programmable Flash consists of: -* - Four User Flash sectors (0 through 3) - 256KB each. +* - User Flash sectors (from 4 to 8) - 256KB each. * - EEPROM emulation sector - 32KB. * * Write operations are performed on a per-sector basis and may be done as @@ -97,9 +97,10 @@ * -# Flash write cannot be performed in ULP (core voltage 0.9V) mode. * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. -* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4) -* have the highest priority, or at least that pipe interrupts are not -* interrupted or in a pending state for more than 700 µs. +* -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe +* interrupts (IPC interrupts 3 and 4) have the highest priority, or +* at least that pipe interrupts are not interrupted or in a pending state +* for more than 700 µs. * -# User must guarantee that during flash write operation no flash read * operations are performed by bus masters other than CM0+ and CM4 (DMA and * Crypto). @@ -119,7 +120,8 @@ * *
*
VersionChangesReason of Change
3.30Updated the \ref Cy_BLE_EcoConfigure() to reuse the \ref Cy_SysClk_ClkPeriGetFrequency().API enhancement.
3.20Updated the Cy_BLE_EcoConfigure(): it stores the ECO frequency for possible frequency calculation by the Cy_SysClk_ClkHfGetFrequency().API enhancement.
-* +* * * * @@ -196,7 +198,8 @@ * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) * -# Do not write to and read/execute from the same flash sector at the same * time. This is true for all sectors. -* -# Writing rules in User Flash: +* -# Writing rules in User Flash (this restriction is applicable just for the +* CY8C6xx6, CY8C6xx7 devices): * -# Any bus master can read/execute from UFLASH S0 and/or S1, during * flash write to UFLASH S2 or S3. * -# Any bus master can read/execute from UFLASH S2 and/or S3, during @@ -209,9 +212,10 @@ * -# Flash write cannot be performed in ULP mode (core voltage 0.9V). * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. -* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4) -* have the highest priority, or at least that pipe interrupts are not -* interrupted or in a pending state for more than 700 µs. +* -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe +* interrupts (IPC interrupts 3 and 4) have the highest priority, or at +* least that pipe interrupts are not interrupted or in a pending state +* for more than 700 µs. * -# User must guarantee that during flash write operation no flash read * operations are performed by bus masters other than CM0+ and CM4 * (DMA and Crypto). @@ -256,6 +260,11 @@ *
Table 1 - Block-out periodsTable 1 - Block-out periods (timing values are valid just for the +* CY8C6xx6, CY8C6xx7 devices)
Block-outPhase
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h index 9fc59cde92..f0c5bacdc4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sar.h -* \version 1.20.1 +* \version 1.20.2 * * Header file for the SAR driver. * @@ -496,13 +496,25 @@ * are connected to the SARADC as separate single-ended channels and as a differential-pair channel. * Note that separate function calls are needed to route the device pins to the SARMUX. The AMUXBUSes * are separated into multiple segments and these segments are connected/disconnected using the AMUX_SPLIT_CTL -* registers in the HSIOM. In the following code snippet, to connect Port 1 to the SARMUX, the left and right -* switches of AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6] need to be closed. +* registers in the HSIOM. * * \image html sar_sarmux_amuxbus.png * * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_AMUXBUS * +* +* To connect SARMUX to any other non-dedicated port, you may need to close additional HSIOM switches to route signals +* through AMUXBUS. +* For more detail, see the device TRM, AMUX splitting. +* +* The following code snippet is an alternative pin configuration. To connect Port 1 to AMUXBUS, close the left and +* right switches of AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6]. +* +* \warning +* This snippet shows how to configure pins for CY8C6347BZI-BLD53. +* +* \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_CUSTOM_PORT +* * \section group_sar_low_power Low Power Support * This SAR driver provides a callback function to handle power mode transitions. * The \ref Cy_SAR_DeepSleepCallback function ensures that SAR conversions are stopped @@ -546,6 +558,11 @@ *
VersionChangesReason for Change
3.30.3Updated documentation to limit devices with the restrictions. Improved calculation of the CY_FLASH_DELAY_CORRECTIVE macro.User experience enhancement.
3.30.2Updated documentation to limit devices with the neighboring restriction.User experience enhancement.
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h index d8f30c116b..d6543717a8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.h -* \version 2.30.1 +* \version 2.40 * * Provides common API declarations of the SCB driver. * @@ -137,6 +137,15 @@ *
VersionChangesReason for Change
1.20.2Code snippets update.PDL infrastructure update, documentation enhancement.
1.20.1Code snippets update.PDL infrastructure update, documentation enhancement.
* * +* +* +* +* +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h index 324750b03e..d9fef60788 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.h -* \version 2.30.1 +* \version 2.40 * * Provides EZI2C API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h index 4f3edfbb5d..e4b9454773 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.h -* \version 2.30.1 +* \version 2.40 * * Provides I2C API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h index 65f1860088..221eca3e3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.h -* \version 2.30.1 +* \version 2.40 * * Provides SPI API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h index 37a22434f9..fc63c5e92a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.h -* \version 2.30.1 +* \version 2.40 * * Provides UART API declarations of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h index d08264fdf6..70d474cce9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_seglcd.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_seglcd.h -* \version 1.0 +* \version 1.0.1 * * \brief * Provides an API declaration of the Segment LCD driver. @@ -43,18 +43,16 @@ * * \section group_seglcd_glossary Glossary * * LCD - Liquid Crystal Display -* * Glass - An LCD glass that may contain a few displays +* * Glass - An LCD glass with one or more displays * (e.g. one 7-segment display and one bar-graph display). * * TN - A twisted nematic LCD glass. * * STN - A super-twisted nematic LCD glass. -* * Display - A block of homogeneous symbols on an LCD glass -* intended to indicate a multi-digital number or character string. -* A few displays are possible whithin a single LCD glass. -* * Symbol - A block of pixels on an LCD glass intended to indicate only digit or character. -* * Pixel - A unity LCD displaying item with a binary state (on/off). -* It can be a segment of e.g. the 7-segment symbol (therefore may be called "segment"), -* a pixel of the matrix display, or a standalone arbitrarily-shaped display element. -* Each pixel has a unique set of common and segment lines in scope of the LCD glass. +* * Display - A block of the same type of symbols on an LCD glass to indicate a multi-digital +* number or character string. There may be one or more displays on a single LCD glass. +* * Symbol - A block of pixels on an LCD glass to indicate a single digit or character. +* * Pixel - A basic displaying item. This can be a segment of a 7-segment symbol (thus called a "segment"), +* a pixel of a dot-matrix display, or a stand-alone arbitrarily-shaped display element. +* Each pixel has a unique set of common and segment lines within one LCD glass. * The API offers pixel identifiers - the 32-bit items of the display pixel map * (to use in the display structure definition, see \ref cy_stc_seglcd_disp_t), * created by the \ref CY_SEGLCD_PIXEL macro. @@ -102,6 +100,8 @@ * For large High Speed clock frequencies, certain ratios between the contrast and frame * rate cannot be achieved due to the limited divider size. The \ref Cy_SegLCD_Init function * automatically restricts such incorrect combinations (returns \ref CY_SEGLCD_BAD_PARAM). +* The peripheral clock divider can be adjusted to clock the LCD block with proper clock frequency: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Clock * * Speed Mode Switching (\ref cy_stc_seglcd_config_t.speed)\n * The High Speed and Low Speed generators mostly duplicate each other, @@ -110,7 +110,8 @@ * typically has a frequency 30-100 times bigger than the 32 KHz clock fed to the Low Speed block. * For MXLCD_ver2, both High Speed and Low Speed generators have similar 16-bit dividers, * because a possibility exists to source a Low Speed generator with a Medium Frequency clock -* (see \ref group_sysclk_mf_funcs) that may be much higher than 32 KHz ILO. +* (see \ref group_sysclk_mf_funcs) that may be much higher than 32 KHz ILO: +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_MF_Clock * Switching between High Speed and Low Speed modes via the \ref Cy_SegLCD_Init function * causes the dividers to reconfigure. * Under possible restrictions related to certain ratios between contrast and frame rates @@ -214,6 +215,16 @@ * \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_InvPixel * \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_ActPixel * +* The basic use case of the bar-graph display type: +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_DefFrame +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_BarLength +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_BarGraphDisplay +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_BarGraphValue +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_SetFrame +* \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_BarGraph +* after which the next image on the glass appears: +* \image html seglcd_bargraph.png +* * Also, you can customize basic fonts, for example: * \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_CustomAsciiFont7seg * And now you can write characters and strings on a standard 7-segment display: @@ -231,6 +242,10 @@ * \snippet seglcd/snippet/SegLCD_Snpt.c snippet_Cy_SegLCD_Custom3x5_WriteNumber * \image html seglcd_3x5.png * +* There are LCD-GPIO terminal mapping definitions for different device families +* used in the mentioned above commons and display pixel arrays: +* \snippet seglcd/snippet/SegLCD_Snpt.h snippet_Cy_SegLCD_connectionRemapping +* * \section group_seglcd_more_information More Information * Refer to the technical reference manual (TRM) and the device datasheet. * @@ -269,6 +284,11 @@ *
VersionChangesReason for Change
2.40Update level selection logic of RX FIFO trigger in the Cy_SCB_UART_Receive().Fix possible stuck if the RTS level is less than the RX FIFO level.
Exclude self-test assertion macros under release build profile.Avoid dependency on CY_ASSERT macro implementation.
2.30.1Added header guards CY_IP_MXSCB.To enable the PDL compilation with wounded out IP blocks.
* * +* +* +* +* +* * * * @@ -476,7 +496,8 @@ typedef struct */ uint8_t frRate; /**< The LCD frame rate, the valid range is 30...150 */ uint8_t contrast; /**< The LCD contrast, the valid range is 0...100 */ - uint32_t clkFreq; /**< The LCD clock frequency (ignored for \ref CY_SEGLCD_SPEED_LOW mode), + uint32_t clkFreq; /**< The LCD clock frequency (ignored for \ref CY_SEGLCD_LSCLK_LF mode, + * or in \ref CY_SEGLCD_SPEED_LOW mode for MXLCD_ver1), * the valid range is 10000...100000000 (Hz) */ } cy_stc_seglcd_config_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h index 0bbdacd992..c109bac045 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.h -* \version 1.40 +* \version 1.40.1 * * Provides an API declaration of the Cypress SMIF driver. * @@ -25,20 +25,21 @@ /** * \addtogroup group_smif * \{ -* The SPI-based communication interface for external memory devices. +* The SPI-based communication interface to the external quad SPI (QSPI) +* high-speed memory devices. * * The functions and other declarations used in this driver are in cy_smif.h and * cy_smif_memslot.h (if used). If you are using the ModusToolbox QSPI Configurator, * also include cycfg_qspi_memslot.h. * -* SMIF: Serial Memory Interface: This IP block implements an SPI-based -* communication interface for interfacing external memory devices to PSoC. The SMIF -* supports Octal-SPI, Dual Quad-SPI, Quad-SPI, Dual-SPI, and SPI. -* +* **SMIF: Serial Memory Interface**: This IP block implements an SPI-based +* communication interface for interfacing external memory devices to PSoC. +* The SMIF supports SPI, dual SPI (DSPI), quad SPI (QSPI), dual QSPI and octal SPI. +* * Features * - Standard SPI Master interface -* - Supports Single/Dual/Quad/Octal SPI Memories -* - Supports Dual-Quad SPI mode +* - Supports single/dual/quad/octal SPI memory devices +* - Supports dual quad SPI mode * - Design-time configurable support for multiple (up to 4) external serial * memory devices * - eXecute-In-Place (XIP) operation mode for both read and write accesses @@ -122,12 +123,12 @@ * See the documentation for Cy_SMIF_Init() and Cy_SMIF_MemInit() for details * on the required configuration structures and other initialization topics. * -* The normal (MMIO) mode is used for implementing a generic SPI/DSPI/QSPI/Dual -* Quad-SPI/Octal-SPI communication interface using the SMIF block. This +* The normal (MMIO) mode is used for implementing a generic SPI/DSPI/QSPI/dual +* QSPI/octal SPI communication interface using the SMIF block. This * interface can be used to implement special commands like Program/Erase of * flash, memory device configuration, sleep mode entry for memory devices or * other special commands specific to the memory device. The transfer width -* (SPI/DSP/Quad-SPI/Octal-SPI) of a transmission is a parameter set for each +* (SPI/DSPI/QSPI/octal SPI) of a transmission is a parameter set for each * transmit/receive operation. So these can be changed at run time. * * In a typical memory interface with flash memory, the SMIF is used in the @@ -213,6 +214,15 @@ *
VersionChangesReason for Change
1.0.1Code snippets are extended to support the CY8C62x5 device familyUser experience improvement
1.0Initial version
* * +* +* +* +* +* +* +* +* +* * *
VersionChangesReason for Change
1.40.1The \ref Cy_SMIF_MemInit is changed. Corrected a false assertion during initialization in SFDP mode.
Minor documentation updates.
1.40The following functions are renamed:\n * Cy_SMIF_GetTxfrStatus into Cy_SMIF_GetTransferStatus;\n @@ -591,7 +601,7 @@ extern "C" { /** The Transfer width options for the command, data, the address and the mode. */ typedef enum { - CY_SMIF_WIDTH_SINGLE = 0U, /**< Normal SPI mode. */ + CY_SMIF_WIDTH_SINGLE = 0U, /**< Single SPI mode. */ CY_SMIF_WIDTH_DUAL = 1U, /**< Dual SPI mode. */ CY_SMIF_WIDTH_QUAD = 2U, /**< Quad SPI mode. */ CY_SMIF_WIDTH_OCTAL = 3U, /**< Octal SPI mode. */ @@ -614,7 +624,7 @@ typedef enum { /** * smif.spi_data[0] = DATA0, smif.spi_data[1] = DATA1, ..., smif.spi_data[7] = DATA7. - * This value is allowed for the SPI, DSPI, quad-SPI, dual quad-SPI, and octal-SPI modes. + * This value is allowed for the SPI, DSPI, QSPI, dual QSPI, and octal SPI modes. */ CY_SMIF_DATA_SEL0 = 0, /** @@ -624,7 +634,7 @@ typedef enum CY_SMIF_DATA_SEL1 = 1, /** * smif.spi_data[4] = DATA0, smif.spi_data[5] = DATA1, ..., smif.spi_data[7] = DATA3. - * This value is only allowed for the SPI, DSPI, quad-SPI and dual quad-SPI modes. + * This value is only allowed for the SPI, DSPI, QSPI and dual QSPI modes. */ CY_SMIF_DATA_SEL2 = 2, /** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h index 918b85f149..b4f1d2760d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.h -* \version 1.40 +* \version 1.40.1 * * \brief * This file provides the constants and parameter values for the memory-level diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index 7b80ad6739..f49264089b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 1.40.2 +* \version 1.50 * * Provides an API declaration of the sysclk driver. * @@ -104,6 +104,11 @@ * * * +* +* +* +* +* * * * @@ -1831,10 +1836,8 @@ typedef struct cy_en_csv_loss_window_t lossWindow; cy_en_csv_error_actions_t lossAction; } cy_stc_clkhf_csv_config_t; -/** \endcond */ -/** \cond INTERNAL */ -extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */ +#define altHfFreq (cy_BleEcoClockFreqHz) /** \endcond */ /** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h index b568337cdf..0d7777895b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib.h -* \version 2.40.1 +* \version 2.50 * * Provides an API declaration of the SysLib driver. * @@ -121,12 +121,6 @@ * * * -* -* -* -* -* -* * * * @@ -139,26 +133,25 @@ * * -* -* -* -* -* -* -* -* -* -* -* -* *
VersionChangesReason for Change
1.50\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.API enhancement.
1.40.2Update documentation based on collateral review feedback.User experience enhancement.Description of Deviation(s)
1.2RNo reliance shall be placed on undefined or unspecified behaviour.This specific behavior is explicitly covered in rule 20.1.
2.1RThis function contains a mixture of in-line assembler statements and C statements.The unions are used for CFSR, HFSR and SHCSR Fault Status Registers * content access as a word in code and as a structure during debug.
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
20.1RReserved identifiers, macros and functions in the standard library, shall not be -* defined, redefined or undefined.The driver defines the macros with leading underscores -* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.
* * \section group_syslib_changelog Changelog * * * +* +* +* +* * * * @@ -196,7 +189,7 @@ * * * -* +* * * * @@ -256,6 +249,7 @@ #include #include +#include "cy_utils.h" #include "cy_device.h" #include "cy_device_headers.h" @@ -463,87 +457,7 @@ typedef enum #define CY_SYSLIB_DRV_VERSION_MAJOR 2 /** The driver minor version */ -#define CY_SYSLIB_DRV_VERSION_MINOR 40 - - -/******************************************************************************* -* Data manipulation defines -*******************************************************************************/ - -/** Get the lower 8 bits of a 16-bit value. */ -#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU)) -/** Get the upper 8 bits of a 16-bit value. */ -#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U)) - -/** Get the lower 16 bits of a 32-bit value. */ -#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU)) -/** Get the upper 16 bits of a 32-bit value. */ -#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U)) - -/** Swap the byte ordering of a 16-bit value */ -#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU))) - -/** Swap the byte ordering of a 32-bit value */ -#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \ - (((x) & 0x0000FF00U) << 8U) | ((x) << 24U))) - -/** Swap the byte ordering of a 64-bit value */ -#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \ - CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U)))) - - -/******************************************************************************* -* Memory model definitions -*******************************************************************************/ -#if defined(__ARMCC_VERSION) - /** To create cross compiler compatible code, use the CY_NOINIT, CY_SECTION, CY_UNUSED, CY_ALIGN - * attributes at the first place of declaration/definition. - * For example: CY_NOINIT uint32_t noinitVar; - */ - #if (__ARMCC_VERSION >= 6010050) - #define CY_NOINIT __attribute__ ((section(".noinit"))) - #else - #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) - #endif /* (__ARMCC_VERSION >= 6010050) */ - #define CY_SECTION(name) __attribute__ ((section(name))) - #define CY_UNUSED __attribute__ ((unused)) - #define CY_NOINLINE __attribute__ ((noinline)) - /* Specifies the minimum alignment (in bytes) for variables of the specified type. */ - #define CY_ALIGN(align) __ALIGNED(align) - #define CY_RAMFUNC_BEGIN __attribute__ ((section(".cy_ramfunc"))) - #define CY_RAMFUNC_END -#elif defined (__GNUC__) - #if defined (__clang__) - #define CY_NOINIT __attribute__ ((section("__DATA, __noinit"))) - #define CY_SECTION(name) __attribute__ ((section("__DATA, "name))) - #define CY_RAMFUNC_BEGIN __attribute__ ((section("__DATA, .cy_ramfunc"))) - #define CY_RAMFUNC_END - #else - #define CY_NOINIT __attribute__ ((section(".noinit"))) - #define CY_SECTION(name) __attribute__ ((section(name))) - #define CY_RAMFUNC_BEGIN __attribute__ ((section(".cy_ramfunc"))) - #define CY_RAMFUNC_END - #endif - - #define CY_UNUSED __attribute__ ((unused)) - #define CY_NOINLINE __attribute__ ((noinline)) - #define CY_ALIGN(align) __ALIGNED(align) -#elif defined (__ICCARM__) - #define CY_PRAGMA(x) _Pragma(#x) - #define CY_NOINIT __no_init - #define CY_SECTION(name) CY_PRAGMA(location = name) - #define CY_UNUSED - #define CY_NOINLINE CY_PRAGMA(optimize = no_inline) - #define CY_RAMFUNC_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc - #define CY_RAMFUNC_END CY_PRAGMA(diag_default = Ta023) - #if (__VER__ < 8010001) - #define CY_ALIGN(align) CY_PRAGMA(data_alignment = align) - #else - #define CY_ALIGN(align) __ALIGNED(align) - #endif /* (__VER__ < 8010001) */ -#else - #error "An unsupported toolchain" -#endif /* (__ARMCC_VERSION) */ +#define CY_SYSLIB_DRV_VERSION_MINOR 50 typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */ #if defined (__ICCARM__) @@ -600,130 +514,6 @@ typedef double float64_t; /**< Specific-length typedef for the basic numerical #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */ -/******************************************************************************* -* Macro Name: CY_GET_REG8(addr) -****************************************************************************//** -* -* Reads the 8-bit value from the specified address. This function can't be -* used to access the Core register, otherwise a fault occurs. -* -* \param addr The register address. -* -* \return The read value. -* -*******************************************************************************/ -#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) - - -/******************************************************************************* -* Macro Name: CY_SET_REG8(addr, value) -****************************************************************************//** -* -* Writes an 8-bit value to the specified address. This function can't be -* used to access the Core register, otherwise a fault occurs. -* -* \param addr The register address. -* -* \param value The value to write. -* -*******************************************************************************/ -#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) - - -/******************************************************************************* -* Macro Name: CY_GET_REG16(addr) -****************************************************************************//** -* -* Reads the 16-bit value from the specified address. -* -* \param addr The register address. -* -* \return The read value. -* -*******************************************************************************/ -#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) - - -/******************************************************************************* -* Macro Name: CY_SET_REG16(addr, value) -****************************************************************************//** -* -* Writes the 16-bit value to the specified address. -* -* \param addr The register address. -* -* \param value The value to write. -* -*******************************************************************************/ -#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) - - -/******************************************************************************* -* Macro Name: CY_GET_REG24(addr) -****************************************************************************//** -* -* Reads the 24-bit value from the specified address. -* -* \param addr The register address. -* -* \return The read value. -* -*******************************************************************************/ -#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \ - (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \ - (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U)) - - -/******************************************************************************* -* Macro Name: CY_SET_REG24(addr, value) -****************************************************************************//** -* -* Writes the 24-bit value to the specified address. -* -* \param addr The register address. -* -* \param value The value to write. -* -*******************************************************************************/ -#define CY_SET_REG24(addr, value) do \ - { \ - (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ - (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \ - (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \ - } \ - while(0) - - -/******************************************************************************* -* Macro Name: CY_GET_REG32(addr) -****************************************************************************//** -* -* Reads the 32-bit value from the specified register. The address is the little -* endian order (LSB in lowest address). -* -* \param addr The register address. -* -* \return The read value. -* -*******************************************************************************/ -#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) - - -/******************************************************************************* -* Macro Name: CY_SET_REG32(addr, value) -****************************************************************************//** -* -* Writes the 32-bit value to the specified register. The address is the little -* endian order (LSB in lowest address). -* -* \param addr The register address. -* -* \param value The value to write. -* -*******************************************************************************/ -#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) - - /** * \defgroup group_syslib_macros_assert Assert Classes and Levels * \{ @@ -764,155 +554,6 @@ typedef double float64_t; /**< Specific-length typedef for the basic numerical /** \} group_syslib_macros_assert */ -/******************************************************************************* -* Macro Name: CY_ASSERT -****************************************************************************//** -* -* The macro that evaluates the expression and, if it is false (evaluates to 0), -* the processor is halted. Cy_SysLib_AssertFailed() is called when the logical -* expression is false to store the ASSERT location and halt the processor. -* -* \param x The logical expression. Asserts if false. -* \note This macro is evaluated unless NDEBUG is not defined. -* If NDEBUG is defined, just empty do while cycle is generated for this -* macro for the sake of consistency and to avoid MISRA violation. -* NDEBUG is defined by default for a Release build setting and not defined -* for a Debug build setting. -* -*******************************************************************************/ -#if !defined(NDEBUG) - #define CY_ASSERT(x) do \ - { \ - if(!(x)) \ - { \ - Cy_SysLib_AssertFailed((char_t *) __FILE__, (uint32_t) __LINE__); \ - } \ - } while(0) -#else - #define CY_ASSERT(x) do \ - { \ - } while(0) -#endif /* !defined(NDEBUG) */ - - -/******************************************************************************* -* Macro Name: _CLR_SET_FLD32U -****************************************************************************//** -* -* The macro for setting a register with a name field and value for providing -* get-clear-modify-write operations. -* Returns a resulting value to be assigned to the register. -* -*******************************************************************************/ -#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) - - -/******************************************************************************* -* Macro Name: CY_REG32_CLR_SET -****************************************************************************//** -* -* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write -* operations with a name field and value and writes a resulting value -* to the 32-bit register. -* -*******************************************************************************/ -#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) - - -/******************************************************************************* -* Macro Name: _CLR_SET_FLD16U -****************************************************************************//** -* -* The macro for setting a 16-bit register with a name field and value for providing -* get-clear-modify-write operations. -* Returns a resulting value to be assigned to the 16-bit register. -* -*******************************************************************************/ -#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \ - ((uint16_t)_VAL2FLD(field, value)))) - - -/******************************************************************************* -* Macro Name: CY_REG16_CLR_SET -****************************************************************************//** -* -* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write -* operations with a name field and value and writes a resulting value -* to the 16-bit register. -* -*******************************************************************************/ -#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) - - -/******************************************************************************* -* Macro Name: _CLR_SET_FLD8U -****************************************************************************//** -* -* The macro for setting a 8-bit register with a name field and value for providing -* get-clear-modify-write operations. -* Returns a resulting value to be assigned to the 8-bit register. -* -*******************************************************************************/ -#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \ - ((uint8_t)_VAL2FLD(field, value)))) - - -/******************************************************************************* -* Macro Name: CY_REG8_CLR_SET -****************************************************************************//** -* -* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write -* operations with a name field and value and writes a resulting value -* to the 8-bit register. -* -*******************************************************************************/ -#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) - - -/******************************************************************************* -* Macro Name: _BOOL2FLD -****************************************************************************//** -* -* Returns a field mask if the value is not false. -* Returns 0, if the value is false. -* -*******************************************************************************/ -#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL) - - -/******************************************************************************* -* Macro Name: _FLD2BOOL -****************************************************************************//** -* -* Returns true, if the value includes the field mask. -* Returns false, if the value doesn't include the field mask. -* -*******************************************************************************/ -#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) - - -/******************************************************************************* -* Macro Name: CY_SYSLIB_DIV_ROUND -****************************************************************************//** -* -* Calculates a / b with rounding to the nearest integer, -* a and b must have the same sign. -* -*******************************************************************************/ -#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) - - -/******************************************************************************* -* Macro Name: CY_SYSLIB_DIV_ROUNDUP -****************************************************************************//** -* -* Calculates a / b with rounding up if remainder != 0, -* both a and b must be positive. -* -*******************************************************************************/ -#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) - - /****************************************************************************** * Constants *****************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index a762587bf2..85cd16688b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 4.40 +* \version 4.50 * * Provides the function definitions for the power management API. * @@ -724,6 +724,25 @@ *
VersionChangesReason for Change
2.50Moved following macros to the core library: +* CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32, +* CY_SWAP_ENDIAN64,CY_GET_REG8,CY_SET_REG8,CY_GET_REG16,CY_SET_REG16, +* CY_GET_REG24,CY_SET_REG24,CY_GET_REG32,CY_SET_REG32,_CLR_SET_FLD32U, +* CY_REG32_CLR_SET,_CLR_SET_FLD16U,CY_REG16_CLR_SET,_CLR_SET_FLD8U, +* CY_REG8_CLR_SET,_BOOL2FLD,_FLD2BOOL,CY_SYSLIB_DIV_ROUND, +* CY_SYSLIB_DIV_ROUNDUP,CY_NOINIT,CY_SECTION,CY_UNUSED,CY_NOINLINE, +* CY_ALIGN,CY_RAMFUNC_BEGIN,CY_RAMFUNC_END. +* Use at least version 1.1 of the core library: https://github.com/cypresssemiconductorco/core-lib. +* Improve PDL code base.
2.40.1Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.Removed the IAR compiler warning.Driver library directory-structure simplification.
Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SETAdded the following macros: CY_REG32_CLR_SET, _CLR_SET_FLD16U, CY_REG16_CLR_SET, _CLR_SET_FLD8U, CY_REG8_CLR_SETRegister access simplification.
* * +* +* +* +* +* +* +* +* +* * *
VersionChangesReason for Change
4.50Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. +* Updated the mechanism for saving/restoring not retained UDB and clock +* registers in the Cy_SysPm_CpuEnterDeepSleep() function. +*
+* Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function to use values +* stored into the variable instead of reading them directly from +* SFLASH memory. +* +* SFLASH memory can be unavailable to read the correct value after +* a Deep sleep state on the CY8C6xx6 and CY8C6xx7 devices. +*
4.40 * Fixed \ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), and @@ -1223,7 +1242,7 @@ extern "C" { #define CY_SYSPM_DRV_VERSION_MAJOR 4 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 40 +#define CY_SYSPM_DRV_VERSION_MINOR 50 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) @@ -1705,6 +1724,9 @@ typedef struct uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN0_REG; /**< UDB bank QCLK_EN0 register */ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN1_REG; /**< UDB bank QCLK_EN1 register */ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN2_REG; /**< UDB bank QCLK_EN2 register */ + + uint32_t CY_SYSPM_CM0_CLOCK_CTL_REG; /**< CPUSS CM0+ clock control register */ + uint32_t CY_SYSPM_CM4_CLOCK_CTL_REG; /**< CPUSS CM4 clock control register */ } cy_stc_syspm_backup_regs_t; /** \} group_syspm_data_structures */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h index f6a68c2d04..e8a12c1b9f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy_trigmux.h -* \version 1.20 +* \version 1.20.1 * * This file provides constants and parameter values for the Trigger multiplexer driver. * @@ -115,53 +115,51 @@ * * For PERI_ver1: * Step 1. Find the trigger group number in the Trigger Group Inputs section of the device -* configuration header file that corresponds to the output of the first peripheral block. -* For example, TRIG11_IN_TCPWM0_TR_OVERFLOW0 input of the reduction multiplexers belongs -* to Trigger Group 11. +* configuration header file that corresponds to the output of the source peripheral block. +* For example, TRIG11_IN_TCPWM0_TR_OVERFLOW0 (see \ref group_trigmux_red_in_enums and the diagram +* at the top of this section) input of the Reduction multiplexers belongs to Trigger Group 11. * * Step 2. Find the trigger group number in the Trigger Group Outputs section of the device -* configuration header file that corresponds to the input of the second peripheral block. -* For example, TRIG0_OUT_CPUSS_DW0_TR_IN0 output of the distribution multiplexer belongs to -* Trigger Group 0. +* configuration header file that corresponds to the input of the destination peripheral block. +* For example, TRIG0_OUT_CPUSS_DW0_TR_IN0 (see \ref group_trigmux_dst_out_enums) output of the +* Distribution multiplexer belongs to Trigger Group 0. * * Step 3. Find the same trigger group number in the Trigger Group Inputs section of the * device configuration header file that corresponds to the trigger group number found in -* Step 1. Select the reduction multiplexer output that can be connected to the trigger group -* found in Step 2. For example, TRIG0_IN_TR_GROUP11_OUTPUT0 means that Reduction Multiplexer -* Output 15 of Trigger Group 13 can be connected to Trigger Group 0. +* Step 1. Select the Reduction multiplexer output that can be connected to the trigger group +* found in Step 2. For example, TRIG0_IN_TR_GROUP11_OUTPUT0 (see \ref group_trigmux_dst_in_enums) +* means that Reduction Multiplexer Output 0 of Trigger Group 11 can be connected to +* Trigger Group 0. * * Step 4. Find the same trigger group number in the Trigger Group Outputs section of the * device configuration header file that corresponds to the trigger group number found in Step 2. * Select the distribution multiplexer input that can be connected to the trigger group found -* in Step 1. For example, TRIG11_OUT_TR_GROUP0_INPUT9 means that the Distribution Multiplexer -* Input 42 of Trigger Group 0 can be connected to the output of the reduction multiplexer -* in Trigger Group 13 found in Step 3. +* in Step 1. For example, TRIG11_OUT_TR_GROUP0_INPUT9 (see \ref group_trigmux_red_out_enums) +* means that the Distribution Multiplexer Input 9 of Trigger Group 0 can be connected to the +* output of the Reduction multiplexer in Trigger Group 11 found in Step 3. * * Step 5. Call Cy_TrigMux_Connect() API twice: the first call - with the constants for the * inTrig and outTrig parameters found in Steps 1 and Step 4, the second call - with the * constants for the inTrig and outTrig parameters found in Steps 2 and Step 3. -* For example, -* Cy_TrigMux_Connect(TRIG11_IN_TCPWM0_TR_OVERFLOW0, TRIG11_OUT_TR_GROUP0_INPUT9, -* false, TRIGGER_TYPE_LEVEL); -* Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP11_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, -* false, TRIGGER_TYPE_EDGE); +* For example: +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_PERI_ver1 * * For PERI_ver2: * Step 1. Find the trigger group number in the Trigger Group Inputs section of the device -* configuration header file that corresponds to the output of the first peripheral block. -* For example, TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 TrigMux input belongs to Trigger Group 0. -* It is the same TCPWM0 counter 0 overflow output (as in the example for PERI_ver1). +* configuration header file that corresponds to the output of the source peripheral block. +* For example, TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 (see \ref group_trigmux_in_enums) TrigMux +* input belongs to Trigger Group 0. It is the same TCPWM0 counter 0 overflow output +* (as in the example for PERI_ver1). * * Step 2. Find the same trigger group number in the Trigger Group Outputs section of the * device configuration header file that corresponds to the trigger group number found in -* Step 1. Select the TrigMux output that can be connected to the second peripheral block. -* For example, TRIG_OUT_MUX_0_PDMA0_TR_IN0 means that the trigger multiplexer -* Output 0 of Trigger Group 0 can be connected to the DW0 channel 0 trigger input -* (the same DMA channel as mentioned in the example for PERI_ver1). +* Step 1. Select the TrigMux output that can be connected to the destination peripheral block. +* For example, TRIG_OUT_MUX_0_PDMA0_TR_IN0 (see \ref group_trigmux_out_enums) means that the +* trigger multiplexer Output 0 of Trigger Group 0 can be connected to the DW0 channel 0 trigger +* input (the same DMA channel as mentioned in the example for PERI_ver1). * * Step 3. Call Cy_TrigMux_Connect() API once: -* Cy_TrigMux_Connect(TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0, TRIG_OUT_MUX_0_PDMA0_TR_IN0, -* false, TRIGGER_TYPE_EDGE); +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_PERI_ver2 * * \section group_trigmux_more_information More Information * For more information on the TrigMux peripheral, refer to the technical reference manual (TRM). @@ -173,6 +171,11 @@ * * * +* +* +* +* +* * * * @@ -217,6 +220,21 @@ * \defgroup group_trigmux_macros Macros * \defgroup group_trigmux_functions Functions * \defgroup group_trigmux_enums Enumerated Types +* \{ +* \defgroup group_trigmux_red_enums Reduction Trigger Mutiplexers +* \{ +* \defgroup group_trigmux_red_in_enums Reduction Trigger Mutiplexer Inputs +* \defgroup group_trigmux_red_out_enums Reduction Trigger Mutiplexer Outputs +* \} +* \defgroup group_trigmux_dst_enums Distribution Trigger Mutiplexers +* \{ +* \defgroup group_trigmux_dst_in_enums Distribution Trigger Mutiplexer Inputs +* \defgroup group_trigmux_dst_out_enums Distribution Trigger Mutiplexer Outputs +* \} +* \defgroup group_trigmux_in_enums Trigger Mutiplexer Inputs +* \defgroup group_trigmux_out_enums Trigger Mutiplexer Outputs +* \defgroup group_trigmux_1to1_enums One-To-One Trigger Lines +* \} */ #if !defined(CY_TRIGMUX_H) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h index 8bba1d06b5..bc64ce9c77 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_wdt.h -* \version 1.10.1 +* \version 1.20 * * This file provides constants and parameter values for the WDT driver. * @@ -191,6 +191,11 @@ *
VersionChangesReason for Change
1.20.1Documentation is extended/improved.Enhancement based on usability feedback.
1.20Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
* * +* +* +* +* +* * *
VersionChangesReason for Change
1.20Added a new API function \ref Cy_WDT_IsEnabled() Enhancement based on usability feedback.
1.10.1Added info that the WDT lock state is not retained during * system Deep Sleep power mode. @@ -251,6 +256,7 @@ #include #include "cy_device_headers.h" #include "cy_device.h" +#include "cy_syslib.h" #if defined(__cplusplus) extern "C" { @@ -270,7 +276,7 @@ extern "C" { #define CY_WDT_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_WDT_DRV_VERSION_MINOR 10 +#define CY_WDT_DRV_VERSION_MINOR 20 /** The internal define for the first iteration of WDT unlocking */ #define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01U << 30U) @@ -364,6 +370,23 @@ __STATIC_INLINE void Cy_WDT_Disable(void) } +/******************************************************************************* +* Function Name: Cy_WDT_IsEnabled +****************************************************************************//** +* +* Reports an enable/disable state of the Watchdog timer. +* +* \return +* - true - if the timer is enabled +* - false - if the timer is disabled +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_WDT_IsEnabled(void) +{ + return _FLD2BOOL(SRSS_WDT_CTL_WDT_EN, SRSS_WDT_CTL); +} + + /******************************************************************************* * Function Name: Cy_WDT_GetMatch ****************************************************************************//** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S index 8bb4a96a3b..16e71def22 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; \file cy_syslib_mdk.s -; \version 2.40 +; \version 2.50 ; ; \brief Assembly routines for ARMCC. ; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S index 2b78215364..68249d7077 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib_a_clang.S -* \version 2.40 +* \version 2.50 * * \brief Assembly routines for Apple Clang. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S index 084ba8649c..1d6e16eba2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib_gcc.S -* \version 2.40 +* \version 2.50 * * \brief Assembly routines for GNU GCC. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S index 37d79a089d..8847749100 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib_iar.s -* \version 2.40 +* \version 2.50 * * \brief Assembly routines for IAR Embedded Workbench IDE. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c index 8edd588d0b..8f92bd1df2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.20 +* \version 3.30 * * \brief * This driver provides the source code for API BLE ECO clock. @@ -276,9 +276,11 @@ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_ /* If clock source for RCB is PeriClk */ if((BLE_BLESS_LL_CLK_EN & BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk) == 0U) { - if(cy_PeriClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ) + uint32_t periClkFreqHz = Cy_SysClk_ClkPeriGetFrequency(); + + if(periClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ) { - rcbDivider = (cy_PeriClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1U; + rcbDivider = (periClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1U; } } else @@ -413,7 +415,7 @@ void Cy_BLE_EcoReset(void) { /* Initiate Soft Reset */ BLE_BLESS_LL_CLK_EN |= BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk; - altHfFreq = 0UL; /* Reset the BLE ECO frequency */ + cy_BleEcoClockFreqHz = 0UL; /* Reset the BLE ECO frequency */ } @@ -785,7 +787,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq temp |= (uint16_t)(CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT); /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */ - altHfFreq = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv); + cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv); } else { @@ -802,7 +804,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq temp |= (uint16_t)(CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT); /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */ - altHfFreq = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv); + cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv); } temp |= (uint16_t)(blerdDivider << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index 4c7b385806..f5bd30c9d4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.c -* \version 3.30.2 +* \version 3.30.3 * * \brief * Provides the public functions for the API for the PSoC 6 Flash Driver. @@ -143,9 +143,7 @@ typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *contex /* The default delay time value */ #define CY_FLASH_DEFAULT_DELAY (150UL) /* Calculates the time in microseconds to wait for the number of the CM0P ticks */ - #define CY_FLASH_DELAY_CORRECTIVE(ticks) ((((uint32)Cy_SysClk_ClkPeriGetDivider() + 1UL) * \ - (Cy_SysClk_ClkSlowGetDivider() + 1UL) * (ticks) * 1000UL)\ - / ((uint32_t)cy_Hfclk0FreqHz / 1000UL)) + #define CY_FLASH_DELAY_CORRECTIVE(ticks) (((ticks) * 1000UL) / (Cy_SysClk_ClkSlowGetFrequency() / 1000UL)) /* Number of the CM0P ticks for StartProgram function delay corrective time */ #define CY_FLASH_START_PROGRAM_DELAY_TICKS (6000UL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c index f5a89837a3..29acc37e1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sar.c -* \version 1.20.1 +* \version 1.20.2 * * Provides the public functions for the API for the SAR driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c index 8cfb4dba11..14cc5ece9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.c -* \version 2.30.1 +* \version 2.40 * * Provides common API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c index e2f30d46f4..8ab2a55508 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.c -* \version 2.30.1 +* \version 2.40 * * Provides EZI2C API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c index cbef087c42..a1137e740a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.c -* \version 2.30.1 +* \version 2.40 * * Provides I2C API implementation of the SCB driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c index 74b498d72e..0706dff07d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.c -* \version 2.30.1 +* \version 2.40 * * Provides SPI API implementation of the SCB driver. * @@ -605,7 +605,9 @@ cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuffer, voi cy_stc_scb_spi_context_t *context) { CY_ASSERT_L1(NULL != context); + #if !defined(NDEBUG) CY_ASSERT_L1(CY_SCB_SPI_INIT_KEY == context->initKey); + #endif CY_ASSERT_L1(CY_SCB_SPI_IS_BUFFER_VALID(txBuffer, rxBuffer, size)); cy_en_scb_spi_status_t retStatus = CY_SCB_SPI_TRANSFER_BUSY; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c index 02babb2603..f7aabf5baa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.c -* \version 2.30.1 +* \version 2.40 * * Provides UART API implementation of the SCB driver. * @@ -34,6 +34,7 @@ extern "C" { static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context); static void HandleRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context); static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context); +static uint32_t SelectRxFifoLevel(CySCB_Type const *base); /******************************************************************************* @@ -453,12 +454,14 @@ cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_ void Cy_SCB_UART_StartRingBuffer(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context) { CY_ASSERT_L1(NULL != context); + #if !defined(NDEBUG) CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey); + #endif CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size)); if ((NULL != buffer) && (size > 0UL)) { - uint32_t halfFifoSize = (Cy_SCB_GetFifoSize(base) / 2UL); + uint32_t irqRxLevel = SelectRxFifoLevel(base); context->rxRingBuf = buffer; context->rxRingBufSize = size; @@ -466,13 +469,32 @@ void Cy_SCB_UART_StartRingBuffer(CySCB_Type *base, void *buffer, uint32_t size, context->rxRingBufTail = 0UL; /* Set up an RX interrupt to handle the ring buffer */ - Cy_SCB_SetRxFifoLevel(base, (size >= halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL)); + Cy_SCB_SetRxFifoLevel(base, (size >= irqRxLevel) ? (irqRxLevel - 1UL) : (size - 1UL)); Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); } } +/******************************************************************************* +* Function Name: SelectRxFifoLevel +****************************************************************************//** +* Select RX FIFO level as RTS level if it is valid (>0) or half of RX FIFO size +* in other case. +* +* \return +* The RX FIFO level. +* +*******************************************************************************/ +static uint32_t SelectRxFifoLevel(CySCB_Type const *base) +{ + uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + uint32_t rtsFifoLevel = Cy_SCB_UART_GetRtsFifoLevel(base); + + return ((rtsFifoLevel != 0UL ) ? (rtsFifoLevel) : (halfFifoSize)); +} + + /******************************************************************************* * Function Name: Cy_SCB_UART_StopRingBuffer ****************************************************************************//** @@ -615,7 +637,9 @@ void Cy_SCB_UART_ClearRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context) { CY_ASSERT_L1(NULL != context); + #if !defined(NDEBUG) CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey); + #endif CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size)); cy_en_scb_uart_status_t retStatus = CY_SCB_UART_RECEIVE_BUSY; @@ -705,7 +729,7 @@ cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint /* Set up a direct RX FIFO receive */ if (size > 0UL) { - uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + uint32_t irqRxLevel = SelectRxFifoLevel(base); /* Set up context */ context->rxStatus = CY_SCB_UART_RECEIVE_ACTIVE; @@ -715,7 +739,7 @@ cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint context->rxBufIdx = numToCopy; /* Set the RX FIFO level to the trigger interrupt */ - Cy_SCB_SetRxFifoLevel(base, (size > halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL)); + Cy_SCB_SetRxFifoLevel(base, (size > irqRxLevel) ? (irqRxLevel - 1UL) : (size - 1UL)); /* Enable the RX interrupt sources to continue data reading */ Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RX_INTR); @@ -873,7 +897,9 @@ uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_co cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context) { CY_ASSERT_L1(NULL != context); + #if !defined(NDEBUG) CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey); + #endif CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size)); cy_en_scb_uart_status_t retStatus = CY_SCB_UART_TRANSMIT_BUSY; @@ -1218,7 +1244,7 @@ void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context) static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context) { uint32_t numCopied; - uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + uint32_t irqRxLevel = SelectRxFifoLevel(base); /* Get data from RX FIFO */ numCopied = Cy_SCB_UART_GetArray(base, context->rxBuf, context->rxBufSize); @@ -1232,8 +1258,8 @@ static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *conte if (NULL != context->rxRingBuf) { /* Adjust the level to proceed with the ring buffer */ - Cy_SCB_SetRxFifoLevel(base, (context->rxRingBufSize >= halfFifoSize) ? - (halfFifoSize - 1UL) : (context->rxRingBufSize - 1UL)); + Cy_SCB_SetRxFifoLevel(base, (context->rxRingBufSize >= irqRxLevel) ? + (irqRxLevel - 1UL) : (context->rxRingBufSize - 1UL)); Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); } @@ -1258,7 +1284,7 @@ static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *conte buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numCopied) : (2UL * numCopied))]; context->rxBuf = (void *) buf; - if (context->rxBufSize < halfFifoSize) + if (context->rxBufSize < irqRxLevel) { /* Set the RX FIFO level to trigger an interrupt */ Cy_SCB_SetRxFifoLevel(base, (context->rxBufSize - 1UL)); @@ -1285,7 +1311,7 @@ static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *conte *******************************************************************************/ static void HandleRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context) { - uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + uint32_t irqRxLevel = SelectRxFifoLevel(base); uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base); uint32_t locHead = context->rxRingBufHead; uint32_t rxData; @@ -1342,7 +1368,7 @@ static void HandleRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *contex /* Get free entries in the ring buffer */ numToCopy = context->rxRingBufSize - Cy_SCB_UART_GetNumInRingBuffer(base, context); - if (numToCopy < halfFifoSize) + if (numToCopy < irqRxLevel) { /* Adjust the level to copy to the ring buffer */ uint32_t level = (numToCopy > 0UL) ? (numToCopy - 1UL) : 0UL; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c index a236b0e4d9..0e9ef763f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_seglcd.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_seglcd.c -* \version 1.0 +* \version 1.0.1 * * \brief * Provides an API implementation of the SegLCD driver @@ -95,15 +95,15 @@ #define CY_SEGLCD_IS_LSCLK_VALID(lsClk) ((CY_SEGLCD_LSCLK_LF == (lsClk)) || \ (CY_SEGLCD_LSCLK_MF == (lsClk))) -#define CY_SEGLCD_FR_RATE_MIN (30) -#define CY_SEGLCD_FR_RATE_MAX (150) +#define CY_SEGLCD_FR_RATE_MIN (30U) +#define CY_SEGLCD_FR_RATE_MAX (150U) #define CY_SEGLCD_IS_RATE_VALID(frRate) (((frRate) >= CY_SEGLCD_FR_RATE_MIN) && ((frRate) <= CY_SEGLCD_FR_RATE_MAX)) #define CY_SEGLCD_CNTR_MAX (100UL) #define CY_SEGLCD_IS_CNTR_VALID(contrast) (((uint32_t)(contrast)) <= CY_SEGLCD_CNTR_MAX) -#define CY_SEGLCD_FREQ_MIN (10000) -#define CY_SEGLCD_FREQ_MAX (100000000) +#define CY_SEGLCD_FREQ_MIN (10000UL) +#define CY_SEGLCD_FREQ_MAX (100000000UL) #define CY_SEGLCD_IS_FREQ_VALID(freq) (((freq) >= CY_SEGLCD_FREQ_MIN) && ((freq) <= CY_SEGLCD_FREQ_MAX)) #define CY_SEGLCD_SPACE(disp) (((disp)->font->ascii) ? ' ' : CY_SEGLCD_NUM_BLANK) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c index 2c50865cf5..30cad1e32a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.c -* \version 1.40 +* \version 1.40.1 * * \brief * This file provides the source code for the SMIF driver APIs. @@ -281,7 +281,7 @@ void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelec * \param slaveSelect * Denotes the number of the slave device to which the transfer is made. * (0, 1, 2 or 4 - the bit defines which slave to enable) Two-bit enable is -* possible only for the Double Quad SPI mode. +* possible only for the double quad SPI mode. * * \param completeTxfr * Specifies if the slave select line must be de-asserted after transferring diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c index 557bbc5e6c..114c5e5d93 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.c -* \version 1.40 +* \version 1.40.1 * * \brief * This file provides the source code for the memory-level APIs of the SMIF driver. @@ -306,7 +306,6 @@ cy_en_smif_status_t Cy_SMIF_MemInit(SMIF_Type *base, CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(memCfg->slaveSelect)); CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(memCfg->dataSelect)); CY_ASSERT_L1(NULL != memCfg->deviceCfg); - CY_ASSERT_L2(MEM_ADDR_SIZE_VALID(memCfg->deviceCfg->numOfAddrBytes)); device = Cy_SMIF_GetDeviceBySlot(base, memCfg->slaveSelect); if (NULL != device) @@ -329,6 +328,8 @@ cy_en_smif_status_t Cy_SMIF_MemInit(SMIF_Type *base, sfdpRes |= ((uint32_t)CY_SMIF_SFDP_FAIL << idx); } } + /* Check the size of the smif memory slot address */ + CY_ASSERT_L2(MEM_ADDR_SIZE_VALID(memCfg->deviceCfg->numOfAddrBytes)); if (((uint32_t)CY_SMIF_SUCCESS == sfdpRet) && (0U != (memCfg->flags & CY_SMIF_FLAG_MEMORY_MAPPED))) @@ -634,7 +635,7 @@ bool Cy_SMIF_MemIsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t const *memDevic ****************************************************************************//** * * This function enables the memory device for the quad mode of operation. -* This command must be executed before sending Quad SPI commands to the +* This command must be executed before sending quad SPI commands to the * memory device. * * \note In the dual quad mode, this API is called for each memory. @@ -1182,7 +1183,7 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, * \param slaveSelect * Denotes the number of the slave device to which the transfer is made. * (0, 1, 2 or 4 - the bit defines which slave to enable). The two-bit enable -* is possible only for the Double Quad SPI mode. +* is possible only for the double quad SPI mode. * * \param size * The size of data to be received. Must be > 0 and not greater than 65536. @@ -2579,7 +2580,7 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Page Program Time */ device->programTime = SfdpGetPageProgramTime(sfdpBuffer); - /* The Read command for 3-byte addressing. The preference order Quad>Dual>SPI */ + /* The Read command for 3-byte addressing. The preference order quad > dual > single SPI */ cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd; cy_en_smif_protocol_mode_t pMode = SfdpGetReadCmdParams(sfdpBuffer, dataSelect, cmdRead); @@ -2715,7 +2716,7 @@ cy_en_smif_status_t Cy_SMIF_MemIsReady(SMIF_Type *base, cy_stc_smif_mem_config_t * The memory device configuration. * * \param isQuadEnabled -* This parameter is updated to indicate whether Quad mode is enabled (true) or +* This parameter is updated to indicate whether quad mode is enabled (true) or * not (false). The value is valid only when the function returns * CY_SMIF_SUCCESS. * @@ -2743,7 +2744,7 @@ cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_co *isQuadEnabled = false; if(CY_SMIF_SUCCESS == status) { - /* Check whether Quad mode is already enabled or not */ + /* Check whether quad mode is already enabled or not */ *isQuadEnabled = (maskQE == (readStatus & maskQE)); } @@ -2756,7 +2757,7 @@ cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_co ****************************************************************************//** * * Sets the QE (QUAD Enable) bit in the external memory -* configuration register to enable Quad SPI mode. +* configuration register to enable quad SPI mode. * This is a blocking function, it will block the execution flow until * the command transmission is completed. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c index 6d49d85fc7..73688148e5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 1.40.2 +* \version 1.50 * * Provides an API implementation of the sysclk driver. * @@ -1789,10 +1789,6 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t /* ========================= clkHf[n] SECTION ========================= */ /* ========================================================================== */ -/** \cond INTERNAL */ -uint32_t altHfFreq = 0UL; /* Internal storage for BLE ECO frequency user setting */ -/** \endcond */ - /** * \addtogroup group_sysclk_clk_hf_funcs * \{ @@ -1844,9 +1840,11 @@ uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) freq = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL; break; + #if defined(CY_IP_MXBLESS) case CY_SYSCLK_CLKPATH_IN_ALTHF: - freq = altHfFreq; + freq = cy_BleEcoClockFreqHz; break; + #endif /* CY_IP_MXBLESS */ case CY_SYSCLK_CLKPATH_IN_ILO: freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c index fbbab869c0..f2a231fd48 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib.c -* \version 2.40.1 +* \version 2.50 * * Description: * Provides system API implementation for the SysLib driver. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index 7b1244edfe..828d53fcfc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 4.40 +* \version 4.50 * * This driver provides the source code for API power management. * @@ -31,7 +31,7 @@ /******************************************************************************* * Internal Functions *******************************************************************************/ -static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor); +static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor); static void SetReadMarginTrimUlp(void); static void SetReadMarginTrimLp(void); @@ -62,17 +62,20 @@ static bool IsVoltageChangePossible(void); /* Mask for both slow and fast mask clock dividers */ #define SYSPM_CLK_DIV_MASK (SYSPM_FAST_CLK_DIV_Msk | SYSPM_SLOW_CLK_DIV_Msk) - - #if (CY_CPU_CORTEX_M4) - #define CUR_CORE_DP_MASK (0x01UL) - #define OTHER_CORE_DP_MASK (0x02UL) - #else - #define CUR_CORE_DP_MASK (0x02UL) - #define OTHER_CORE_DP_MASK (0x01UL) - #endif - #endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ + +#if (CY_CPU_CORTEX_M4) + #define CUR_CORE_DP_MASK (0x01UL << 28u) + #define OTHER_CORE_DP_MASK (0x02UL << 28u) +#else + #define CUR_CORE_DP_MASK (0x02UL << 28u) + #define OTHER_CORE_DP_MASK (0x01UL << 28u) +#endif + +#define SYSPM_IPC_STRUCT_ADDR_MASK (0x0FFFFFFFUL) +#define SYSPM_IPC_STRUCT_UDB_DP_MASK (0x04UL << 28u) + /* The define for the current active bus master */ #if (CY_CPU_CORTEX_M0P) #define ACTIVE_BUS_MASTER CPUSS_MS_ID_CM0 @@ -278,9 +281,6 @@ static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {NULL, NULL, /* The array of the pointers to failed callback */ static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL}; -/* Structure for registers that should retain while Deep Sleep mode */ -static cy_stc_syspm_backup_regs_t bkpRegs; - #if (CY_CPU_CORTEX_M4) /* Global boolean variable used to clear the Event Register of the CM4 core */ static bool wasEventSent = false; @@ -635,32 +635,12 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) * Selects wait for action. See \ref cy_en_syspm_waitfor_t. * * \sideeffect -* This side effect is applicable only for devices with a UDBs. -* You can obtain unpredictable behavior of the UDB block after the device wakeup -* from system Deep Sleep. -* Unpredictable behavior scenario: -* * The first CPU saves non-retained UDB configuration registers and goes into -* the CPU Deep Sleep (Cy_SysPm_CpuEnterDeepSleep() function). -* * These non-retained UDB configuration registers are modified in runtime by -* another (second) active CPU. -* * The second CPU saves non-retained UDB configuration registers and goes into -* the CPU Deep Sleep (Cy_SysPm_CpuEnterDeepSleep() function). -* These conditions save different values of the non-retained UDB configuration -* registers. On the first CPU wakeup (system wakeup from Deep Sleep), these -* registers are restored by the values saved on the first CPU. After the -* second CPU wakeup, these registers are "reconfigured" by the values saved on -* the second CPU. -* Be aware of this situation. -* -* \sideeffect * For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the * CM4 CPU after wakeup from WFE. * * \sideeffect -* This side effect is applicable only for rev-08 of the CY8CKIT-062. -* This function changes the slow and fast clock dividers to -* SYSPM_CLK_DIVIDER right before entering into system Deep Sleep and restores -* these dividers after wakeup. +* This function changes the slow and fast clock dividers right before +* entering into system Deep Sleep and restores these dividers after wakeup. * * \return * Entered status, see \ref cy_en_syspm_status_t. @@ -683,12 +663,18 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) { + /* Structure for registers that should retain while Deep Sleep mode */ + static cy_stc_syspm_backup_regs_t bkpRegs; + uint32_t interruptState; uint32_t cbDeepSleepRootIdx = (uint32_t) CY_SYSPM_DEEPSLEEP; + uint32_t ddftStructData = 0UL; + uint8_t deviceRev; cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); + deviceRev = Cy_SysLib_GetDeviceRevision(); /* Call the registered callback functions with the CY_SYSPM_CHECK_READY * parameter */ @@ -703,9 +689,6 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) */ if (retVal == CY_SYSPM_SUCCESS) { - /* System Deep Sleep indicator */ - bool wasSystemDeepSleep = false; - /* Call the registered callback functions with the * CY_SYSPM_BEFORE_TRANSITION parameter */ @@ -715,27 +698,67 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_BEFORE_TRANSITION); } - if (0U != cy_device->udbPresent) + /* Preparation for the System Deep Sleep mode */ + + /* Acquire the IPC to prevent changing of the shared resources at the same time */ + while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) { - /* Check whether the UDB disabled on MMIO level */ - if (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED)) - { - /* Save non-retained registers */ - Cy_SysPm_SaveRegisters(&bkpRegs); - } + /* Wait until the IPC structure is released by another CPU */ } + ddftStructData = REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); + + if (0U != (ddftStructData & OTHER_CORE_DP_MASK)) + { + ddftStructData &= ~SYSPM_IPC_STRUCT_ADDR_MASK; + + Cy_SysPm_SaveRegisters(&bkpRegs); + + #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE + if (deviceRev == CY_SYSLIB_DEVICE_REV_0A) + { + /* Increase the clock divider for the slow and fast clocks to SYSPM_CLK_DIVIDER */ + CPUSS_CM0_CLOCK_CTL = + _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, SYSPM_CLK_DIVIDER); + + CPUSS_CM4_CLOCK_CTL = + _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, SYSPM_CLK_DIVIDER); + } + else + #endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ + { + /* Set the clock divider equal to 2 for the slow and fast clocks */ + CPUSS_CM0_CLOCK_CTL = + _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, 1); + + CPUSS_CM4_CLOCK_CTL = + _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, 1); + } + + ddftStructData |= (uint32_t) &bkpRegs; + } + + ddftStructData |= CUR_CORE_DP_MASK; + + /* Update pointer to the latest saved structure */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = ddftStructData; + + /* Release the IPC */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; + + /* Read the release value to make sure it is set */ + (void) REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); + /* Different device families and revisions have a different Deep Sleep entries */ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { /* The CPU enters Deep Sleep and wakes up in the RAM */ - wasSystemDeepSleep = EnterDeepSleepRam(waitFor); + EnterDeepSleepRam(waitFor); } else { #if (CY_CPU_CORTEX_M0P) - /* Check if there is a pending syscall */ if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false) { @@ -744,7 +767,6 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) } else #endif /* (CY_CPU_CORTEX_M0P) */ - { #if (CY_CPU_CORTEX_M4) /* Repeat the WFI/WFE instruction if a wake up was not intended. @@ -772,31 +794,31 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) } } - if (0U != cy_device->udbPresent) + /* Acquire the IPC to prevent changing of the shared resources at the same time */ + while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) { - /* Do not restore the UDBs if there was no system Deep Sleep mode or - * UDBs are disabled on MMIO level - */ - if (wasSystemDeepSleep && (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED))) - { - cy_stc_syspm_backup_regs_t *ptrRegs; - - #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A) - { - ptrRegs = &bkpRegs; - } - else - #endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ - { - ptrRegs = (cy_stc_syspm_backup_regs_t *) REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); - } - - /* Restore non-retained registers */ - Cy_SysPm_RestoreRegisters(ptrRegs); - } + /* Wait until the IPC structure is released by another CPU */ } + ddftStructData = REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); + + if (0U != (ddftStructData & OTHER_CORE_DP_MASK)) + { + cy_stc_syspm_backup_regs_t *ptrRegs; + + ptrRegs = (cy_stc_syspm_backup_regs_t *) (SYSPM_IPC_STRUCT_ADDR_MASK & ddftStructData); + + /* Restore saved registers */ + Cy_SysPm_RestoreRegisters(ptrRegs); + } + ddftStructData &= ~CUR_CORE_DP_MASK; + + /* Update pointer to the latest saved structure */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = ddftStructData; + + /* Release the IPC */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; + Cy_SysLib_ExitCriticalSection(interruptState); } @@ -2591,7 +2613,7 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, */ if(retVal == CY_SYSPM_FAIL) { - failedCallback[(uint32_t) type] = lastExecutedCallback; + failedCallback[(uint32_t) type] = lastExecutedCallback; } else { @@ -2813,16 +2835,12 @@ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_ * Function Name: Cy_SysPm_SaveRegisters ****************************************************************************//** * -* Saves non-retained UDB registers before system entering system Deep Sleep. +* Saves non-retained UDB registers and the slow and fast clock dividers before +* system entering system Deep Sleep. * Must be called if programmable logic or function are implemented in the UDB * array. -* -* \warning -* Only one CPU on dual CPU devices should call this function. If both CPUs call -* this function the UDB state restored may be inconsistent with the expected -* state when restored. * -* Cypress ID #280370. +* Cypress ID #280370, #1451. * * \param regs * The structure where the registers are saved. @@ -2836,15 +2854,21 @@ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) CY_ASSERT_L1(NULL != regs); /* Save the registers before Deep Sleep */ - regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG = UDB_UDBIF_BANK_CTL; + regs->CY_SYSPM_CM0_CLOCK_CTL_REG = CPUSS_CM0_CLOCK_CTL; + regs->CY_SYSPM_CM4_CLOCK_CTL_REG = CPUSS_CM4_CLOCK_CTL; - regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG = UDB_BCTL_MDCLK_EN; - regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG = UDB_BCTL_MBCLK_EN; - regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG = UDB_BCTL_BOTSEL_L; - regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG = UDB_BCTL_BOTSEL_U; - regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG = UDB_BCTL_QCLK_EN_0; - regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG = UDB_BCTL_QCLK_EN_1; - regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG = UDB_BCTL_QCLK_EN_2; + if ((0U != cy_device->udbPresent) && (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED))) + { + regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG = UDB_UDBIF_BANK_CTL; + + regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG = UDB_BCTL_MDCLK_EN; + regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG = UDB_BCTL_MBCLK_EN; + regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG = UDB_BCTL_BOTSEL_L; + regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG = UDB_BCTL_BOTSEL_U; + regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG = UDB_BCTL_QCLK_EN_0; + regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG = UDB_BCTL_QCLK_EN_1; + regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG = UDB_BCTL_QCLK_EN_2; + } } @@ -2852,20 +2876,16 @@ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) * Function Name: Cy_SysPm_RestoreRegisters ****************************************************************************//** * -* Restores non-retained UDB registers before system entering system Deep Sleep. +* Restores non-retained UDB registers and the slow and fast clock dividers +* before system entering system Deep Sleep. * Must be called if programmable logic or function are implemented in the UDB * array. * -* \warning -* Only one CPU on dual CPU devices should call this function. If both CPUs call -* this function the UDB state restored may be inconsistent with the expected -* state when restored. -* -* Cypress ID #280370. +* Cypress ID #280370, #1451. * * \param regs * The structure with data stored (using Cy_SysPm_SaveRegisters()) into the -* required non-retained registers after Deep Sleep. +* required registers after Deep Sleep. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_SaveRestoreRegisters @@ -2876,15 +2896,21 @@ void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) CY_ASSERT_L1(NULL != regs); /* Restore the registers after Deep Sleep */ - UDB_BCTL_MDCLK_EN = regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG; - UDB_BCTL_MBCLK_EN = regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG; - UDB_BCTL_BOTSEL_L = regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG; - UDB_BCTL_BOTSEL_U = regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG; - UDB_BCTL_QCLK_EN_0 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG; - UDB_BCTL_QCLK_EN_1 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG; - UDB_BCTL_QCLK_EN_2 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG; + CPUSS_CM0_CLOCK_CTL = regs->CY_SYSPM_CM0_CLOCK_CTL_REG; + CPUSS_CM4_CLOCK_CTL = regs->CY_SYSPM_CM4_CLOCK_CTL_REG; - UDB_UDBIF_BANK_CTL = regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG; + if ((0U != cy_device->udbPresent) && (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED))) + { + UDB_BCTL_MDCLK_EN = regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG; + UDB_BCTL_MBCLK_EN = regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG; + UDB_BCTL_BOTSEL_L = regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG; + UDB_BCTL_BOTSEL_U = regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG; + UDB_BCTL_QCLK_EN_0 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG; + UDB_BCTL_QCLK_EN_1 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG; + UDB_BCTL_QCLK_EN_2 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG; + + UDB_UDBIF_BANK_CTL = regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG; + } } @@ -2909,64 +2935,11 @@ void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) #else CY_SECTION(".cy_ramfunc") CY_NOINLINE #endif -static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) +static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) { - /* Store the address of the IPC7 acquire register into the RAM */ - volatile uint32_t *ipcAcquire = ((uint32_t *) (®_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))); - /* Store the address of the Deep Sleep indicator into the RAM */ volatile uint32_t *delayDoneFlag = &FLASHC_BIST_DATA_0; - - /* Indicator of System Deep Sleep mode */ - bool retVal = false; - /* Acquire the IPC to prevent changing of the shared resources at the same time */ - while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) - { - /* Wait until the IPC structure is released by another CPU */ - } - -#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A) - { - /* Set the flag that the current CPU entered Deep Sleep */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) |= CUR_CORE_DP_MASK; - - /* Change the slow and fast clock dividers only under the condition that - * the other CPU is already in Deep Sleep. Cypress ID #284516 - */ - if (0U != (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & OTHER_CORE_DP_MASK)) - { - /* Get the divider values of the slow and high clocks and store them into - * the IPC data register - */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = - (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & ((uint32_t) ~(SYSPM_CLK_DIV_MASK))) | - (((uint32_t)(_FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS_CM0_CLOCK_CTL) << SYSPM_SLOW_CLK_DIV_Pos)) | - ((uint32_t)(_FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS_CM4_CLOCK_CTL) << SYSPM_FAST_CLK_DIV_Pos))); - - /* Increase the clock divider for the slow and fast clocks to SYSPM_CLK_DIVIDER */ - CPUSS_CM0_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, SYSPM_CLK_DIVIDER); - - CPUSS_CM4_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, SYSPM_CLK_DIVIDER); - - /* Read the divider value to make sure it is set */ - (void) CPUSS_CM0_CLOCK_CTL; - (void) CPUSS_CM4_CLOCK_CTL; - } - } - else -#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ - { - /* Update pointer to the latest saved UDB structure */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (uint32_t) &bkpRegs; - } - - /* Release the IPC */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; - #if (CY_CPU_CORTEX_M4) /* Store the address of the CM4 power status register */ @@ -3006,81 +2979,41 @@ static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, (*cpussCm4PwrCtlAddr)) == CM4_PWR_STS_RETAINED); #endif /* (CY_CPU_CORTEX_M4) */ - /* Acquire the IPC to prevent changing of the shared resources at the same time */ - while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, (*ipcAcquire))) + /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is + * cleared. Cypress ID #288510 + */ + if (*delayDoneFlag == NEED_DELAY) { - /* Wait until the IPC structure is released by another CPU */ - } + uint32_t ddftSlowCtl; + uint32_t clkOutputSlow; + uint32_t ddftFastCtl; -#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A) - { - /* Read and change the slow and fast clock dividers only under the condition - * that the other CPU is already in Deep Sleep. Cypress ID #284516 - */ - if (0U != (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & OTHER_CORE_DP_MASK)) + /* Save timer configuration */ + ddftSlowCtl = SRSS_TST_DDFT_SLOW_CTL_REG; + clkOutputSlow = SRSS_CLK_OUTPUT_SLOW; + ddftFastCtl = SRSS_TST_DDFT_FAST_CTL_REG; + + /* Configure the counter to be sourced by IMO */ + SRSS_TST_DDFT_SLOW_CTL_REG = SRSS_TST_DDFT_SLOW_CTL_MASK; + SRSS_CLK_OUTPUT_SLOW = CLK_OUTPUT_SLOW_MASK; + SRSS_TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_MASK; + + /* Load the down-counter to count the 10 us */ + SRSS_CLK_CAL_CNT1 = IMO_10US_DELAY; + + while (0U == (SRSS_CLK_CAL_CNT1 & SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk)) { - /* Restore the clock dividers for the slow and fast clocks */ - CPUSS_CM0_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, - (_FLD2VAL(SYSPM_SLOW_CLK_DIV, REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))); - - CPUSS_CM4_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, - (_FLD2VAL(SYSPM_FAST_CLK_DIV, REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))); - - retVal = true; + /* Wait until the counter stops counting */ } - /* Indicate that the current CPU is out of Deep Sleep */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) &= ((uint32_t) ~CUR_CORE_DP_MASK); + /* Indicate that delay was done */ + *delayDoneFlag = DELAY_DONE; + + /* Restore timer configuration */ + SRSS_TST_DDFT_SLOW_CTL_REG = ddftSlowCtl; + SRSS_CLK_OUTPUT_SLOW = clkOutputSlow; + SRSS_TST_DDFT_FAST_CTL_REG = ddftFastCtl; } - else -#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ - { - /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is - * cleared. Cypress ID #288510 - */ - if (*delayDoneFlag == NEED_DELAY) - { - uint32_t ddftSlowCtl; - uint32_t clkOutputSlow; - uint32_t ddftFastCtl; - - /* Save timer configuration */ - ddftSlowCtl = SRSS_TST_DDFT_SLOW_CTL_REG; - clkOutputSlow = SRSS_CLK_OUTPUT_SLOW; - ddftFastCtl = SRSS_TST_DDFT_FAST_CTL_REG; - - /* Configure the counter to be sourced by IMO */ - SRSS_TST_DDFT_SLOW_CTL_REG = SRSS_TST_DDFT_SLOW_CTL_MASK; - SRSS_CLK_OUTPUT_SLOW = CLK_OUTPUT_SLOW_MASK; - SRSS_TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_MASK; - - /* Load the down-counter to count the 10 us */ - SRSS_CLK_CAL_CNT1 = IMO_10US_DELAY; - - while (0U == (SRSS_CLK_CAL_CNT1 & SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk)) - { - /* Wait until the counter stops counting */ - } - - /* Indicate that delay was done */ - *delayDoneFlag = DELAY_DONE; - - /* Restore timer configuration */ - SRSS_TST_DDFT_SLOW_CTL_REG = ddftSlowCtl; - SRSS_CLK_OUTPUT_SLOW = clkOutputSlow; - SRSS_TST_DDFT_FAST_CTL_REG = ddftFastCtl; - - retVal = true; - } - } - - /* Release the IPC */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; - - return retVal; } #if defined (__ICCARM__) #pragma diag_default=Ta023 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c index 6956f61ef1..0070b4f86b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_trigmux.c -* \version 1.20 +* \version 1.20.1 * * \brief Trigger mux API. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c index eca611f184..c8789b502e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_wdt.c -* \version 1.10.1 +* \version 1.20 * * This file provides the source code to the API for the WDT driver. * @@ -23,7 +23,6 @@ *******************************************************************************/ #include "cy_wdt.h" -#include "cy_syslib.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality index e7c3c53417..b6af7770d7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality @@ -168,10 +168,24 @@ + + + + + + + + + + + + - + + + @@ -192,11 +206,13 @@ + + @@ -209,6 +225,7 @@ + @@ -227,10 +244,23 @@ - + + + + + + + + + - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/csd-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/csd-2.0.cypersonality index cd5500b857..151f6207a9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/csd-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/csd-2.0.cypersonality @@ -253,10 +253,9 @@ - + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality index 16a02772f2..2b6285774e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality @@ -163,11 +163,10 @@ - + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality index c167619c24..b2b1538c45 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality @@ -199,14 +199,14 @@ - - 43012 - The 43012 devices - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/base/view.xml new file mode 100644 index 0000000000..04bf73b413 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/base/view.xml @@ -0,0 +1,17 @@ + + + 0x00000000 + 0x000 + 0 + 0 + + + Cypress + 0 + 1310720 + 106-WLBGA + 106 + 3200 + 4400 + The CYW43012TC0EKUBG device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/info.xml new file mode 100644 index 0000000000..fb6d339281 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/info.xml @@ -0,0 +1,6 @@ + + + CYW43012TC0EKUBG + The CYW43012TC0EKUBG devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/studio/presentation rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml new file mode 100644 index 0000000000..96da71097e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/base/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/base/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/info.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/info.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/info.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/studio/presentation rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml index 10d33fcedd..2efa5cdb8e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012TC0KFFBH/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml @@ -2,7 +2,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/base/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/base/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/info.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/info.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/info.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation new file mode 100644 index 0000000000..3d4d778bec --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation @@ -0,0 +1,2 @@ +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml index 08416896ec..2278e82177 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/CYW43012WKWBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml @@ -2,7 +2,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/hobto/ipblocks.cydata new file mode 100644 index 0000000000000000000000000000000000000000..2c1caa018d2c41a14d5efbc248cad68ec5f785b6 GIT binary patch literal 531 zcmWFt_IGv;a&-*x4{~t~adh+aagF&@QIuL-%)r9XJ1Nlru!2bI{hy*w_E|@LJvifH zYU~x0NF#ZlFKZL0_$F~L*>LLL-VN7EE=zuQ*-`U+&TQdj#`mx65MDbqD$qlnGhyM5 zbxUpq-Pn2ds_Ypf6J4LU?0<=c2TlvNSAKF`f| z9jEnLc@qD;ZM%DqgKN9_z2BdL^Hd%rXMa-PT{eAE40rv!+BDtl7H<8*0;@yqwVF1% z;Xi9QBeY&?s9c!bDC;SDPGZ`U>)jV(kH4BLQOxAkS94zF@4AE&b-HrhhBN;t_xAD} p`t!6XGXA_m%o@3SbsqlPwnu((D!f+T# + + 43012C0 + The 43012C0 devices + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/studio/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/studio/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/hobto/ipblocks.cydata deleted file mode 100644 index 4a1e4211a638503885cc1ef9af53dc082a42f000..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 531 zcmWFt_IGv;a&-*x4{~t~adh+aagF&@Q6w?-Q!K;(-bs$xOojrj?|+IWzBBETb2;O+ zeaj|=8_f&0tEMGO@0#7>yXE8k**mmXuU$Itkk7vF_YBUIJXm(eS4EF6vEH`O7l<{Kk`TbA*nD%W`tKSs;UE}1|58rQ=hi&%S@j+O6yKc?A>4$1I z`pg$^Sh}gtNnXlmgY3#f(uds+7oJFb8dsvps1m-eyr@opfp1)Te&lrTe-n?@ZaGx) ob;p`WKkb^xeR*{r`OCI@esS7(eU4Mp1 - - 43438 - The 43438 devices - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/base/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/base/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/info.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/info.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/info.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/presentation rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml index c50aafc2e4..419a6baa1f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml @@ -2,7 +2,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/base/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/base/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/info.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/info.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/info.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/studio/presentation rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml index 42d65f915c..5b39ddbf31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKUBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml @@ -2,7 +2,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/base/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/base/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/info.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/info.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/info.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/studio/presentation rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml index d144487462..28634da81e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/CYW4343WKWBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml @@ -2,7 +2,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/hobto/ipblocks.cydata new file mode 100644 index 0000000000000000000000000000000000000000..2e7a7aae9fe1c697f0b734b8d96c7036553d8424 GIT binary patch literal 531 zcmWFt_IGv;a&-*x4{~t~adh+aagF&@QIuL-%)r9XJIOJd$xxv6{ZG-vccxu(OJ;~} z-?B;JhV#O`x`xuXFWgnhd1UtQx7xdDS698zJagvzJ?XYH&-Q5*DraeLU1T7|!^nNK zRPm~M>)hLRK8f=dM5bK|`kdd*Jny^3k*G+n_;WMeoqpWAa_AQ0b9T5N4WDE8e*baLQ+<$}T{QLXj%v?!t^3dH+cYcmP^)LooNXTx zwTfNC;GHVls< + + 4343A1 + The 4343A1 devices + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/studio/view.xml similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/studio/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/ipblocks.cydata deleted file mode 100644 index dc13b6a85dbea0b5c436f663963678f1ff91af9c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 531 zcmWFt_IGv;a&-*x4{~t~adh+aagF&@Q6w?-Q!K;(-bs$xOojrj?|+IWzBBET>zXk& zFY|QM0(QrI?=#2DO3XQDulRU>_73gUYnRSD&`Ec0Jii)`Xc$d;Wv4wgwk}u_) zdsJiJz>-)~c=%lgOY6l8)$`?_gfZ>grdGd6`n$%-tslPMWL+Jp8uO#G_qLebdGCkG zX8!SM4NEumImt^IZIE4gNcynb;m{L_PyI?X8CAm9l^50NFYt{^eIGg9``^T4wObCA p{M@l7(oef)?*6s)9{J0*dwy}+czupj(*@4`hav>+m>5Pj000Q=hqnL# diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/view.xml deleted file mode 100644 index db77a062a0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/view.xml +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/info.xml deleted file mode 100644 index 30e55dcf8f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/info.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - 4343W - The 4343W devices - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/studio/view.xml deleted file mode 100644 index cdc66e3e2d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/studio/view.xml +++ /dev/null @@ -1 +0,0 @@ - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_bt_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_bt_v1.cydata index bb290d891c73ddfe4caefcb80a9ee27d068036b4..05e979dc3b00b868b6cbe553e221bf44b4fe90ca 100644 GIT binary patch delta 197 zcmV;$06PDZ0+Rxe7k_1Qa{vSYjgK)8f-n$;cYZ~4yHuisF%%-38;R}&OO-}w8}7jN z-wSGD;^g?gyvuzr&3)goNe!s25s<`dV9H3_Xmb-V(si|iJd4u9AlqZfC^#kHLcki0 zuB$_3>V780`Ab|)t$)o%iubNxR$o% z9;-2HC#^9`k{&dLVu&G)7)!Fo%I8;7Fk9ARlWSc!}>_y^1Davs) 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zcmV;c095~z0+Rxe7k?U+@?8M`m5)6O!Y~kq_x_4-yGGGLq^am2xCsu9rKG7nY?IJC zYx3`{R#4m=--r8n-gFb%M)am5bXLK9Is;*>b|u=2f*V(p6>PF3-FCV@90f;j6x^{w z5G9gtikRD?9oQKs`!DDVt`(djv1vh2LGQ8UB7~5S2cGov8IhJ09yw(6+F5HfV~-s3 Zehyh8M7nF7zP?SpyPNJ0Re2nd$V)<6P{;rP diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index 1940a0f73d..9b8bed892c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -51,7 +51,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/amuxbus.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/amuxbus.cydata index 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z22s0S@{|~u&Drku5Rw!8Z{vIF+)-Z*+eKx{8?dQLa0ia$L>-;0pn#)I|kBkC*IVZC-U; zT~Xz6<~cq!smHk7ino~V;s0y*hLcK$Ol(teZTL&dIAQj9v+vB6LqLZ zcRca62xL-t)6UPs9v1V z6EhL2^;!6F+VfQ{QgH~SCHGzGPq$q0woUBo4ev1I6wEnQ_UR_6%-J-{4T?Kh;Z8?2 zzaKp7TE$i3n{Ow6O65H}NL1a}8gWkyHHf>|L7rB{e`Aa4kBLH`ZX%}Om*bLOE8K`k zZ?$v7wG}%=q^Rb(VWLGLBJ%9jx#gtA79z4v@7xk8?`N{)x0p&Tk*L#S3t%nmuAagu?`lvjTrNDt-#awJn`MnYH+dsYwa{(f`$n)pV6wjb;x`9_QN}- z57pz|jTbI`6^2dMkLU59#vb3f zDp7j()ZMCt;m~Ufs@>d6QQm48|&GwO5=FCCdGH;a=gZc z+|9kWK5I8b!mw@j{D=mHHir177K{BBvdNF5eiRw3dKR@csXg?4c;Y#wIFCpBH1-tr zV};>qEE4s@*`KM~-~u9g2MN>nnLM*{x_Vf8_+r+ZA%0(j@v6gHW_tPj(ukmr3o@Qa-k2yZz6RHYgvP&Q3m1-? z#rCwjevU9cjkmZ|rRl^uH%vWIGGmk43G_rde2L0$CS|{BW5Qi)dH?owfoP`pXWfOI zgWBBa`qd5aH0xMd#_42j7O|*mu_Ea$jOUX~)++GF#j|w4!0Fs;W>wc^4r5g3VppNI zdc~~5IQT+2@$q1_bfS1>Nql*`{LoFSO=gw0Ok&wYZFxFUD{}=4pCHM?hSt94jWbYv zJ*G4UVxkI9=Z1HrL_e3Q@v5YE=5d&+C6<1DjTEcxJS!R#@_fjqX1{y6E~uJ%v$HIz z{>m#ndPRD7Qf1Z;*3r2xz1t3c!8 - + @@ -294,7 +294,7 @@ 1 - Precision ILO: An additional source that can provide a much more accurate 32.768kHz clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. This clock is stopped in the hibernate power mode. + Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. @@ -1965,18 +1965,18 @@ SYS_TICK - - - - + + - - - - + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cyvis b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cyvis index f8f1ca2f9b..e82e6b2241 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cyvis +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cyvis @@ -1,5 +1,5 @@  - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/product_links.list b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/product_links.list new file mode 100644 index 0000000000..85380788b6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/product_links.list @@ -0,0 +1 @@ +[PSoC 6 Product Selector](https://www.cypress.com/search/psg/114026#/?_facetShow=ss_pmain_core,ss_psecondary_core,fs_pmax_operating_frequency_mhz_,fs_pflash_kb_,fs_psram_kb_,fs_pno_of_gpios,fs_pble_maximum_data_rate_mbps_,fs_pble_power_output_dbm_,fs_pble_rx_sensitivity_dbm_,fs_pble_supported_frequency_band_ghz_,ss_pdedicated_adc___max_resolution_sample_rate_,ss_pcapsense,ss_pfs_usb,ss_pdedicated_dac___max_resolution_sample_rate_,fs_pno_of_dedicated_opamps,fs_pno_of_dedicated_comparators,fs_pno_of_dedicated_timer_counter_pwm_blocks,fs_pno_of_serial_communication_blocks_i2c_uart_spi_,fs_psmart_i_o,fs_pno) \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml index 667ceb310d..470bd60bf3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml @@ -6,7 +6,7 @@ 1 CortexM0p,CortexM4 Cypress - 524288 + 458752 262144 68-QFN 68 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml index 3a4e2ece26..a98b8cbe96 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml @@ -8,7 +8,7 @@ - + @@ -52,7 +52,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/amuxbus.cydata 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additional source that can provide a much more accurate 32.768kHz clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. This clock is stopped in the hibernate power mode. + Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. @@ -1200,8 +1200,8 @@ SYS_TICK - + @@ -1807,16 +1807,16 @@ SYS_TICK - - - + + + + + - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis index f82f0025e1..f89b6bcede 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis @@ -1,5 +1,5 @@  - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/product_links.list b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/product_links.list new file mode 100644 index 0000000000..85380788b6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/product_links.list @@ -0,0 +1 @@ +[PSoC 6 Product Selector](https://www.cypress.com/search/psg/114026#/?_facetShow=ss_pmain_core,ss_psecondary_core,fs_pmax_operating_frequency_mhz_,fs_pflash_kb_,fs_psram_kb_,fs_pno_of_gpios,fs_pble_maximum_data_rate_mbps_,fs_pble_power_output_dbm_,fs_pble_rx_sensitivity_dbm_,fs_pble_supported_frequency_band_ghz_,ss_pdedicated_adc___max_resolution_sample_rate_,ss_pcapsense,ss_pfs_usb,ss_pdedicated_dac___max_resolution_sample_rate_,fs_pno_of_dedicated_opamps,fs_pno_of_dedicated_comparators,fs_pno_of_dedicated_timer_counter_pwm_blocks,fs_pno_of_serial_communication_blocks_i2c_uart_spi_,fs_psmart_i_o,fs_pno) \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation index d3b5d7b9fa..6a8bdde3e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation @@ -1,2 +1,2 @@ PSoC 6 -PSoC 63 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml index 21d084ff40..7311e0738b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml @@ -5,7 +5,7 @@ - + @@ -48,7 +48,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation index d3b5d7b9fa..6a8bdde3e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation @@ -1,2 +1,2 @@ PSoC 6 -PSoC 63 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml index 4b289cf509..240cfaccc4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml @@ -5,7 +5,7 @@ - + @@ -48,7 +48,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation index 2d84ef27e9..6a8bdde3e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation @@ -1,2 +1,2 @@ PSoC 6 -PSoC 62 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml index f0451972da..97073c5517 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml @@ -5,7 +5,7 @@ - + @@ -48,7 +48,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/amuxbus.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/amuxbus.cydata index d7b8d5103112a611cdddaaa9f1cf14d5a6791309..300f62f4b6258967b7b45e4bfbcc049ef64f13be 100644 GIT binary patch delta 1436 zcmV;N1!MZT7QGgb7k_1Qa{vSY?VDR~;#L%e-z)V$Sbpf+3_iXcyM-A6ohp%t8V#AY zQdL|;16i++qDx17>)Q=y2{Gr{Qubz6VRLOC##MSk2oOaavEPq@4+-i-!EtX-Lz8@v? z)>AspkH>!I`}u2wRq8!5H7}(o?O`~bhjEr}j>=;t_UB(Q= zL~;K7)$scF8*lh&;B{}l{MA)=Rq{Hw{#c1u^B`PyR9D@VyVcew)jCcw4KOCg7+|^> z(*ZNYm;sn6#(zw}EHP#w=3V_kv{zPSj8a9n5F~WbZ3HQ0ID&*Wx`QC0j_x8z=ws*z z+5~7I$O#a7)F~Ye7ePWtQ$vu@(PRh`I+{9y)RY+r5;~eDf`pEyg&?7$3DaXxI+`3o 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b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cysem index 42cec63d46..955b34d57e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cysem @@ -1,5 +1,5 @@  - + @@ -4716,7 +4716,7 @@ false - VBGR + AREF 0 @@ -4725,7 +4725,7 @@ AREF_VBGR - VBGR + VREF @@ -8445,7 +8445,7 @@ - + @@ -8616,6 +8616,9 @@ + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cyvis b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cyvis index dd7ebea2a3..f458f89825 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cyvis +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analog.cyvis @@ -1,5 +1,5 @@  - + @@ -663,6 +663,12 @@ w:PASS0_SARADC0_SAR + + + pass0_sar_vminus0 + + + @@ -839,7 +845,7 @@ - VBGR + VREF `=$RefName` diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analogResourceMap.txt b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analogResourceMap.txt index 5a7c2f8b7e..260b5c5461 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analogResourceMap.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/analogResourceMap.txt @@ -10,4 +10,4 @@ CTDAC 0 pass[0].ctdac[0] TEMP 0 pass[0].sarmux[0].tempsensor[0] SARADC 0 pass[0].sar[0] VSSA 0 pass[0].vssa[0] -VBGR 0 pass[0].aref[0] +AREF 0 pass[0].aref[0] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/modules/module_43-SMT.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/modules/module_43-SMT.cydata index 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b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/product_links.list @@ -0,0 +1 @@ +[PSoC 6 Product Selector](https://www.cypress.com/search/psg/114026#/?_facetShow=ss_pmain_core,ss_psecondary_core,fs_pmax_operating_frequency_mhz_,fs_pflash_kb_,fs_psram_kb_,fs_pno_of_gpios,fs_pble_maximum_data_rate_mbps_,fs_pble_power_output_dbm_,fs_pble_rx_sensitivity_dbm_,fs_pble_supported_frequency_band_ghz_,ss_pdedicated_adc___max_resolution_sample_rate_,ss_pcapsense,ss_pfs_usb,ss_pdedicated_dac___max_resolution_sample_rate_,fs_pno_of_dedicated_opamps,fs_pno_of_dedicated_comparators,fs_pno_of_dedicated_timer_counter_pwm_blocks,fs_pno_of_serial_communication_blocks_i2c_uart_spi_,fs_psmart_i_o,fs_pno) \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/hobto/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/hobto/view.xml deleted file mode 100644 index cdc66e3e2d..0000000000 --- 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z8g#4XfCIra{vSYksTTvRA_syT^cp4O+pf#W$e2znPrNCOxR9I9`F5; zQY3#Vm|9X>E?yB7Ov^H_GoDwrlyc^fyo87?n6c}y6yyyq(`b0LYnHiLhNx*lpmW{K zSDSCt6?S0|*l>quu0ymmMm~5RsimS?w~45{jV|n&Ng_C>#IQ9pb+-0VuLTfHg)*?c zh`3l9H7|+qGfoC07f`t=cMTp-(*(ggD_llazk|R#L>M*#gkJL>5KA7e1?%^7&`8XNbO%&r8M^Et&zi*3`IgKBO^*d+j=HGN_x05>o*cCW( AYybcN delta 250 zcmV?8(r8vlSFV%iD7GI>TKoH#5l!(FM^Doqe%}@=a~eMm>vzu5&A;i=mXkXH*d@er AU;qFB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxusbfs_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxusbfs_v1.cydata index a2f0f02b6dc5b0ab3180510a66708367ce7e5a1b..cb451c3f3cec9b460152e1b252acc98bafd20c6c 100644 GIT binary patch delta 398 zcmV;90dfA51d{}i7k_1Qa{vSYt(4Jf!Y~wu?|q68cCj(E^G-%p>I4x)1@$_lNnC?X z(&eOGefy=WLnbQD?keP*9wCl2_Kfc5oS`1phZy zY8s+gx+A`vgnx_T^uAbX*se-QCa$SW=eLR^2Hbg-I@3(!;FiP|t{tV$H<99s5-UFb zQ2E{kN}OA8LSOBN-+s=LKz^4O%(h`Se0M_TA0R)i;Q0BvN3ysDt|$eR=ba2cs1u|hDyY{XP2w7C zk}fCh>c3xV9fGJhyQ`9O+UI$5nzlbGRf-B>K^i^4-Od|ELNmjq{v6=kZQDIO8n*hO zWl6L|Zl4KXh8QC*Axr6=XsUc^qh$r5DOw3D{big3dfu$YFMsGs^73?hMqM(%A4aKM zOGcg7VgwY9994Sw7V6R|7Dhhi`C7vOC(dQ>LBRHz6#yM(R8Ru9w?l2_5aJGhQgg8v&U zH4RZL-4Q=d!hc0^{=Qgh*sf|wCT>}x`Mr|FfV*s|JIx%&v?R80Yb$lXiHa*qtoZuF zRbIw95K5Bb s7ZuLK*<$)ADSm*|59%M_u=N9tW=!ZY1poj5000000F#*kdXu051!7RTrvLx| diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk index 1763c9f4ae..dc60a1a3ed 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk @@ -14,11 +14,18 @@ CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 C CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY_DEVICES_WITH_FLASH_KB_832=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY_DEVICES_WITH_FLASH_KB_1856=CYB0644ABZI-S2D44 +CY_DEVICES_WITH_FLASH_KB_448=CYB06445LQI-S3D42 + +CY_DEVICES_WITH_SRAM_KB_128=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 +CY_DEVICES_WITH_SRAM_KB_288=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 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CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 CY_DEVICES_WITH_MAX_SPEED_MHZ_50=CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6117BZI-F34 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6117FDI-F02 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6117WI-F34 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat index dee60c3d86..c7973f6737 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat @@ -1 +1 @@ -1.1.2.62 +1.1.3.51 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml index 5298029c68..b1f03ef760 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml @@ -1 +1 @@ -1.1.2.62 +1.1.3.51 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml index 7fa78eaf8e..909bd30c58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -1 +1 @@ -1.3.1.1499 +1.4.0.1889