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Update PSoC 6 BSPs to verion 1.2

pull/12943/head
Kyle Kearney 2020-04-29 17:12:29 -07:00
parent 6afa8fd35d
commit f38e21fa6c
290 changed files with 3683 additions and 14013 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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@ -4,8 +4,8 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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@ -4,8 +4,8 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file → Executable file
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@ -4,8 +4,8 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
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@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -27,7 +27,7 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
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@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
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@ -5,8 +5,8 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
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@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -26,7 +26,7 @@
#include "cycfg_peripherals.h"
cy_stc_csd_context_t cy_csd_0_context =
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

68
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -26,7 +26,7 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_RX_PORT_NUM,
.channel_num = CYBSP_CSD_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,

36
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -57,7 +57,7 @@ extern "C" {
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -81,7 +81,7 @@ extern "C" {
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -105,7 +105,7 @@ extern "C" {
#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -129,7 +129,7 @@ extern "C" {
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
@ -153,7 +153,7 @@ extern "C" {
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
@ -177,7 +177,7 @@ extern "C" {
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
@ -201,7 +201,7 @@ extern "C" {
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -225,7 +225,7 @@ extern "C" {
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -249,7 +249,7 @@ extern "C" {
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -273,7 +273,7 @@ extern "C" {
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -297,7 +297,7 @@ extern "C" {
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -321,7 +321,7 @@ extern "C" {
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -345,7 +345,7 @@ extern "C" {
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -369,7 +369,7 @@ extern "C" {
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -393,7 +393,7 @@ extern "C" {
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -417,7 +417,7 @@ extern "C" {
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -4,7 +4,8 @@
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -4,7 +4,8 @@
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -4,8 +4,8 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

20
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,8 +4,8 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -40,16 +40,16 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus)
}

79
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -5,7 +5,7 @@
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -69,7 +69,7 @@
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 20U,
@ -83,7 +83,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
@ -91,7 +91,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
@ -99,14 +99,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 36,
.referenceDiv = 1,
@ -114,7 +114,7 @@ static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
@ -247,14 +247,14 @@ __STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
@ -285,7 +285,7 @@ void init_cycfg_system(void)
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
@ -296,59 +296,59 @@ void init_cycfg_system(void)
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
{
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
@ -358,7 +358,7 @@ void init_cycfg_system(void)
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
@ -405,21 +405,21 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
@ -466,7 +466,7 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
@ -513,48 +513,49 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
Cy_SysClk_IloHibernateOn(false);
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -5,7 +5,7 @@
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,4 +1,3 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0 build 531-->
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0.1483-->
<Configuration app="Capsense" major="2" minor="0">
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
@ -114,12 +114,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
@ -216,12 +216,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
@ -318,12 +318,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -468,7 +468,7 @@
</Mux>
</Netlist>
</Device>
<Device mpn="CYW43012WKWBG">
<Device mpn="CYW43012C0WKWBG">
<BlockConfig/>
<Netlist/>
</Device>

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c
View File

@ -2,12 +2,12 @@
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -29,6 +29,7 @@
#include "cybsp.h"
#if defined(CY_USING_HAL)
#include "cyhal_hwmgr.h"
#include "cyhal_syspm.h"
#endif
#if defined(__cplusplus)
@ -36,7 +37,7 @@ extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void)
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_syspm_init();
}
#else
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void)
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,9 +26,6 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#include "cyhal_sdio.h"
#endif
@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/

201
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -28,6 +28,9 @@
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(__cplusplus)
extern "C" {
@ -66,14 +69,22 @@ extern "C" {
*/
/** Pin state for the LED on. */
#ifndef CYBSP_LED_STATE_ON
#define CYBSP_LED_STATE_ON (0U)
#endif
/** Pin state for the LED off. */
#ifndef CYBSP_LED_STATE_OFF
#define CYBSP_LED_STATE_OFF (1U)
#endif
/** Pin state for when a button is pressed. */
#ifndef CYBSP_BTN_PRESSED
#define CYBSP_BTN_PRESSED (0U)
#endif
/** Pin state for when a button is released. */
#ifndef CYBSP_BTN_OFF
#define CYBSP_BTN_OFF (1U)
#endif
/** \} group_bsp_pin_state */
@ -90,28 +101,50 @@ extern "C" {
*/
/** LED 8; User LED1 (orange) */
#ifndef CYBSP_LED8
#define CYBSP_LED8 (P1_5)
#endif
/** LED 9; User LED2 (red) */
#ifndef CYBSP_LED9
#define CYBSP_LED9 (P11_1)
#endif
/** LED 5: RGB LED - Red; User LED3 */
#ifndef CYBSP_LED_RGB_RED
#define CYBSP_LED_RGB_RED (P1_1)
#endif
/** LED 5: RGB LED - Green; User LED4 */
#ifndef CYBSP_LED_RGB_GREEN
#define CYBSP_LED_RGB_GREEN (P0_5)
#endif
/** LED 5: RGB LED - Blue; User LED5 */
#ifndef CYBSP_LED_RGB_BLUE
#define CYBSP_LED_RGB_BLUE (P7_3)
#endif
/** LED 8; User LED1 (orange) */
#ifndef CYBSP_USER_LED1
#define CYBSP_USER_LED1 (CYBSP_LED8)
#endif
/** LED 9; User LED2 (red) */
#ifndef CYBSP_USER_LED2
#define CYBSP_USER_LED2 (CYBSP_LED9)
#endif
/** LED 5: RGB LED - Red; User LED3 */
#ifndef CYBSP_USER_LED3
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
#endif
/** LED 5: RGB LED - Green; User LED4 */
#ifndef CYBSP_USER_LED4
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
#endif
/** LED 5: RGB LED - Blue; User LED5 */
#ifndef CYBSP_USER_LED5
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
#endif
/** LED 8; User LED1 (orange) */
#ifndef CYBSP_USER_LED
#define CYBSP_USER_LED (CYBSP_USER_LED1)
#endif
/** \} group_bsp_pins_led */
@ -122,16 +155,26 @@ extern "C" {
*/
/** Switch 2; User Button 1 */
#ifndef CYBSP_SW2
#define CYBSP_SW2 (P0_4)
#endif
/** Switch 4; User Button 2 */
#ifndef CYBSP_SW4
#define CYBSP_SW4 (P1_4)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN1
#define CYBSP_USER_BTN1 (CYBSP_SW2)
#endif
/** Switch 4; User Button 2 */
#ifndef CYBSP_USER_BTN2
#define CYBSP_USER_BTN2 (CYBSP_SW4)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
#endif
/** \} group_bsp_pins_btn */
@ -142,71 +185,131 @@ extern "C" {
*/
/** Pin: WIFI SDIO D0 */
#ifndef CYBSP_WIFI_SDIO_D0
#define CYBSP_WIFI_SDIO_D0 (P2_0)
#endif
/** Pin: WIFI SDIO D1 */
#ifndef CYBSP_WIFI_SDIO_D1
#define CYBSP_WIFI_SDIO_D1 (P2_1)
#endif
/** Pin: WIFI SDIO D2 */
#ifndef CYBSP_WIFI_SDIO_D2
#define CYBSP_WIFI_SDIO_D2 (P2_2)
#endif
/** Pin: WIFI SDIO D3 */
#ifndef CYBSP_WIFI_SDIO_D3
#define CYBSP_WIFI_SDIO_D3 (P2_3)
#endif
/** Pin: WIFI SDIO CMD */
#ifndef CYBSP_WIFI_SDIO_CMD
#define CYBSP_WIFI_SDIO_CMD (P2_4)
#endif
/** Pin: WIFI SDIO CLK */
#ifndef CYBSP_WIFI_SDIO_CLK
#define CYBSP_WIFI_SDIO_CLK (P2_5)
#endif
/** Pin: WIFI ON */
#ifndef CYBSP_WIFI_WL_REG_ON
#define CYBSP_WIFI_WL_REG_ON (P2_6)
#endif
/** Pin: WIFI Host Wakeup */
#ifndef CYBSP_WIFI_HOST_WAKE
#define CYBSP_WIFI_HOST_WAKE (P4_1)
#endif
/** Pin: BT UART RX */
#ifndef CYBSP_BT_UART_RX
#define CYBSP_BT_UART_RX (P3_0)
#endif
/** Pin: BT UART TX */
#ifndef CYBSP_BT_UART_TX
#define CYBSP_BT_UART_TX (P3_1)
#endif
/** Pin: BT UART RTS */
#ifndef CYBSP_BT_UART_RTS
#define CYBSP_BT_UART_RTS (P3_2)
#endif
/** Pin: BT UART CTS */
#ifndef CYBSP_BT_UART_CTS
#define CYBSP_BT_UART_CTS (P3_3)
#endif
/** Pin: BT Power */
#ifndef CYBSP_BT_POWER
#define CYBSP_BT_POWER (P3_4)
#endif
/** Pin: BT Host Wakeup */
#ifndef CYBSP_BT_HOST_WAKE
#define CYBSP_BT_HOST_WAKE (P4_0)
#endif
/** Pin: BT Device Wakeup */
#ifndef CYBSP_BT_DEVICE_WAKE
#define CYBSP_BT_DEVICE_WAKE (P3_5)
#endif
/** Pin: UART RX */
#ifndef CYBSP_DEBUG_UART_RX
#define CYBSP_DEBUG_UART_RX (P5_0)
#endif
/** Pin: UART TX */
#ifndef CYBSP_DEBUG_UART_TX
#define CYBSP_DEBUG_UART_TX (P5_1)
#endif
/** Pin: UART RX */
#ifndef CYBSP_DEBUG_UART_RTS
#define CYBSP_DEBUG_UART_RTS (P5_2)
#endif
/** Pin: UART TX */
#ifndef CYBSP_DEBUG_UART_CTS
#define CYBSP_DEBUG_UART_CTS (P5_3)
#endif
/** Pin: I2C SCL */
#ifndef CYBSP_I2C_SCL
#define CYBSP_I2C_SCL (P6_0)
#endif
/** Pin: I2C SDA */
#ifndef CYBSP_I2C_SDA
#define CYBSP_I2C_SDA (P6_1)
#endif
/** Pin: SWO */
#ifndef CYBSP_SWO
#define CYBSP_SWO (P6_4)
#endif
/** Pin: SWDIO */
#ifndef CYBSP_SWDIO
#define CYBSP_SWDIO (P6_6)
#endif
/** Pin: SWDCK */
#ifndef CYBSP_SWDCK
#define CYBSP_SWDCK (P6_7)
#endif
/** Pin: QUAD SPI SS */
#ifndef CYBSP_QSPI_SS
#define CYBSP_QSPI_SS (P11_2)
#endif
/** Pin: QUAD SPI D3 */
#ifndef CYBSP_QSPI_D3
#define CYBSP_QSPI_D3 (P11_3)
#endif
/** Pin: QUAD SPI D2 */
#ifndef CYBSP_QSPI_D2
#define CYBSP_QSPI_D2 (P11_4)
#endif
/** Pin: QUAD SPI D1 */
#ifndef CYBSP_QSPI_D1
#define CYBSP_QSPI_D1 (P11_5)
#endif
/** Pin: QUAD SPI D0 */
#ifndef CYBSP_QSPI_D0
#define CYBSP_QSPI_D0 (P11_6)
#endif
/** Pin: QUAD SPI SCK */
#ifndef CYBSP_QSPI_SCK
#define CYBSP_QSPI_SCK (P11_7)
#endif
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
@ -214,13 +317,21 @@ extern "C" {
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** Pin: SPI MOSI */
#ifndef CYBSP_SPI_MOSI
#define CYBSP_SPI_MOSI (P12_0)
#endif
/** Pin: SPI MISO */
#ifndef CYBSP_SPI_MISO
#define CYBSP_SPI_MISO (P12_1)
#endif
/** Pin: SPI CLK */
#ifndef CYBSP_SPI_CLK
#define CYBSP_SPI_CLK (P12_2)
#endif
/** Pin: SPI CS */
#ifndef CYBSP_SPI_CS
#define CYBSP_SPI_CS (P12_4)
#endif
/** \} group_bsp_pins_comm */
@ -231,49 +342,93 @@ extern "C" {
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
#ifndef CYBSP_A0
#define CYBSP_A0 (P10_0)
#endif
/** Arduino A1 */
#define CYBSP_A1 P10_1
#ifndef CYBSP_A1
#define CYBSP_A1 (P10_1)
#endif
/** Arduino A2 */
#define CYBSP_A2 P10_2
#ifndef CYBSP_A2
#define CYBSP_A2 (P10_2)
#endif
/** Arduino A3 */
#define CYBSP_A3 P10_3
#ifndef CYBSP_A3
#define CYBSP_A3 (P10_3)
#endif
/** Arduino A4 */
#define CYBSP_A4 P10_4
#ifndef CYBSP_A4
#define CYBSP_A4 (P10_4)
#endif
/** Arduino A5 */
#define CYBSP_A5 P10_5
#ifndef CYBSP_A5
#define CYBSP_A5 (P10_5)
#endif
/** Arduino D0 */
#ifndef CYBSP_D0
#define CYBSP_D0 (P5_0)
#endif
/** Arduino D1 */
#ifndef CYBSP_D1
#define CYBSP_D1 (P5_1)
#endif
/** Arduino D2 */
#ifndef CYBSP_D2
#define CYBSP_D2 (P5_2)
#endif
/** Arduino D3 */
#ifndef CYBSP_D3
#define CYBSP_D3 (P5_3)
#endif
/** Arduino D4 */
#ifndef CYBSP_D4
#define CYBSP_D4 (P5_4)
#endif
/** Arduino D5 */
#ifndef CYBSP_D5
#define CYBSP_D5 (P5_5)
#endif
/** Arduino D6 */
#ifndef CYBSP_D6
#define CYBSP_D6 (P5_6)
#endif
/** Arduino D7 */
#ifndef CYBSP_D7
#define CYBSP_D7 (P5_7)
#endif
/** Arduino D8 */
#ifndef CYBSP_D8
#define CYBSP_D8 (P7_5)
#endif
/** Arduino D9 */
#ifndef CYBSP_D9
#define CYBSP_D9 (P7_6)
#endif
/** Arduino D10 */
#ifndef CYBSP_D10
#define CYBSP_D10 (P12_3)
#endif
/** Arduino D11 */
#ifndef CYBSP_D11
#define CYBSP_D11 (P12_0)
#endif
/** Arduino D12 */
#ifndef CYBSP_D12
#define CYBSP_D12 (P12_1)
#endif
/** Arduino D13 */
#ifndef CYBSP_D13
#define CYBSP_D13 (P12_2)
#endif
/** Arduino D14 */
#ifndef CYBSP_D14
#define CYBSP_D14 (P6_1)
#endif
/** Arduino D15 */
#ifndef CYBSP_D15
#define CYBSP_D15 (P6_0)
#endif
/** \} group_bsp_pins_arduino */
@ -284,37 +439,69 @@ extern "C" {
*/
/** Cypress J2 Header pin 1 */
#ifndef CYBSP_J2_1
#define CYBSP_J2_1 (CYBSP_A0)
#endif
/** Cypress J2 Header pin 2 */
#ifndef CYBSP_J2_2
#define CYBSP_J2_2 (P9_0)
#endif
/** Cypress J2 Header pin 3 */
#ifndef CYBSP_J2_3
#define CYBSP_J2_3 (CYBSP_A1)
#endif
/** Cypress J2 Header pin 4 */
#ifndef CYBSP_J2_4
#define CYBSP_J2_4 (P9_1)
#endif
/** Cypress J2 Header pin 5 */
#ifndef CYBSP_J2_5
#define CYBSP_J2_5 (CYBSP_A2)
#endif
/** Cypress J2 Header pin 6 */
#ifndef CYBSP_J2_6
#define CYBSP_J2_6 (P9_2)
#endif
/** Cypress J2 Header pin 7 */
#ifndef CYBSP_J2_7
#define CYBSP_J2_7 (CYBSP_A3)
#endif
/** Cypress J2 Header pin 8 */
#ifndef CYBSP_J2_8
#define CYBSP_J2_8 (P9_3)
#endif
/** Cypress J2 Header pin 9 */
#ifndef CYBSP_J2_9
#define CYBSP_J2_9 (CYBSP_A4)
#endif
/** Cypress J2 Header pin 10 */
#ifndef CYBSP_J2_10
#define CYBSP_J2_10 (P9_4)
#endif
/** Cypress J2 Header pin 11 */
#ifndef CYBSP_J2_11
#define CYBSP_J2_11 (CYBSP_A5)
#endif
/** Cypress J2 Header pin 12 */
#ifndef CYBSP_J2_12
#define CYBSP_J2_12 (P9_5)
#endif
/** Cypress J2 Header pin 13 */
#ifndef CYBSP_J2_13
#define CYBSP_J2_13 (P10_6)
#endif
/** Cypress J2 Header pin 14 */
#ifndef CYBSP_J2_14
#define CYBSP_J2_14 (P9_6)
#endif
/** Cypress J2 Header pin 15 */
#ifndef CYBSP_J2_15
#define CYBSP_J2_15 (P10_7)
#endif
/** Cypress J2 Header pin 16 */
#ifndef CYBSP_J2_16
#define CYBSP_J2_16 (P9_7)
#endif
/** \} group_bsp_pins_j2 */

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm0plus.sct
;* \version 2.70
;* \version 2.70.1
;*
;* Linker file for the ARMCC.
;*
@ -26,7 +26,7 @@
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm0plus.ld
* \version 2.70
* \version 2.70.1
*
* Linker file for the GNU C compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
/*******************************************************************************
* \file cy8c6xxa_cm0plus.icf
* \version 2.70
* \version 2.70.1
*
* Linker file for the IAR compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Public RAM */
define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000);
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm0plus.c
* \version 2.70
* \version 2.70.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.70
;* \version 2.70.1
;*
;* Linker file for the ARMCC.
;*
@ -26,7 +26,7 @@
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
@ -42,6 +42,9 @@
;* limitations under the License.
;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.70
* \version 2.70.1
*
* Linker file for the GNU C compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -40,6 +40,10 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
/*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf
* \version 2.70
* \version 2.70.1
*
* Linker file for the IAR compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -41,6 +41,10 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.70
* \version 2.70.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

172
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.70
* \version 2.70.1
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,6 @@
* * \ref group_system_config_single_core_device_initialization
* - \ref group_system_config_device_memory_definition
* - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps
* - \ref group_system_config_default_handlers
* - \ref group_system_config_device_vector_table
* - \ref group_system_config_cm4_functions
@ -56,44 +55,58 @@
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* \note For the PSoC 64 Secure MCUs devices, refer to the following page:
* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide
*
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either:
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
* of the Cortex-M0+ application should be the same value as the flash LENGTH in
* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
* Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* <b>ARM MDK</b>\n
* <b>ARM Compiler</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
@ -106,29 +119,32 @@
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group:
* - 'xx_cm0plus.sct', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define FLASH_SIZE 0x00002000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* #define RAM_SIZE 0x00002000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
* - 'xx_cm4_dual.sct', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00100000
* #define RAM_START 0x08002000
* #define RAM_SIZE 0x00045800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either:
* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
* Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
@ -138,32 +154,39 @@
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either:
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
* 'xx_cm0plus.icf'. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code
@ -189,7 +212,9 @@
* -# Editing source code files
* -# Specifying via command line
*
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
* By default, the stack size is set to 0x00001000 and the heap size is allocated
* dynamically to the whole available free memory up to stack memory and it
* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
*
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
* - <b>Editing source code files</b>\n
@ -198,28 +223,23 @@
* Change the heap and stack sizes by modifying the following lines:\n
* \code .equ Stack_Size, 0x00001000 \endcode
* \code .equ Heap_Size, 0x00000400 \endcode
* Also, the stack size is defined in the linker script files: 'xx_yy.ld',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n
* \code -D __STACK_SIZE=0x000000400 \endcode
* \code -D __HEAP_SIZE=0x000000100 \endcode
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
* The stack size is defined in the linker script files: 'xx_yy.sct',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n
@ -232,21 +252,6 @@
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
*
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default
* values.
*
* The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific.
*
* The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data.
*
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
@ -273,10 +278,10 @@
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* The code in these files copies the vector table from Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler
* The linker script file is 'xx_yy.sct', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and
* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
@ -291,10 +296,6 @@
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_more_information More Information
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
* more details.
*
* \section group_system_config_MISRA MISRA Compliance
*
* <table class="doxtable">
@ -320,6 +321,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.70.1</td>
* <td>Updated documentation for the better description of the existing startup implementation.</td>
* <td>User experience enhancement.</td>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -4,8 +4,8 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -4,8 +4,8 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file → Executable file
View File

@ -4,8 +4,8 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -27,7 +27,7 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -5,8 +5,8 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -27,14 +27,14 @@
#include "cycfg_peripherals.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BLE_obj =
const cyhal_resource_inst_t CYBSP_BLE_obj =
{
.type = CYHAL_RSC_BLESS,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
cy_stc_csd_context_t cy_csd_0_context =
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

68
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -26,7 +26,7 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,

36
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -57,7 +57,7 @@ extern "C" {
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -81,7 +81,7 @@ extern "C" {
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -105,7 +105,7 @@ extern "C" {
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -129,7 +129,7 @@ extern "C" {
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
@ -153,7 +153,7 @@ extern "C" {
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
@ -177,7 +177,7 @@ extern "C" {
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
@ -201,7 +201,7 @@ extern "C" {
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -225,7 +225,7 @@ extern "C" {
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -249,7 +249,7 @@ extern "C" {
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -273,7 +273,7 @@ extern "C" {
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -297,7 +297,7 @@ extern "C" {
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -321,7 +321,7 @@ extern "C" {
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -345,7 +345,7 @@ extern "C" {
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -369,7 +369,7 @@ extern "C" {
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -393,7 +393,7 @@ extern "C" {
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -417,7 +417,7 @@ extern "C" {
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG

47
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -4,7 +4,8 @@
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
@ -24,7 +25,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -42,7 +43,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +61,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,7 +79,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
@ -96,7 +97,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,7 +115,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
@ -132,7 +133,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +151,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +169,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,34 +187,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -226,7 +227,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@ -244,11 +245,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
&S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -4,7 +4,8 @@
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
@ -28,19 +29,19 @@
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -4,8 +4,8 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,8 +4,8 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -40,16 +40,16 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus)
}

83
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -4,8 +4,8 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -72,7 +72,7 @@
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 20U,
@ -86,7 +86,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
@ -94,7 +94,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
@ -102,7 +102,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
@ -110,7 +110,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
@ -118,14 +118,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
@ -255,14 +255,14 @@ __STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
@ -293,7 +293,7 @@ void init_cycfg_system(void)
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
@ -304,59 +304,59 @@ void init_cycfg_system(void)
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
{
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
@ -366,7 +366,7 @@ void init_cycfg_system(void)
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
@ -413,21 +413,21 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
@ -474,7 +474,7 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
@ -521,48 +521,49 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
Cy_SysClk_IloHibernateOn(false);
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,8 +4,8 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,4 +1,3 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

17
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
View File

@ -1,13 +1,6 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 351
-->
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0.1483-->
<Configuration app="Capsense" major="2" minor="0">
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
@ -121,12 +114,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
@ -223,12 +216,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
@ -325,12 +318,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>

13
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -82,12 +82,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[2]"/>
<Block location="ioss[0].port[11].pin[3]"/>
<Block location="ioss[0].port[11].pin[4]"/>
<Block location="ioss[0].port[11].pin[5]"/>
<Block location="ioss[0].port[11].pin[6]"/>
<Block location="ioss[0].port[11].pin[7]"/>
<Block location="ioss[0].port[1].pin[0]">
<Alias value="CYBSP_CSD_TX"/>
<Personality template="mxs40pin" version="1.1">
@ -101,8 +95,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[0]"/>
<Block location="ioss[0].port[6].pin[1]"/>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
@ -280,9 +272,6 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[1]"/>
<Block location="scb[3]"/>
<Block location="smif[0]"/>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
@ -405,7 +394,6 @@
<Param id="accuracyPpm" value="150"/>
</Personality>
</Block>
<Block location="srss[0].mcwdt[0]"/>
<Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.2">
<Param id="pwrMode" value="LDO_1_1"/>
@ -423,7 +411,6 @@
<Param id="vddio1Mv" value="3300"/>
</Personality>
</Block>
<Block location="srss[0].rtc[0]"/>
</BlockConfig>
<Netlist>
<Net>

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c
View File

@ -2,12 +2,12 @@
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -29,6 +29,7 @@
#include "cybsp.h"
#if defined(CY_USING_HAL)
#include "cyhal_hwmgr.h"
#include "cyhal_syspm.h"
#endif
#if defined(__cplusplus)
@ -36,7 +37,7 @@ extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void)
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_syspm_init();
}
#else
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void)
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,9 +26,6 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#include "cyhal_sdio.h"
#endif
@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/

175
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -28,6 +28,9 @@
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(__cplusplus)
extern "C" {
@ -66,14 +69,26 @@ extern "C" {
*/
/** Pin state for the LED on. */
#ifndef CYBSP_LED_STATE_ON
#ifndef CYBSP_LED_STATE_ON
#define CYBSP_LED_STATE_ON (0U)
#endif
#endif
/** Pin state for the LED off. */
#ifndef CYBSP_LED_STATE_OFF
#ifndef CYBSP_LED_STATE_OFF
#define CYBSP_LED_STATE_OFF (1U)
#endif
#endif
/** Pin state for when a button is pressed. */
#ifndef CYBSP_BTN_PRESSED
#define CYBSP_BTN_PRESSED (0U)
#endif
/** Pin state for when a button is released. */
#ifndef CYBSP_BTN_OFF
#define CYBSP_BTN_OFF (1U)
#endif
/** \} group_bsp_pin_state */
@ -90,28 +105,50 @@ extern "C" {
*/
/** LED 8; User LED1 */
#ifndef CYBSP_LED8
#define CYBSP_LED8 (P1_5)
#endif
/** LED 9; User LED2 */
#ifndef CYBSP_LED9
#define CYBSP_LED9 (P13_7)
#endif
/** LED 5: RGB LED - Red; User LED3 */
#ifndef CYBSP_LED_RGB_RED
#define CYBSP_LED_RGB_RED (P0_3)
#endif
/** LED 5: RGB LED - Green; User LED4 */
#ifndef CYBSP_LED_RGB_GREEN
#define CYBSP_LED_RGB_GREEN (P1_1)
#endif
/** LED 5: RGB LED - Blue; User LED5 */
#ifndef CYBSP_LED_RGB_BLUE
#define CYBSP_LED_RGB_BLUE (P11_1)
#endif
/** LED 8; User LED1 */
#ifndef CYBSP_USER_LED1
#define CYBSP_USER_LED1 (CYBSP_LED8)
#endif
/** LED 9; User LED2 */
#ifndef CYBSP_USER_LED2
#define CYBSP_USER_LED2 (CYBSP_LED9)
#endif
/** LED 5: RGB LED - Red; User LED3 */
#ifndef CYBSP_USER_LED3
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
#endif
/** LED 5: RGB LED - Green; User LED4 */
#ifndef CYBSP_USER_LED4
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
#endif
/** LED 5: RGB LED - Blue; User LED5 */
#ifndef CYBSP_USER_LED5
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
#endif
/** LED 8; User LED1 */
#ifndef CYBSP_USER_LED
#define CYBSP_USER_LED (CYBSP_USER_LED1)
#endif
/** \} group_bsp_pins_led */
@ -121,12 +158,18 @@ extern "C" {
*/
/** Switch 2; User Button 1 */
#ifndef CYBSP_SW2
#define CYBSP_SW2 (P0_4)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN1
#define CYBSP_USER_BTN1 (CYBSP_SW2)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
#endif
/** \} group_bsp_pins_btn */
@ -137,43 +180,77 @@ extern "C" {
*/
/** Pin: UART RX */
#ifndef CYBSP_DEBUG_UART_RX
#define CYBSP_DEBUG_UART_RX (P5_0)
#endif
/** Pin: UART TX */
#ifndef CYBSP_DEBUG_UART_TX
#define CYBSP_DEBUG_UART_TX (P5_1)
#endif
/** Pin: I2C SCL */
#ifndef CYBSP_I2C_SCL
#define CYBSP_I2C_SCL (P6_0)
#endif
/** Pin: I2C SDA */
#ifndef CYBSP_I2C_SDA
#define CYBSP_I2C_SDA (P6_1)
#endif
/** Pin: SWO */
#ifndef CYBSP_SWO
#define CYBSP_SWO (P6_4)
#endif
/** Pin: SWDIO */
#ifndef CYBSP_SWDIO
#define CYBSP_SWDIO (P6_6)
#endif
/** Pin: SWDCK */
#ifndef CYBSP_SWDCK
#define CYBSP_SWDCK (P6_7)
#endif
/** Pin: QUAD SPI SS */
#ifndef CYBSP_QSPI_SS
#define CYBSP_QSPI_SS (P11_2)
#endif
/** Pin: QUAD SPI D3 */
#ifndef CYBSP_QSPI_D3
#define CYBSP_QSPI_D3 (P11_3)
#endif
/** Pin: QUAD SPI D2 */
#ifndef CYBSP_QSPI_D2
#define CYBSP_QSPI_D2 (P11_4)
#endif
/** Pin: QUAD SPI D1 */
#ifndef CYBSP_QSPI_D1
#define CYBSP_QSPI_D1 (P11_5)
#endif
/** Pin: QUAD SPI D0 */
#ifndef CYBSP_QSPI_D0
#define CYBSP_QSPI_D0 (P11_6)
#endif
/** Pin: QUAD SPI SCK */
#ifndef CYBSP_QSPI_SCK
#define CYBSP_QSPI_SCK (P11_7)
#endif
/** Pin: SPI MOSI */
#ifndef CYBSP_SPI_MOSI
#define CYBSP_SPI_MOSI (P12_0)
#endif
/** Pin: SPI MISO */
#ifndef CYBSP_SPI_MISO
#define CYBSP_SPI_MISO (P12_1)
#endif
/** Pin: SPI CLK */
#ifndef CYBSP_SPI_CLK
#define CYBSP_SPI_CLK (P12_2)
#endif
/** Pin: SPI CS */
#ifndef CYBSP_SPI_CS
#define CYBSP_SPI_CS (P12_4)
#endif
/** \} group_bsp_pins_comm */
@ -184,49 +261,93 @@ extern "C" {
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
#ifndef CYBSP_A0
#define CYBSP_A0 (P10_0)
#endif
/** Arduino A1 */
#define CYBSP_A1 P10_1
#ifndef CYBSP_A1
#define CYBSP_A1 (P10_1)
#endif
/** Arduino A2 */
#define CYBSP_A2 P10_2
#ifndef CYBSP_A2
#define CYBSP_A2 (P10_2)
#endif
/** Arduino A3 */
#define CYBSP_A3 P10_3
#ifndef CYBSP_A3
#define CYBSP_A3 (P10_3)
#endif
/** Arduino A4 */
#define CYBSP_A4 P10_4
#ifndef CYBSP_A4
#define CYBSP_A4 (P10_4)
#endif
/** Arduino A5 */
#define CYBSP_A5 P10_5
#ifndef CYBSP_A5
#define CYBSP_A5 (P10_5)
#endif
/** Arduino D0 */
#ifndef CYBSP_D0
#define CYBSP_D0 (P5_0)
#endif
/** Arduino D1 */
#ifndef CYBSP_D1
#define CYBSP_D1 (P5_1)
#endif
/** Arduino D2 */
#ifndef CYBSP_D2
#define CYBSP_D2 (P5_2)
#endif
/** Arduino D3 */
#ifndef CYBSP_D3
#define CYBSP_D3 (P5_3)
#endif
/** Arduino D4 */
#ifndef CYBSP_D4
#define CYBSP_D4 (P5_4)
#endif
/** Arduino D5 */
#ifndef CYBSP_D5
#define CYBSP_D5 (P5_5)
#endif
/** Arduino D6 */
#ifndef CYBSP_D6
#define CYBSP_D6 (P5_6)
#endif
/** Arduino D7 */
#ifndef CYBSP_D7
#define CYBSP_D7 (P0_2)
#endif
/** Arduino D8 */
#ifndef CYBSP_D8
#define CYBSP_D8 (P13_0)
#endif
/** Arduino D9 */
#ifndef CYBSP_D9
#define CYBSP_D9 (P13_1)
#endif
/** Arduino D10 */
#ifndef CYBSP_D10
#define CYBSP_D10 (P12_3)
#endif
/** Arduino D11 */
#ifndef CYBSP_D11
#define CYBSP_D11 (P12_0)
#endif
/** Arduino D12 */
#ifndef CYBSP_D12
#define CYBSP_D12 (P12_1)
#endif
/** Arduino D13 */
#ifndef CYBSP_D13
#define CYBSP_D13 (P12_2)
#endif
/** Arduino D14 */
#ifndef CYBSP_D14
#define CYBSP_D14 (P6_1)
#endif
/** Arduino D15 */
#ifndef CYBSP_D15
#define CYBSP_D15 (P6_0)
#endif
/** \} group_bsp_pins_arduino */
@ -237,45 +358,85 @@ extern "C" {
*/
/** Cypress J2 Header pin 1 */
#ifndef CYBSP_J2_1
#define CYBSP_J2_1 (CYBSP_A0)
#endif
/** Cypress J2 Header pin 2 */
#ifndef CYBSP_J2_2
#define CYBSP_J2_2 (P9_0)
#endif
/** Cypress J2 Header pin 3 */
#ifndef CYBSP_J2_3
#define CYBSP_J2_3 (CYBSP_A1)
#endif
/** Cypress J2 Header pin 4 */
#ifndef CYBSP_J2_4
#define CYBSP_J2_4 (P9_1)
#endif
/** Cypress J2 Header pin 5 */
#ifndef CYBSP_J2_5
#define CYBSP_J2_5 (CYBSP_A2)
#endif
/** Cypress J2 Header pin 6 */
#ifndef CYBSP_J2_6
#define CYBSP_J2_6 (P9_2)
#endif
/** Cypress J2 Header pin 7 */
#ifndef CYBSP_J2_7
#define CYBSP_J2_7 (CYBSP_A3)
#endif
/** Cypress J2 Header pin 8 */
#ifndef CYBSP_J2_8
#define CYBSP_J2_8 (P9_3)
#endif
/** Cypress J2 Header pin 9 */
#ifndef CYBSP_J2_9
#define CYBSP_J2_9 (CYBSP_A4)
#endif
/** Cypress J2 Header pin 10 */
#ifndef CYBSP_J2_10
#define CYBSP_J2_10 (P9_4)
#endif
/** Cypress J2 Header pin 11 */
#ifndef CYBSP_J2_11
#define CYBSP_J2_11 (CYBSP_A5)
#endif
/** Cypress J2 Header pin 12 */
#ifndef CYBSP_J2_12
#define CYBSP_J2_12 (P9_5)
#endif
/** Cypress J2 Header pin 13 */
#ifndef CYBSP_J2_13
#define CYBSP_J2_13 (P10_6)
#endif
/** Cypress J2 Header pin 14 */
#ifndef CYBSP_J2_14
#define CYBSP_J2_14 (NC)
#endif
/** Cypress J2 Header pin 15 */
#ifndef CYBSP_J2_15
#define CYBSP_J2_15 (P6_2)
#endif
/** Cypress J2 Header pin 16 */
#ifndef CYBSP_J2_16
#define CYBSP_J2_16 (P9_6)
#endif
/** Cypress J2 Header pin 17 */
#ifndef CYBSP_J2_17
#define CYBSP_J2_17 (P6_3)
#endif
/** Cypress J2 Header pin 18 */
#ifndef CYBSP_J2_18
#define CYBSP_J2_18 (P9_7)
#endif
/** Cypress J2 Header pin 19 */
#ifndef CYBSP_J2_19
#define CYBSP_J2_19 (P13_6)
#endif
/** Cypress J2 Header pin 20 */
#ifndef CYBSP_J2_20
#define CYBSP_J2_20 (P13_7)
#endif
/** \} group_bsp_pins_j2 */

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm0plus.sct
;* \version 2.70
;* \version 2.70.1
;*
;* Linker file for the ARMCC.
;*
@ -26,7 +26,7 @@
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm0plus.ld
* \version 2.70
* \version 2.70.1
*
* Linker file for the GNU C compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
/*******************************************************************************
* \file cy8c6xx7_cm0plus.icf
* \version 2.70
* \version 2.70.1
*
* Linker file for the IAR compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Public RAM */
define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000);
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm0plus.c
* \version 2.70
* \version 2.70.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.70
;* \version 2.70.1
;*
;* Linker file for the ARMCC.
;*
@ -26,7 +26,7 @@
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
@ -42,6 +42,9 @@
;* limitations under the License.
;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.70
* \version 2.70.1
*
* Linker file for the GNU C compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -40,6 +40,10 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
/*******************************************************************************
* \file cy8c6xx7_cm4_dual.icf
* \version 2.70
* \version 2.70.1
*
* Linker file for the IAR compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -41,6 +41,10 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.70
* \version 2.70.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

172
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.70
* \version 2.70.1
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,6 @@
* * \ref group_system_config_single_core_device_initialization
* - \ref group_system_config_device_memory_definition
* - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps
* - \ref group_system_config_default_handlers
* - \ref group_system_config_device_vector_table
* - \ref group_system_config_cm4_functions
@ -56,44 +55,58 @@
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* \note For the PSoC 64 Secure MCUs devices, refer to the following page:
* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide
*
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either:
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
* of the Cortex-M0+ application should be the same value as the flash LENGTH in
* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
* Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* <b>ARM MDK</b>\n
* <b>ARM Compiler</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
@ -106,29 +119,32 @@
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group:
* - 'xx_cm0plus.sct', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define FLASH_SIZE 0x00002000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* #define RAM_SIZE 0x00002000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
* - 'xx_cm4_dual.sct', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00100000
* #define RAM_START 0x08002000
* #define RAM_SIZE 0x00045800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either:
* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
* Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
@ -138,32 +154,39 @@
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either:
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
* 'xx_cm0plus.icf'. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code
@ -189,7 +212,9 @@
* -# Editing source code files
* -# Specifying via command line
*
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
* By default, the stack size is set to 0x00001000 and the heap size is allocated
* dynamically to the whole available free memory up to stack memory and it
* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
*
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
* - <b>Editing source code files</b>\n
@ -198,28 +223,23 @@
* Change the heap and stack sizes by modifying the following lines:\n
* \code .equ Stack_Size, 0x00001000 \endcode
* \code .equ Heap_Size, 0x00000400 \endcode
* Also, the stack size is defined in the linker script files: 'xx_yy.ld',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n
* \code -D __STACK_SIZE=0x000000400 \endcode
* \code -D __HEAP_SIZE=0x000000100 \endcode
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
* The stack size is defined in the linker script files: 'xx_yy.sct',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n
@ -232,21 +252,6 @@
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
*
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default
* values.
*
* The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific.
*
* The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data.
*
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
@ -273,10 +278,10 @@
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* The code in these files copies the vector table from Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler
* The linker script file is 'xx_yy.sct', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and
* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
@ -291,10 +296,6 @@
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_more_information More Information
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
* more details.
*
* \section group_system_config_MISRA MISRA Compliance
*
* <table class="doxtable">
@ -320,6 +321,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.70.1</td>
* <td>Updated documentation for the better description of the existing startup implementation.</td>
* <td>User experience enhancement.</td>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -4,8 +4,8 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -4,8 +4,8 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file → Executable file
View File

@ -4,8 +4,8 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -27,7 +27,7 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -5,8 +5,8 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -26,7 +26,7 @@
#include "cycfg_peripherals.h"
cy_stc_csd_context_t cy_csd_0_context =
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

68
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -26,7 +26,7 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,

36
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -57,7 +57,7 @@ extern "C" {
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -81,7 +81,7 @@ extern "C" {
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -105,7 +105,7 @@ extern "C" {
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -129,7 +129,7 @@ extern "C" {
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
@ -153,7 +153,7 @@ extern "C" {
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
@ -177,7 +177,7 @@ extern "C" {
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
@ -201,7 +201,7 @@ extern "C" {
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -225,7 +225,7 @@ extern "C" {
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -249,7 +249,7 @@ extern "C" {
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -273,7 +273,7 @@ extern "C" {
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -297,7 +297,7 @@ extern "C" {
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -321,7 +321,7 @@ extern "C" {
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -345,7 +345,7 @@ extern "C" {
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -369,7 +369,7 @@ extern "C" {
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -393,7 +393,7 @@ extern "C" {
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -417,7 +417,7 @@ extern "C" {
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -4,7 +4,8 @@
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -4,7 +4,8 @@
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -4,8 +4,8 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,8 +4,8 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -40,16 +40,16 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus)
}

83
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -4,8 +4,8 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -72,7 +72,7 @@
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 20U,
@ -86,7 +86,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
@ -94,7 +94,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
@ -102,7 +102,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
@ -110,7 +110,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
@ -118,14 +118,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
@ -255,14 +255,14 @@ __STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
@ -293,7 +293,7 @@ void init_cycfg_system(void)
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
@ -304,59 +304,59 @@ void init_cycfg_system(void)
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
{
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
@ -366,7 +366,7 @@ void init_cycfg_system(void)
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
@ -413,21 +413,21 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
@ -474,7 +474,7 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
@ -521,48 +521,49 @@ void init_cycfg_system(void)
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
Cy_SysClk_IloHibernateOn(false);
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,8 +4,8 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,4 +1,3 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

17
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
View File

@ -1,13 +1,6 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 185
-->
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0.1483-->
<Configuration app="Capsense" major="2" minor="0">
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
@ -121,12 +114,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
@ -223,12 +216,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
@ -325,12 +318,12 @@
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
View File

@ -1,5 +1,5 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -75,14 +75,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[2]"/>
<Block location="ioss[0].port[11].pin[3]"/>
<Block location="ioss[0].port[11].pin[4]"/>
<Block location="ioss[0].port[11].pin[5]"/>
<Block location="ioss[0].port[11].pin[6]"/>
<Block location="ioss[0].port[11].pin[7]"/>
<Block location="ioss[0].port[14].pin[0]"/>
<Block location="ioss[0].port[14].pin[1]"/>
<Block location="ioss[0].port[1].pin[0]">
<Alias value="CYBSP_CSD_TX"/>
<Personality template="mxs40pin" version="1.1">
@ -96,16 +88,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[2].pin[7]"/>
<Block location="ioss[0].port[3].pin[0]"/>
<Block location="ioss[0].port[3].pin[1]"/>
<Block location="ioss[0].port[3].pin[2]"/>
<Block location="ioss[0].port[3].pin[3]"/>
<Block location="ioss[0].port[3].pin[4]"/>
<Block location="ioss[0].port[3].pin[5]"/>
<Block location="ioss[0].port[4].pin[0]"/>
<Block location="ioss[0].port[6].pin[0]"/>
<Block location="ioss[0].port[6].pin[1]"/>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
@ -275,8 +257,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[0]"/>
<Block location="peri[0].div_8[1]"/>
<Block location="peri[0].div_8[3]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Personality template="mxs40peripheralclock" version="1.0">
@ -285,10 +265,6 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[4]"/>
<Block location="scb[2]"/>
<Block location="scb[3]"/>
<Block location="smif[0]"/>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
@ -411,7 +387,6 @@
<Param id="accuracyPpm" value="150"/>
</Personality>
</Block>
<Block location="srss[0].mcwdt[0]"/>
<Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.2">
<Param id="pwrMode" value="LDO_1_1"/>
@ -429,8 +404,6 @@
<Param id="vddio1Mv" value="3300"/>
</Personality>
</Block>
<Block location="srss[0].rtc[0]"/>
<Block location="usb[0]"/>
</BlockConfig>
<Netlist>
<Net>

1509
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
View File

File diff suppressed because it is too large Load Diff

396
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h
View File

@ -1,396 +0,0 @@
/***************************************************************************//**
* \file SDIO_HOST.h
*
* \brief
* This file provides types definition, constants and function definition for
* the SDIO driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \defgroup group_bsp_pin_state Pin States
* \defgroup group_bsp_pins Pin Mappings
* \defgroup group_bsp_macros Macros
* \defgroup group_bsp_functions Functions
*
* \defgroup group_udb_sdio UDB_SDIO
* \{
* SDIO - Secure Digital Input Output is a standard for communicating with various
external devices such as Wifi and bluetooth devices.
* <p>
* The driver is currently designed to only support communication with certain
* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general
* SDIO card, or even and SD card. It is only intended to be used by the WiFi
* driver for communication.
* <p>
* This is not intended to be used as a general purpose API.
*
* \section group_udb_sdio_section_configuration_considerations Configuration Considerations
* Features:
* * Always Four Wire Mode
* * Supports Card Interrupt
* * Uses DMA for command and data transfer
*
* \defgroup group_udb_sdio_macros Macros
* \defgroup group_udb_sdio_functions Functions
* \defgroup group_udb_sdio_data_structures Data Structures
*/
#if !defined(CY_SDIO_H)
#define CY_SDIO_H
#include "SDIO_HOST_cfg.h"
#if defined(__cplusplus)
extern "C" {
#endif
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_udb_sdio_macros
* \{
*/
#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/
#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/
#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/
#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/
/*!
\defgroup group_sdio_cmd_constants Constants for the command channel
*/
/* @{*/
#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */
#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/
#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/
#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/
/*@} group_sdio_cmd_constants */
/*!
\defgroup group_sdio_ctrl_reg SDIO control register bits
*/
/* @{*/
#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/
#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/
#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/
#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/
#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/
#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/
#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/
#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/
/*@} group_sdio_ctrl_reg */
/*!
\defgroup group_sdio_status_reg SDIO status register bits
*/
/* @{*/
#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/
#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/
#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/
#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/
#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/
#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/
#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/
/*@} group_sdio_status_reg */
/*!
\defgroup group_sdio_crc Constants for 7bit CRC for command
*/
/* @{*/
#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/
#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/
/*@} group_sdio_crc */
/** \} group_udb_sdio_macros */
/***************************************
* Type Definitions
***************************************/
/**
* \addtogroup group_udb_sdio_data_structures
* \{
*/
/**
* Create a type for the card interrupt call back
*/
typedef void (* sdio_card_int_cb_t)(void);
/**
* \brief This enum is used when checking for specific events
*/
typedef enum en_sdio_event
{
SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/
SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/
}en_sdio_event_t;
/**
* \brief Used to indicate the result of a function
*/
typedef enum en_sdio_result
{
Ok = 0x00, /**< No error*/
Error = 0x01, /**< Non-specific error code*/
CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/
CommandIdxError = 0x04, /**< The index for the command didn't match*/
CommandEndError = 0x08, /**< There was an end bit error on the command*/
DataCrcError = 0x10, /**< There was a data CRC Error*/
CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/
DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/
ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/
} en_sdio_result_t;
/**
* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function
*/
typedef struct stc_sdcmd_event_flag
{
uint8_t u8CmdComplete; /**< If non-zero a command has completed*/
uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/
uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/
}stc_sdio_event_flag_t;
/**
* \brief Holds pointers to callback functions
*/
typedef struct stc_sdio_irq_cb
{
sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/
}stc_sdio_irq_cb_t;
/**
* \brief Global structure used to hold data from interrupt and other functions
*/
typedef struct stc_sdio_gInternalData
{
stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/
stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/
}stc_sdio_gInternalData_t;
/**
* \brief structure used for configuring command
*/
typedef struct stc_sdio_cmd_config
{
uint8_t u8CmdIndex; /**< Command index*/
uint32_t u32Argument; /**< The argument of command */
uint8_t bResponseRequired; /**< TRUE: A Response is required*/
uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/
}stc_sdio_cmd_config_t;
/**
* \brief structure used for the data channel
*/
typedef struct stc_sdio_data_config
{
uint8_t bRead; /**< TRUE: Read, FALSE: write*/
uint16_t u16BlockSize; /**< Block size*/
uint16_t u16BlockCount; /**< Holds the number of blocks to send*/
uint8_t *pu8Data; /**< Pointer data buffer*/
}stc_sdio_data_config_t;
/**
* \brief structure used for configuring command and data
*/
typedef struct stc_sdio_cmd
{
uint32_t u32CmdIdx; /**< Command index*/
uint32_t u32Arg; /**< The argument of command*/
uint32_t *pu32Response; /**< Pointer to location to store response*/
uint8_t *pu8Data; /**< Pointer data buffer*/
uint8_t bRead; /**< TRUE: Read, FALSE: write*/
uint16_t u16BlockCnt; /**< Number of blocks to send*/
uint16_t u16BlockSize; /**< Block size*/
}stc_sdio_cmd_t;
/** \} group_udb_sdio_data_structures */
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_udb_sdio_functions
* \{
*/
/* Main functions*/
void SDIO_Init(stc_sdio_irq_cb_t* pfuCb);
en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd);
void SDIO_EnableIntClock(void);
void SDIO_DisableIntClock(void);
void SDIO_EnableSdClk(void);
void SDIO_DisableSdClk(void);
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
void SDIO_Reset(void);
void SDIO_EnableChipInt(void);
void SDIO_DisableChipInt(void);
void SDIO_Free(void);
/*Low Level Functions*/
void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig);
en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf);
void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig);
en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType);
uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size);
void SDIO_SetBlockSize(uint8_t u8ByteCount);
void SDIO_SetNumBlocks(uint8_t u8BlockCount);
/*DMA setup function*/
void SDIO_SetupDMA(void);
/*Interrupt Function*/
void SDIO_IRQ(void);
void SDIO_READ_DMA_IRQ(void);
void SDIO_WRITE_DMA_IRQ(void);
void SDIO_Crc7Init(void);
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode);
/** \endcond */
/** \} group_udb_sdio_functions */
/***************************************
* Hardware Registers
***************************************/
/** \cond INTERNAL */
#define SDIO_CONTROL_REG (* (reg8 *) \
SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG)
#define SDIO_CONTROL_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG)
#define SDIO_STATUS_REG (* (reg8 *) \
SDIO_HOST_bSDIO_StatusReg__STATUS_REG)
#define SDIO_STATUS_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_StatusReg__STATUS_REG)
#define SDIO_STATUS_INT_MSK (* (reg8*) \
SDIO_HOST_bSDIO_StatusReg__MASK_REG)
#define SDIO_STATUS_AUX_CTL (* (reg8 *) \
SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG)
#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \
SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG)
#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG)
#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \
SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG)
#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG)
#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \
SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG)
#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG)
#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \
SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG)
#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG)
#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__A0_REG)
#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__A0_REG)
#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__D0_REG)
#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__D0_REG)
#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__A1_REG)
#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__A1_REG)
#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__D1_REG)
#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_blockCounter_u0__D1_REG)
#define SDIO_CMD_COMMAND_REG (* (reg8 *) \
SDIO_HOST_bSDIO_CMD__F0_REG)
#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \
SDIO_HOST_bSDIO_CMD__A0_REG)
#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_CMD__F0_REG)
#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \
SDIO_HOST_bSDIO_CMD__F1_REG)
#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \
SDIO_HOST_bSDIO_CMD__F1_REG)
#define SDIO_DAT_WRITE_REG (* (reg16 *) \
SDIO_HOST_bSDIO_Write_DP__F0_F1_REG)
#define SDIO_DAT_WRITE_PTR ( (reg16 *) \
SDIO_HOST_bSDIO_Write_DP__F0_F1_REG)
#define SDIO_DAT_READ_REG (* (reg16 *) \
SDIO_HOST_bSDIO_Read_DP__F0_F1_REG)
#define SDIO_DAT_READ_PTR ( (reg16 *) \
SDIO_HOST_bSDIO_Read_DP__F0_F1_REG)
#define SDIO_BYTE_COUNT_REG (* (reg8 *) \
SDIO_HOST_bSDIO_byteCounter__PERIOD_REG)
/** \endcond */
#if defined(__cplusplus)
}
#endif
#endif /* (CY_SDIO_H) */
/** \} group_udb_sdio */
/* [] END OF FILE */

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/***************************************************************************//**
* \file SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#if !defined(CY_SDIO_CFG_H)
#define CY_SDIO_CFG_H
#include <string.h>
#include "cy_dma.h"
#include "cy_sysclk.h"
#include "cy_trigmux.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u
#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u
#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u
#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu
#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u
#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u
#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u
#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu
#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu
#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu
#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu
#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu
#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu
#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu
#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu
#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu
#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu
#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu
#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu
#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u
#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u
#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u
#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u
#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u
#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u
#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u
#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u
#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u
#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u
#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u
#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u
#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u
#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u
#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u
#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u
#define CYDEV_UDB_DSI0_BASE 0x40346000u
#define CYDEV_UDB_DSI1_BASE 0x40346080u
#define CYDEV_UDB_DSI2_BASE 0x40346100u
#define CYDEV_UDB_DSI3_BASE 0x40346180u
#define CYDEV_UDB_DSI4_BASE 0x40346200u
#define CYDEV_UDB_DSI5_BASE 0x40346280u
#define CYDEV_UDB_DSI6_BASE 0x40346300u
#define CYDEV_UDB_DSI7_BASE 0x40346380u
#define CYDEV_UDB_DSI8_BASE 0x40346400u
#define CYDEV_UDB_DSI9_BASE 0x40346480u
#define CYDEV_UDB_DSI10_BASE 0x40346500u
#define CYDEV_UDB_DSI11_BASE 0x40346580u
#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u
/*************Defines for UDBs from Creator*****************************/
/***********These come for cyfitter.h**********************************/
/* TFT_DMA */
#define TFT_DMA_DW__BLOCK_HW DW0
#define TFT_DMA_DW__BLOCK_NUMBER 0u
#define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2
#define TFT_DMA_DW__CHANNEL_NUMBER 2u
#define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2
#define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2
/* TFT_CTRL */
#define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u
#define TFT_CTRL_Sync_ctrl_reg__0__POS 0
#define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u
#define TFT_CTRL_Sync_ctrl_reg__1__POS 1
#define TFT_CTRL_Sync_ctrl_reg__2__MASK 0x04u
#define TFT_CTRL_Sync_ctrl_reg__2__POS 2
#define TFT_CTRL_Sync_ctrl_reg__3__MASK 0x08u
#define TFT_CTRL_Sync_ctrl_reg__3__POS 3
#define TFT_CTRL_Sync_ctrl_reg__4__MASK 0x10u
#define TFT_CTRL_Sync_ctrl_reg__4__POS 4
#define TFT_CTRL_Sync_ctrl_reg__5__MASK 0x20u
#define TFT_CTRL_Sync_ctrl_reg__5__POS 5
#define TFT_CTRL_Sync_ctrl_reg__6__MASK 0x40u
#define TFT_CTRL_Sync_ctrl_reg__6__POS 6
#define TFT_CTRL_Sync_ctrl_reg__7__MASK 0x80u
#define TFT_CTRL_Sync_ctrl_reg__7__POS 7
#define TFT_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG 0x4034192Cu
#define TFT_CTRL_Sync_ctrl_reg__CONTROL_REG 0x4034172Cu
#define TFT_CTRL_Sync_ctrl_reg__CONTROL_ST_REG 0x4034032Cu
#define TFT_CTRL_Sync_ctrl_reg__COUNT_REG 0x4034172Cu
#define TFT_CTRL_Sync_ctrl_reg__COUNT_ST_REG 0x4034032Cu
#define TFT_CTRL_Sync_ctrl_reg__MASK 0xFFu
#define TFT_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG 0x4034042Cu
#define TFT_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG 0x4034042Cu
#define TFT_CTRL_Sync_ctrl_reg__PERIOD_REG 0x4034182Cu
#define TFT_CTRL_Sync_ctrl_reg__RC_CFG0 0x40342ADCu
#define TFT_CTRL_Sync_ctrl_reg__RC_CFG1 0x40342AE0u
#define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u
#define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u
/* SDIO_HOST */
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x4034131Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x4034141Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x4034151Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x4034101Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x4034111Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x4034121Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x4034131Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x4034141Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x4034151Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x4034001Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x4034101Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x4034111Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x4034011Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x4034121Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x4034131Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x403426C0u
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x403426C4u
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x403426C8u
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x403426CCu
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x403426D0u
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x403426E4u
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x403426E8u
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x403426ECu
#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x403426F0u
#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x4034021Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x4034141Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x4034151Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__MSK_DP_AUX_CTL_REG 0x4034041Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__PER_DP_AUX_CTL_REG 0x4034041Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x403426DCu
#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x403426E0u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__32BIT_COUNT_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__32BIT_PERIOD_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340320u
#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341720u
#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340320u
#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340420u
#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340420u
#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x4034285Cu
#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x40342860u
#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x40342854u
#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x40342858u
#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341620u
#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_MASK_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_REG 0x40341620u
#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341820u
#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340420u
#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340420u
#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x4034285Cu
#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x40342860u
#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x40342854u
#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x40342858u
#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340320u
#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340320u
#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341620u
#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341018u
#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341118u
#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341218u
#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341318u
#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341918u
#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341418u
#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341518u
#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341018u
#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341118u
#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341218u
#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341318u
#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341918u
#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341418u
#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341518u
#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340018u
#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341018u
#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341118u
#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340118u
#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341218u
#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341318u
#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341918u
#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342640u
#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342644u
#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342648u
#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034264Cu
#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342650u
#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342664u
#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342668u
#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034266Cu
#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342670u
#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340218u
#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341418u
#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341518u
#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034265Cu
#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342660u
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_CONTROL_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_COUNT_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_CONTROL_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_COUNT_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_MASK_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_PERIOD_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_MASK_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_PERIOD_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_COUNT_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_PERIOD_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034031Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034171Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034031Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034041Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034041Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x403426DCu
#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x403426E0u
#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x403426D4u
#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x403426D8u
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_REG 0x4034161Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_MASK_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_REG 0x4034161Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034181Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034041Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034041Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x403426DCu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x403426E0u
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x403426D4u
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x403426D8u
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034191Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034031Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034031Cu
#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034161Cu
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u
#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u
#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u
#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u
#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u
#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u
#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u
#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u
#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u
#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u
#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu
#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u
#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u
#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu
#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u
#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u
#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u
#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0
#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u
#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341814u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341814u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341814u
#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341814u
#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u
#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2
#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u
#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3
#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341814u
#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u
#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4
#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u
#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6
#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u
#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7
#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340314u
#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341714u
#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340314u
#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu
#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340414u
#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340414u
#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341814u
#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x403424DCu
#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x403424E0u
#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x403424D4u
#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x403424D8u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341000u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341100u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341200u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341300u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341900u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341400u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341500u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341000u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341100u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341200u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341300u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341900u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341400u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341500u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340000u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341000u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341100u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340100u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341200u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341300u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341900u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342040u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342044u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342048u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034204Cu
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342050u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342064u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342068u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034206Cu
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342070u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340200u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341400u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341500u
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034205Cu
#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342060u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341004u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341104u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341204u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341304u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341404u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341504u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341004u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341104u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341204u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341304u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341404u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341504u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340004u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341004u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341104u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340104u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341204u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341304u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403420C0u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403420C4u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403420C8u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403420CCu
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403420D0u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403420E4u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403420E8u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403420ECu
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403420F0u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340204u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341404u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341504u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__MSK_DP_AUX_CTL_REG 0x40340404u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__PER_DP_AUX_CTL_REG 0x40340404u
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403420DCu
#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403420E0u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341010u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341110u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341210u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341310u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341910u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341410u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341510u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A0_REG 0x40341010u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A1_REG 0x40341110u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D0_REG 0x40341210u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D1_REG 0x40341310u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_DP_AUX_CTL_REG 0x40341910u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F0_REG 0x40341410u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F1_REG 0x40341510u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340010u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341010u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341110u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340110u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341210u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341310u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341910u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342440u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342444u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342448u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x4034244Cu
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342450u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342464u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342468u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x4034246Cu
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342470u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340210u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341410u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341510u
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x4034245Cu
#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342460u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A0_REG 0x40341014u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A1_REG 0x40341114u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D0_REG 0x40341214u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D1_REG 0x40341314u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_DP_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F0_REG 0x40341414u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F1_REG 0x40341514u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A0_REG 0x40341014u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A1_REG 0x40341114u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D0_REG 0x40341214u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D1_REG 0x40341314u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_DP_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F0_REG 0x40341414u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F1_REG 0x40341514u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x40340014u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x40341014u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x40341114u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x40340114u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x40341214u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x40341314u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x403424C0u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x403424C4u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x403424C8u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x403424CCu
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x403424D0u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x403424E4u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x403424E8u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x403424ECu
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x403424F0u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x40340214u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x40341414u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x40341514u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x40340414u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x40340414u
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x403424DCu
#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x403424E0u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341028u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341128u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341228u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341328u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341928u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341428u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341528u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340028u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341028u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341128u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340128u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341228u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341328u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341928u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342A40u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342A44u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342A48u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x40342A4Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342A50u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342A64u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342A68u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x40342A6Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342A70u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340228u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341428u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341528u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__MSK_DP_AUX_CTL_REG 0x40340428u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__PER_DP_AUX_CTL_REG 0x40340428u
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x40342A5Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342A60u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x4034002Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x4034102Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x4034112Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x4034012Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x4034122Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x4034132Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x4034192Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x40342AC0u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x40342AC4u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x40342AC8u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x40342ACCu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x40342AD0u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x40342AE4u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x40342AE8u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x40342AECu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x40342AF0u
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x4034022Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x4034142Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x4034152Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x4034042Cu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x40342ADCu
#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x40342AE0u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341020u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341120u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341220u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341320u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341420u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341520u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341020u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341120u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341220u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341320u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341420u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341520u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340020u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341020u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341120u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340120u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341220u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341320u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341920u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342840u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342844u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342848u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034284Cu
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342850u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342864u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342868u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034286Cu
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342870u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340220u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341420u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341520u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340420u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340420u
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034285Cu
#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342860u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x40341024u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x40341124u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x40341224u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x40341324u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x40341924u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x40341424u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x40341524u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x40340024u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x40341024u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x40341124u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x40340124u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x40341224u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x40341324u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x40341924u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403428C0u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403428C4u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403428C8u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403428CCu
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403428D0u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403428E4u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403428E8u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403428ECu
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403428F0u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x40340224u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x40341424u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x40341524u
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403428DCu
#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403428E0u
#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x4034100Cu
#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x4034110Cu
#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x4034120Cu
#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x4034130Cu
#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu
#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x4034140Cu
#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x4034150Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x4034100Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x4034110Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x4034120Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x4034130Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x4034140Cu
#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x4034150Cu
#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x4034000Cu
#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x4034100Cu
#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x4034110Cu
#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x4034010Cu
#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x4034120Cu
#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x4034130Cu
#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x4034190Cu
#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403422C0u
#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403422C4u
#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403422C8u
#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403422CCu
#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403422D0u
#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403422E4u
#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403422E8u
#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403422ECu
#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403422F0u
#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x4034020Cu
#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x4034140Cu
#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x4034150Cu
#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403422DCu
#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403422E0u
#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x4034190Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x4034160Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x4034180Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x4034190Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x4034160Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x4034180Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403422DCu
#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403422E0u
#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403422D4u
#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403422D8u
#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x4034190Cu
#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x4034160Cu
#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u
#define SDIO_HOST_bSDIO_StatusReg__0__POS 0
#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u
#define SDIO_HOST_bSDIO_StatusReg__1__POS 1
#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341614u
#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u
#define SDIO_HOST_bSDIO_StatusReg__2__POS 2
#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u
#define SDIO_HOST_bSDIO_StatusReg__3__POS 3
#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341814u
#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341614u
#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u
#define SDIO_HOST_bSDIO_StatusReg__6__POS 6
#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu
#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341814u
#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340414u
#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340414u
#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x403424DCu
#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x403424E0u
#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x403424D4u
#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x403424D8u
#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341914u
#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340314u
#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340314u
#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341614u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x40341008u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x40341108u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x40341208u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x40341308u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x40341908u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x40341408u
#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x40341508u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x40341008u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x40341108u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x40341208u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x40341308u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x40341908u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x40341408u
#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x40341508u
#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x40340008u
#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x40341008u
#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x40341108u
#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x40340108u
#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x40341208u
#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x40341308u
#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x40341908u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x40342240u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x40342244u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x40342248u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x4034224Cu
#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x40342250u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x40342264u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x40342268u
#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x4034226Cu
#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x40342270u
#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x40340208u
#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x40341408u
#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x40341508u
#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x40340408u
#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x40340408u
#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x4034225Cu
#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x40342260u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x40341908u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x40341808u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x40341808u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x40341808u
#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x40341808u
#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x40341908u
#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x40341808u
#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x40341908u
#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x40340308u
#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x40341708u
#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x40340308u
#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x40340408u
#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x40340408u
#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x40341808u
#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x4034225Cu
#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x40342260u
#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x40342254u
#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x40342258u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340304u
#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341704u
#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340304u
#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340404u
#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340404u
#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x403420DCu
#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x403420E0u
#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x403420D4u
#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x403420D8u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341604u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341604u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341804u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340404u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340404u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x403420DCu
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x403420E0u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x403420D4u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x403420D8u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341904u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340304u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340304u
#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341604u
#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0
#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u
#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1
#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u
#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1
#define SDIO_HOST_Internal_Clock__DIV_IDX 0
#define SDIO_HOST_Internal_Clock__DIV_NUM 0
#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1
#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u
#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3
#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u
#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3
#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0
#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u
#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0
#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u
#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0
#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1
#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u
#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1
#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u
#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1
/***************************CMD DMA***************************************/
#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u)
#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_CMD_DMA_HW (DW0)
#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
#define SDIO_HOST_CMD_DMA_PRIORITY (1u)
#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
/***************************Read DMA***************************************/
#define SDIO_HOST_Read_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u)
#define SDIO_HOST_Read_DMA_HW (DW1)
#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
#define SDIO_HOST_Read_DMA_PRIORITY (0u)
#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Read_DMA_PREEMPTABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
/***************************Resp DMA***************************************/
#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u)
#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u)
#define SDIO_HOST_Resp_DMA_HW (DW0)
#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
#define SDIO_HOST_Resp_DMA_PRIORITY (1u)
#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
/***************************Write DMA***************************************/
#define SDIO_HOST_Write_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_Write_DMA_HW (DW1)
#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
#define SDIO_HOST_Write_DMA_PRIORITY (0u)
#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Write_DMA_PREEMPTABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
/***************************SDIO Clock**************************************/
/* The peripheral clock divider number */
#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0)
/* The peripheral clock divider type */
#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT)
/*Function for configuring TriggerMuxes*/
void SDIO_Host_Config_TriggerMuxes(void);
/*Function for configuring UDBs*/
void SDIO_Host_Config_UDBs(void);
/* SDIO_HOST_Read_Int */
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int__INTC_NUMBER 69u
#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int_INTC_NUMBER 69u
/* SDIO_HOST_sdio_int */
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int__INTC_NUMBER 122u
#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int_INTC_NUMBER 122u
/* SDIO_HOST_Write_Int */
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int__INTC_NUMBER 67u
#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int_INTC_NUMBER 67u
#if defined(__cplusplus)
}
#endif
#endif /* !defined(CY_SDIO_CFG_H) */
/* [] END OF FILE */

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c
View File

@ -2,12 +2,12 @@
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -29,6 +29,7 @@
#include "cybsp.h"
#if defined(CY_USING_HAL)
#include "cyhal_hwmgr.h"
#include "cyhal_syspm.h"
#endif
#if defined(__cplusplus)
@ -36,7 +37,7 @@ extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void)
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_syspm_init();
}
#else
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void)
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,9 +26,6 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#include "cyhal_sdio.h"
#endif
@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/

201
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -28,6 +28,9 @@
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(__cplusplus)
extern "C" {
@ -66,14 +69,22 @@ extern "C" {
*/
/** Pin state for the LED on. */
#ifndef CYBSP_LED_STATE_ON
#define CYBSP_LED_STATE_ON (0U)
#endif
/** Pin state for the LED off. */
#ifndef CYBSP_LED_STATE_OFF
#define CYBSP_LED_STATE_OFF (1U)
#endif
/** Pin state for when a button is pressed. */
#ifndef CYBSP_BTN_PRESSED
#define CYBSP_BTN_PRESSED (0U)
#endif
/** Pin state for when a button is released. */
#ifndef CYBSP_BTN_OFF
#define CYBSP_BTN_OFF (1U)
#endif
/** \} group_bsp_pin_state */
@ -90,28 +101,50 @@ extern "C" {
*/
/** LED 8; User LED1 */
#ifndef CYBSP_LED8
#define CYBSP_LED8 (P1_5)
#endif
/** LED 9; User LED2 */
#ifndef CYBSP_LED9
#define CYBSP_LED9 (P13_7)
#endif
/** LED 5: RGB LED - Red; User LED3 */
#ifndef CYBSP_LED_RGB_RED
#define CYBSP_LED_RGB_RED (P0_3)
#endif
/** LED 5: RGB LED - Green; User LED4 */
#ifndef CYBSP_LED_RGB_GREEN
#define CYBSP_LED_RGB_GREEN (P1_1)
#endif
/** LED 5: RGB LED - Blue; User LED5 */
#ifndef CYBSP_LED_RGB_BLUE
#define CYBSP_LED_RGB_BLUE (P11_1)
#endif
/** LED 8; User LED1 */
#ifndef CYBSP_USER_LED1
#define CYBSP_USER_LED1 (CYBSP_LED8)
#endif
/** LED 9; User LED2 */
#ifndef CYBSP_USER_LED2
#define CYBSP_USER_LED2 (CYBSP_LED9)
#endif
/** LED 5: RGB LED - Red; User LED3 */
#ifndef CYBSP_USER_LED3
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
#endif
/** LED 5: RGB LED - Green; User LED4 */
#ifndef CYBSP_USER_LED4
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
#endif
/** LED 5: RGB LED - Blue; User LED5 */
#ifndef CYBSP_USER_LED5
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
#endif
/** LED 8; User LED1 */
#ifndef CYBSP_USER_LED
#define CYBSP_USER_LED (CYBSP_USER_LED1)
#endif
/** \} group_bsp_pins_led */
@ -122,12 +155,18 @@ extern "C" {
*/
/** Switch 2; User Button 1 */
#ifndef CYBSP_SW2
#define CYBSP_SW2 (P0_4)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN1
#define CYBSP_USER_BTN1 (CYBSP_SW2)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
#endif
/** \} group_bsp_pins_btn */
@ -138,76 +177,140 @@ extern "C" {
*/
/** Pin: WIFI SDIO D0 */
#ifndef CYBSP_WIFI_SDIO_D0
#define CYBSP_WIFI_SDIO_D0 (P2_0)
#endif
/** Pin: WIFI SDIO D1 */
#ifndef CYBSP_WIFI_SDIO_D1
#define CYBSP_WIFI_SDIO_D1 (P2_1)
#endif
/** Pin: WIFI SDIO D2 */
#ifndef CYBSP_WIFI_SDIO_D2
#define CYBSP_WIFI_SDIO_D2 (P2_2)
#endif
/** Pin: WIFI SDIO D3 */
#ifndef CYBSP_WIFI_SDIO_D3
#define CYBSP_WIFI_SDIO_D3 (P2_3)
#endif
/** Pin: WIFI SDIO CMD */
#ifndef CYBSP_WIFI_SDIO_CMD
#define CYBSP_WIFI_SDIO_CMD (P2_4)
#endif
/** Pin: WIFI SDIO CLK */
#ifndef CYBSP_WIFI_SDIO_CLK
#define CYBSP_WIFI_SDIO_CLK (P2_5)
#endif
/** Pin: WIFI ON */
#ifndef CYBSP_WIFI_WL_REG_ON
#define CYBSP_WIFI_WL_REG_ON (P2_6)
#endif
/** Pin: WIFI Host Wakeup */
#ifndef CYBSP_WIFI_HOST_WAKE
#define CYBSP_WIFI_HOST_WAKE (P2_7)
#endif
/** Pin: BT UART RX */
#ifndef CYBSP_BT_UART_RX
#define CYBSP_BT_UART_RX (P3_0)
#endif
/** Pin: BT UART TX */
#ifndef CYBSP_BT_UART_TX
#define CYBSP_BT_UART_TX (P3_1)
#endif
/** Pin: BT UART RTS */
#ifndef CYBSP_BT_UART_RTS
#define CYBSP_BT_UART_RTS (P3_2)
#endif
/** Pin: BT UART CTS */
#ifndef CYBSP_BT_UART_CTS
#define CYBSP_BT_UART_CTS (P3_3)
#endif
/** Pin: BT Power */
#ifndef CYBSP_BT_POWER
#define CYBSP_BT_POWER (P3_4)
#endif
/** Pin: BT Host Wakeup */
#ifndef CYBSP_BT_HOST_WAKE
#define CYBSP_BT_HOST_WAKE (P3_5)
#endif
/** Pin: BT Device Wakeup */
#ifndef CYBSP_BT_DEVICE_WAKE
#define CYBSP_BT_DEVICE_WAKE (P4_0)
#endif
/** Pin: UART RX */
#ifndef CYBSP_DEBUG_UART_RX
#define CYBSP_DEBUG_UART_RX (P5_0)
#endif
/** Pin: UART TX */
#ifndef CYBSP_DEBUG_UART_TX
#define CYBSP_DEBUG_UART_TX (P5_1)
#endif
/** Pin: I2C SCL */
#ifndef CYBSP_I2C_SCL
#define CYBSP_I2C_SCL (P6_0)
#endif
/** Pin: I2C SDA */
#ifndef CYBSP_I2C_SDA
#define CYBSP_I2C_SDA (P6_1)
#endif
/** Pin: SWO */
#ifndef CYBSP_SWO
#define CYBSP_SWO (P6_4)
#endif
/** Pin: SWDIO */
#ifndef CYBSP_SWDIO
#define CYBSP_SWDIO (P6_6)
#endif
/** Pin: SWDCK */
#ifndef CYBSP_SWDCK
#define CYBSP_SWDCK (P6_7)
#endif
/** Pin: QUAD SPI SS */
#ifndef CYBSP_QSPI_SS
#define CYBSP_QSPI_SS (P11_2)
#endif
/** Pin: QUAD SPI D3 */
#ifndef CYBSP_QSPI_D3
#define CYBSP_QSPI_D3 (P11_3)
#endif
/** Pin: QUAD SPI D2 */
#ifndef CYBSP_QSPI_D2
#define CYBSP_QSPI_D2 (P11_4)
#endif
/** Pin: QUAD SPI D1 */
#ifndef CYBSP_QSPI_D1
#define CYBSP_QSPI_D1 (P11_5)
#endif
/** Pin: QUAD SPI D0 */
#ifndef CYBSP_QSPI_D0
#define CYBSP_QSPI_D0 (P11_6)
#endif
/** Pin: QUAD SPI SCK */
#ifndef CYBSP_QSPI_SCK
#define CYBSP_QSPI_SCK (P11_7)
#endif
/** Pin: SPI MOSI */
#ifndef CYBSP_SPI_MOSI
#define CYBSP_SPI_MOSI (P12_0)
#endif
/** Pin: SPI MISO */
#ifndef CYBSP_SPI_MISO
#define CYBSP_SPI_MISO (P12_1)
#endif
/** Pin: SPI CLK */
#ifndef CYBSP_SPI_CLK
#define CYBSP_SPI_CLK (P12_2)
#endif
/** Pin: SPI CS */
#ifndef CYBSP_SPI_CS
#define CYBSP_SPI_CS (P12_4)
#endif
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
@ -223,49 +326,93 @@ extern "C" {
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
#ifndef CYBSP_A0
#define CYBSP_A0 (P10_0)
#endif
/** Arduino A1 */
#define CYBSP_A1 P10_1
#ifndef CYBSP_A1
#define CYBSP_A1 (P10_1)
#endif
/** Arduino A2 */
#define CYBSP_A2 P10_2
#ifndef CYBSP_A2
#define CYBSP_A2 (P10_2)
#endif
/** Arduino A3 */
#define CYBSP_A3 P10_3
#ifndef CYBSP_A3
#define CYBSP_A3 (P10_3)
#endif
/** Arduino A4 */
#define CYBSP_A4 P10_4
#ifndef CYBSP_A4
#define CYBSP_A4 (P10_4)
#endif
/** Arduino A5 */
#define CYBSP_A5 P10_5
#ifndef CYBSP_A5
#define CYBSP_A5 (P10_5)
#endif
/** Arduino D0 */
#ifndef CYBSP_D0
#define CYBSP_D0 (P5_0)
#endif
/** Arduino D1 */
#ifndef CYBSP_D1
#define CYBSP_D1 (P5_1)
#endif
/** Arduino D2 */
#ifndef CYBSP_D2
#define CYBSP_D2 (P5_2)
#endif
/** Arduino D3 */
#ifndef CYBSP_D3
#define CYBSP_D3 (P5_3)
#endif
/** Arduino D4 */
#ifndef CYBSP_D4
#define CYBSP_D4 (P5_4)
#endif
/** Arduino D5 */
#ifndef CYBSP_D5
#define CYBSP_D5 (P5_5)
#endif
/** Arduino D6 */
#ifndef CYBSP_D6
#define CYBSP_D6 (P5_6)
#endif
/** Arduino D7 */
#ifndef CYBSP_D7
#define CYBSP_D7 (P0_2)
#endif
/** Arduino D8 */
#ifndef CYBSP_D8
#define CYBSP_D8 (P13_0)
#endif
/** Arduino D9 */
#ifndef CYBSP_D9
#define CYBSP_D9 (P13_1)
#endif
/** Arduino D10 */
#ifndef CYBSP_D10
#define CYBSP_D10 (P12_3)
#endif
/** Arduino D11 */
#ifndef CYBSP_D11
#define CYBSP_D11 (P12_0)
#endif
/** Arduino D12 */
#ifndef CYBSP_D12
#define CYBSP_D12 (P12_1)
#endif
/** Arduino D13 */
#ifndef CYBSP_D13
#define CYBSP_D13 (P12_2)
#endif
/** Arduino D14 */
#ifndef CYBSP_D14
#define CYBSP_D14 (P6_1)
#endif
/** Arduino D15 */
#ifndef CYBSP_D15
#define CYBSP_D15 (P6_0)
#endif
/** \} group_bsp_pins_arduino */
@ -276,45 +423,85 @@ extern "C" {
*/
/** Cypress J2 Header pin 1 */
#ifndef CYBSP_J2_1
#define CYBSP_J2_1 (CYBSP_A0)
#endif
/** Cypress J2 Header pin 2 */
#ifndef CYBSP_J2_2
#define CYBSP_J2_2 (P9_0)
#endif
/** Cypress J2 Header pin 3 */
#ifndef CYBSP_J2_3
#define CYBSP_J2_3 (CYBSP_A1)
#endif
/** Cypress J2 Header pin 4 */
#ifndef CYBSP_J2_4
#define CYBSP_J2_4 (P9_1)
#endif
/** Cypress J2 Header pin 5 */
#ifndef CYBSP_J2_5
#define CYBSP_J2_5 (CYBSP_A2)
#endif
/** Cypress J2 Header pin 6 */
#ifndef CYBSP_J2_6
#define CYBSP_J2_6 (P9_2)
#endif
/** Cypress J2 Header pin 7 */
#ifndef CYBSP_J2_7
#define CYBSP_J2_7 (CYBSP_A3)
#endif
/** Cypress J2 Header pin 8 */
#ifndef CYBSP_J2_8
#define CYBSP_J2_8 (P9_3)
#endif
/** Cypress J2 Header pin 9 */
#ifndef CYBSP_J2_9
#define CYBSP_J2_9 (CYBSP_A4)
#endif
/** Cypress J2 Header pin 10 */
#ifndef CYBSP_J2_10
#define CYBSP_J2_10 (P9_4)
#endif
/** Cypress J2 Header pin 11 */
#ifndef CYBSP_J2_11
#define CYBSP_J2_11 (CYBSP_A5)
#endif
/** Cypress J2 Header pin 12 */
#ifndef CYBSP_J2_12
#define CYBSP_J2_12 (P9_5)
#endif
/** Cypress J2 Header pin 13 */
#ifndef CYBSP_J2_13
#define CYBSP_J2_13 (P10_6)
#endif
/** Cypress J2 Header pin 14 */
#ifndef CYBSP_J2_14
#define CYBSP_J2_14 (NC)
#endif
/** Cypress J2 Header pin 15 */
#ifndef CYBSP_J2_15
#define CYBSP_J2_15 (P6_2)
#endif
/** Cypress J2 Header pin 16 */
#ifndef CYBSP_J2_16
#define CYBSP_J2_16 (P9_6)
#endif
/** Cypress J2 Header pin 17 */
#ifndef CYBSP_J2_17
#define CYBSP_J2_17 (P6_3)
#endif
/** Cypress J2 Header pin 18 */
#ifndef CYBSP_J2_18
#define CYBSP_J2_18 (P9_7)
#endif
/** Cypress J2 Header pin 19 */
#ifndef CYBSP_J2_19
#define CYBSP_J2_19 (P13_6)
#endif
/** Cypress J2 Header pin 20 */
#ifndef CYBSP_J2_20
#define CYBSP_J2_20 (P13_7)
#endif
/** \} group_bsp_pins_j2 */

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm0plus.sct
;* \version 2.70
;* \version 2.70.1
;*
;* Linker file for the ARMCC.
;*
@ -26,7 +26,7 @@
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm0plus.ld
* \version 2.70
* \version 2.70.1
*
* Linker file for the GNU C compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
/*******************************************************************************
* \file cy8c6xx7_cm0plus.icf
* \version 2.70
* \version 2.70.1
*
* Linker file for the IAR compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Public RAM */
define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000);
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm0plus.c
* \version 2.70
* \version 2.70.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.70
;* \version 2.70.1
;*
;* Linker file for the ARMCC.
;*
@ -26,7 +26,7 @@
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
@ -42,6 +42,9 @@
;* limitations under the License.
;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.70
* \version 2.70.1
*
* Linker file for the GNU C compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -40,6 +40,10 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
/*******************************************************************************
* \file cy8c6xx7_cm4_dual.icf
* \version 2.70
* \version 2.70.1
*
* Linker file for the IAR compiler.
*
@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -41,6 +41,10 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.70
* \version 2.70.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

172
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h
View File

@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.70
* \version 2.70.1
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,6 @@
* * \ref group_system_config_single_core_device_initialization
* - \ref group_system_config_device_memory_definition
* - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps
* - \ref group_system_config_default_handlers
* - \ref group_system_config_device_vector_table
* - \ref group_system_config_cm4_functions
@ -56,44 +55,58 @@
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* \note For the PSoC 64 Secure MCUs devices, refer to the following page:
* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide
*
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either:
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
* of the Cortex-M0+ application should be the same value as the flash LENGTH in
* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
* Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* <b>ARM MDK</b>\n
* <b>ARM Compiler</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
@ -106,29 +119,32 @@
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group:
* - 'xx_cm0plus.sct', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define FLASH_SIZE 0x00002000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* #define RAM_SIZE 0x00002000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
* - 'xx_cm4_dual.sct', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00100000
* #define RAM_START 0x08002000
* #define RAM_SIZE 0x00045800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either:
* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
* Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
@ -138,32 +154,39 @@
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either:
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
* 'xx_cm0plus.icf'. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
* or
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
* 'xx' is the device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
*
* \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code
@ -189,7 +212,9 @@
* -# Editing source code files
* -# Specifying via command line
*
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
* By default, the stack size is set to 0x00001000 and the heap size is allocated
* dynamically to the whole available free memory up to stack memory and it
* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
*
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
* - <b>Editing source code files</b>\n
@ -198,28 +223,23 @@
* Change the heap and stack sizes by modifying the following lines:\n
* \code .equ Stack_Size, 0x00001000 \endcode
* \code .equ Heap_Size, 0x00000400 \endcode
* Also, the stack size is defined in the linker script files: 'xx_yy.ld',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n
* \code -D __STACK_SIZE=0x000000400 \endcode
* \code -D __HEAP_SIZE=0x000000100 \endcode
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
* The stack size is defined in the linker script files: 'xx_yy.sct',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n
@ -232,21 +252,6 @@
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
*
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default
* values.
*
* The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific.
*
* The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data.
*
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
@ -273,10 +278,10 @@
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* The code in these files copies the vector table from Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler
* The linker script file is 'xx_yy.sct', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and
* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
@ -291,10 +296,6 @@
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_more_information More Information
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
* more details.
*
* \section group_system_config_MISRA MISRA Compliance
*
* <table class="doxtable">
@ -320,6 +321,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.70.1</td>
* <td>Updated documentation for the better description of the existing startup implementation.</td>
* <td>User experience enhancement.</td>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
* <td>Code optimization.</td>

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