From f38e21fa6cf79bf8cc738707ee12110330e69b56 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Wed, 29 Apr 2020 17:12:29 -0700 Subject: [PATCH] Update PSoC 6 BSPs to verion 1.2 --- .../GeneratedSource/cycfg.c | 4 +- .../GeneratedSource/cycfg.h | 4 +- .../GeneratedSource/cycfg.timestamp | 4 +- .../GeneratedSource/cycfg_clocks.c | 6 +- .../GeneratedSource/cycfg_clocks.h | 4 +- .../GeneratedSource/cycfg_notices.h | 4 +- .../GeneratedSource/cycfg_peripherals.c | 6 +- .../GeneratedSource/cycfg_peripherals.h | 4 +- .../GeneratedSource/cycfg_pins.c | 68 +- .../GeneratedSource/cycfg_pins.h | 36 +- .../GeneratedSource/cycfg_qspi_memslot.c | 3 +- .../GeneratedSource/cycfg_qspi_memslot.h | 3 +- .../GeneratedSource/cycfg_routing.c | 4 +- .../GeneratedSource/cycfg_routing.h | 20 +- .../GeneratedSource/cycfg_system.c | 79 +- .../GeneratedSource/cycfg_system.h | 2 +- .../GeneratedSource/qspi_config.cfg | 1 - .../design.cycapsense | 8 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 2 +- .../TARGET_CY8CKIT_062S2_43012/cybsp.c | 16 +- .../TARGET_CY8CKIT_062S2_43012/cybsp.h | 7 +- .../TARGET_CY8CKIT_062S2_43012/cybsp_types.h | 201 ++- .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 4 +- .../GeneratedSource/cycfg.h | 4 +- .../GeneratedSource/cycfg.timestamp | 4 +- .../GeneratedSource/cycfg_clocks.c | 6 +- .../GeneratedSource/cycfg_clocks.h | 4 +- .../GeneratedSource/cycfg_notices.h | 4 +- .../GeneratedSource/cycfg_peripherals.c | 8 +- .../GeneratedSource/cycfg_peripherals.h | 4 +- .../GeneratedSource/cycfg_pins.c | 68 +- .../GeneratedSource/cycfg_pins.h | 36 +- .../GeneratedSource/cycfg_qspi_memslot.c | 47 +- .../GeneratedSource/cycfg_qspi_memslot.h | 25 +- .../GeneratedSource/cycfg_routing.c | 4 +- .../GeneratedSource/cycfg_routing.h | 22 +- .../GeneratedSource/cycfg_system.c | 83 +- .../GeneratedSource/cycfg_system.h | 4 +- .../GeneratedSource/qspi_config.cfg | 1 - .../design.cycapsense | 17 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 13 - .../TARGET_CY8CKIT_062_BLE/cybsp.c | 16 +- .../TARGET_CY8CKIT_062_BLE/cybsp.h | 7 +- .../TARGET_CY8CKIT_062_BLE/cybsp_types.h | 175 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 4 +- .../GeneratedSource/cycfg.h | 4 +- .../GeneratedSource/cycfg.timestamp | 4 +- .../GeneratedSource/cycfg_clocks.c | 6 +- .../GeneratedSource/cycfg_clocks.h | 4 +- .../GeneratedSource/cycfg_notices.h | 4 +- .../GeneratedSource/cycfg_peripherals.c | 6 +- .../GeneratedSource/cycfg_peripherals.h | 4 +- .../GeneratedSource/cycfg_pins.c | 68 +- .../GeneratedSource/cycfg_pins.h | 36 +- .../GeneratedSource/cycfg_qspi_memslot.c | 3 +- .../GeneratedSource/cycfg_qspi_memslot.h | 3 +- .../GeneratedSource/cycfg_routing.c | 4 +- .../GeneratedSource/cycfg_routing.h | 22 +- .../GeneratedSource/cycfg_system.c | 83 +- .../GeneratedSource/cycfg_system.h | 4 +- .../GeneratedSource/qspi_config.cfg | 1 - .../design.cycapsense | 17 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 27 - .../SDIO_HOST/SDIO_HOST.c | 1509 ----------------- .../SDIO_HOST/SDIO_HOST.h | 396 ----- .../SDIO_HOST/SDIO_HOST_cfg.c | 1056 ------------ .../SDIO_HOST/SDIO_HOST_cfg.h | 931 ---------- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp.c | 16 +- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp.h | 7 +- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h | 201 ++- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 4 +- .../GeneratedSource/cycfg.h | 4 +- .../GeneratedSource/cycfg.timestamp | 4 +- .../GeneratedSource/cycfg_clocks.c | 6 +- .../GeneratedSource/cycfg_clocks.h | 4 +- .../GeneratedSource/cycfg_notices.h | 4 +- .../GeneratedSource/cycfg_peripherals.c | 6 +- .../GeneratedSource/cycfg_peripherals.h | 4 +- .../GeneratedSource/cycfg_pins.c | 68 +- .../GeneratedSource/cycfg_pins.h | 36 +- .../GeneratedSource/cycfg_qspi_memslot.c | 3 +- .../GeneratedSource/cycfg_qspi_memslot.h | 3 +- .../GeneratedSource/cycfg_routing.c | 4 +- .../GeneratedSource/cycfg_routing.h | 6 +- .../GeneratedSource/cycfg_system.c | 83 +- .../GeneratedSource/cycfg_system.h | 4 +- .../GeneratedSource/qspi_config.cfg | 1 - .../design.cycapsense | 17 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 27 - .../TARGET_CY8CKIT_064S2_4343W/cybsp.c | 16 +- .../TARGET_CY8CKIT_064S2_4343W/cybsp.h | 7 +- .../TARGET_CY8CKIT_064S2_4343W/cybsp_types.h | 201 ++- .../TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cyb06xxa_cm4.sct | 50 +- .../TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld | 51 +- .../TOOLCHAIN_IAR/cyb06xxa_cm4.icf | 10 +- .../device/COMPONENT_CM4/device_cfg.h | 27 - .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg.timestamp | 2 +- .../GeneratedSource/cycfg_clocks.c | 4 +- .../GeneratedSource/cycfg_clocks.h | 2 +- .../GeneratedSource/cycfg_notices.h | 2 +- .../GeneratedSource/cycfg_peripherals.c | 4 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.c | 50 +- .../GeneratedSource/cycfg_pins.h | 26 +- .../GeneratedSource/cycfg_qspi_memslot.c | 2 +- .../GeneratedSource/cycfg_qspi_memslot.h | 2 +- .../GeneratedSource/cycfg_routing.c | 2 +- .../GeneratedSource/cycfg_routing.h | 2 +- .../GeneratedSource/cycfg_system.c | 77 +- .../GeneratedSource/cycfg_system.h | 2 +- .../design.cycapsense | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 6 +- .../TARGET_CY8CPROTO_062S3_4343W/cybsp.c | 16 +- .../TARGET_CY8CPROTO_062S3_4343W/cybsp.h | 7 +- .../cybsp_types.h | 77 +- .../TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg.timestamp | 2 +- .../GeneratedSource/cycfg_clocks.c | 4 +- .../GeneratedSource/cycfg_clocks.h | 2 +- .../GeneratedSource/cycfg_notices.h | 2 +- .../GeneratedSource/cycfg_peripherals.c | 4 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.c | 66 +- .../GeneratedSource/cycfg_pins.h | 34 +- .../GeneratedSource/cycfg_qspi_memslot.c | 3 +- .../GeneratedSource/cycfg_qspi_memslot.h | 3 +- .../GeneratedSource/cycfg_routing.c | 2 +- .../GeneratedSource/cycfg_routing.h | 8 +- .../GeneratedSource/cycfg_system.c | 83 +- .../GeneratedSource/cycfg_system.h | 2 +- .../GeneratedSource/qspi_config.cfg | 1 - .../design.cycapsense | 17 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../TARGET_CY8CPROTO_062_4343W/cybsp.c | 16 +- .../TARGET_CY8CPROTO_062_4343W/cybsp.h | 7 +- .../TARGET_CY8CPROTO_062_4343W/cybsp_types.h | 81 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg.timestamp | 2 +- .../GeneratedSource/cycfg_notices.h | 2 +- .../GeneratedSource/cycfg_pins.c | 30 +- .../GeneratedSource/cycfg_pins.h | 16 +- .../GeneratedSource/cycfg_qspi_memslot.c | 3 +- .../GeneratedSource/cycfg_qspi_memslot.h | 3 +- .../GeneratedSource/cycfg_routing.c | 2 +- .../GeneratedSource/cycfg_routing.h | 2 +- .../GeneratedSource/cycfg_system.c | 81 +- .../GeneratedSource/cycfg_system.h | 2 +- .../GeneratedSource/qspi_config.cfg | 1 - .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../TARGET_CY8CPROTO_064_SB/cybsp.c | 16 +- .../TARGET_CY8CPROTO_064_SB/cybsp.h | 7 +- .../TARGET_CY8CPROTO_064_SB/cybsp_types.h | 59 +- .../TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cyb06xx7_cm4.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld | 4 +- .../TOOLCHAIN_IAR/cyb06xx7_cm4.icf | 10 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg.timestamp | 2 +- .../GeneratedSource/cycfg_clocks.c | 4 +- .../GeneratedSource/cycfg_clocks.h | 2 +- .../GeneratedSource/cycfg_notices.h | 2 +- .../GeneratedSource/cycfg_peripherals.c | 4 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.c | 62 +- .../GeneratedSource/cycfg_pins.h | 32 +- .../GeneratedSource/cycfg_qspi_memslot.c | 48 +- .../GeneratedSource/cycfg_qspi_memslot.h | 22 +- .../GeneratedSource/cycfg_routing.c | 2 +- .../GeneratedSource/cycfg_routing.h | 14 +- .../GeneratedSource/cycfg_system.c | 81 +- .../GeneratedSource/cycfg_system.h | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 4 +- .../SDIO_HOST/SDIO_HOST.c | 1509 ----------------- .../SDIO_HOST/SDIO_HOST.h | 396 ----- .../SDIO_HOST/SDIO_HOST_cfg.c | 1037 ----------- .../SDIO_HOST/SDIO_HOST_cfg.h | 869 ---------- .../TARGET_CYW9P62S1_43012EVB_01/cybsp.c | 16 +- .../TARGET_CYW9P62S1_43012EVB_01/cybsp.h | 7 +- .../cybsp_types.h | 153 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- .../GeneratedSource/cycfg.c | 4 +- .../GeneratedSource/cycfg.h | 4 +- .../GeneratedSource/cycfg.timestamp | 4 +- .../GeneratedSource/cycfg_clocks.c | 6 +- .../GeneratedSource/cycfg_clocks.h | 4 +- .../GeneratedSource/cycfg_notices.h | 4 +- .../GeneratedSource/cycfg_peripherals.c | 6 +- .../GeneratedSource/cycfg_peripherals.h | 4 +- .../GeneratedSource/cycfg_pins.c | 68 +- .../GeneratedSource/cycfg_pins.h | 36 +- .../GeneratedSource/cycfg_qspi_memslot.c | 2 +- .../GeneratedSource/cycfg_qspi_memslot.h | 2 +- .../GeneratedSource/cycfg_routing.c | 4 +- .../GeneratedSource/cycfg_routing.h | 10 +- .../GeneratedSource/cycfg_system.c | 83 +- .../GeneratedSource/cycfg_system.h | 4 +- .../design.cycapsense | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 27 - .../SDIO_HOST/SDIO_HOST.c | 1509 ----------------- .../SDIO_HOST/SDIO_HOST.h | 396 ----- .../SDIO_HOST/SDIO_HOST_cfg.c | 1056 ------------ .../SDIO_HOST/SDIO_HOST_cfg.h | 931 ---------- .../TARGET_CYW9P62S1_43438EVB_01/cybsp.c | 16 +- .../TARGET_CYW9P62S1_43438EVB_01/cybsp.h | 7 +- .../cybsp_types.h | 197 ++- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 4 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld | 4 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 12 +- .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 4 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 7 +- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 8 +- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 16 +- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 4 +- .../device/system_psoc6.h | 172 +- targets/targets.json | 9 +- 290 files changed, 3683 insertions(+), 14013 deletions(-) mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index ed8102601f..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 55f9bd74fa..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 46ae60d212..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 163bb04199..187aa9fd2d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 5b816c8b6a..1b0d5a4229 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 682af2fcd3..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 4f7cad51ee..a5c7a71428 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 528b81acee..a840124e95 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 5ea5df83bd..47ec41cdba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_RX_obj = + const cyhal_resource_inst_t CYBSP_CSD_RX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_RX_PORT_NUM, .channel_num = CYBSP_CSD_RX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index ace7a770b0..d9240fabfb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -417,7 +417,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 14d433859d..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 0ee62b1d55..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index 56e95d20c8..f8200c70ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index c8dc287b4b..7076bbba88 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -40,16 +40,16 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index b89e131d05..3e3476b25a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -69,7 +69,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -83,7 +83,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -91,7 +91,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -99,14 +99,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 36, .referenceDiv = 1, @@ -114,7 +114,7 @@ static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = .lfMode = false, .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, }; -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -247,14 +247,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -285,7 +285,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -296,59 +296,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -358,7 +358,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -405,21 +405,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -466,7 +466,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -513,48 +513,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 0e1b2e9945..744f2a111d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 5557ddecdd..909b041e9f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,4 +1,3 @@ set SMIF_BANKS { 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} } - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 6080a67de6..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,5 +1,5 @@ - + @@ -114,12 +114,12 @@ + - @@ -216,12 +216,12 @@ + - @@ -318,12 +318,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 6df618b3a8..58e8231d08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus index e714f2a614..bcf9df6f1a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -468,7 +468,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h index dac724d76e..ea350f531b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,28 +101,50 @@ extern "C" { */ /** LED 8; User LED1 (orange) */ +#ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) +#endif /** LED 9; User LED2 (red) */ +#ifndef CYBSP_LED9 #define CYBSP_LED9 (P11_1) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_LED_RGB_RED #define CYBSP_LED_RGB_RED (P1_1) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_LED_RGB_GREEN #define CYBSP_LED_RGB_GREEN (P0_5) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_LED_RGB_BLUE #define CYBSP_LED_RGB_BLUE (P7_3) +#endif /** LED 8; User LED1 (orange) */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) +#endif /** LED 9; User LED2 (red) */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_USER_LED3 #define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_USER_LED4 #define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_USER_LED5 #define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +#endif /** LED 8; User LED1 (orange) */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -122,16 +155,26 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 4; User Button 2 */ +#ifndef CYBSP_SW4 #define CYBSP_SW4 (P1_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 4; User Button 2 */ +#ifndef CYBSP_USER_BTN2 #define CYBSP_USER_BTN2 (CYBSP_SW4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -142,71 +185,131 @@ extern "C" { */ /** Pin: WIFI SDIO D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif /** Pin: WIFI SDIO D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif /** Pin: WIFI SDIO D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif /** Pin: WIFI SDIO D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif /** Pin: WIFI SDIO CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif /** Pin: WIFI SDIO CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif /** Pin: WIFI ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif /** Pin: WIFI Host Wakeup */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P4_1) +#endif /** Pin: BT UART RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P3_0) +#endif /** Pin: BT UART TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P3_1) +#endif /** Pin: BT UART RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P3_2) +#endif /** Pin: BT UART CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P3_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P3_4) +#endif /** Pin: BT Host Wakeup */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P4_0) +#endif /** Pin: BT Device Wakeup */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P3_5) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RTS #define CYBSP_DEBUG_UART_RTS (P5_2) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_CTS #define CYBSP_DEBUG_UART_CTS (P5_3) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) @@ -214,13 +317,21 @@ extern "C" { #define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P12_0) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P12_1) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P12_2) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P12_4) +#endif /** \} group_bsp_pins_comm */ @@ -231,49 +342,93 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#ifndef CYBSP_A0 +#define CYBSP_A0 (P10_0) +#endif /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#ifndef CYBSP_A1 +#define CYBSP_A1 (P10_1) +#endif /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#ifndef CYBSP_A2 +#define CYBSP_A2 (P10_2) +#endif /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#ifndef CYBSP_A3 +#define CYBSP_A3 (P10_3) +#endif /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#ifndef CYBSP_A4 +#define CYBSP_A4 (P10_4) +#endif /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#ifndef CYBSP_A5 +#define CYBSP_A5 (P10_5) +#endif /** Arduino D0 */ +#ifndef CYBSP_D0 #define CYBSP_D0 (P5_0) +#endif /** Arduino D1 */ +#ifndef CYBSP_D1 #define CYBSP_D1 (P5_1) +#endif /** Arduino D2 */ +#ifndef CYBSP_D2 #define CYBSP_D2 (P5_2) +#endif /** Arduino D3 */ +#ifndef CYBSP_D3 #define CYBSP_D3 (P5_3) +#endif /** Arduino D4 */ +#ifndef CYBSP_D4 #define CYBSP_D4 (P5_4) +#endif /** Arduino D5 */ +#ifndef CYBSP_D5 #define CYBSP_D5 (P5_5) +#endif /** Arduino D6 */ +#ifndef CYBSP_D6 #define CYBSP_D6 (P5_6) +#endif /** Arduino D7 */ +#ifndef CYBSP_D7 #define CYBSP_D7 (P5_7) +#endif /** Arduino D8 */ +#ifndef CYBSP_D8 #define CYBSP_D8 (P7_5) +#endif /** Arduino D9 */ +#ifndef CYBSP_D9 #define CYBSP_D9 (P7_6) +#endif /** Arduino D10 */ +#ifndef CYBSP_D10 #define CYBSP_D10 (P12_3) +#endif /** Arduino D11 */ +#ifndef CYBSP_D11 #define CYBSP_D11 (P12_0) +#endif /** Arduino D12 */ +#ifndef CYBSP_D12 #define CYBSP_D12 (P12_1) +#endif /** Arduino D13 */ +#ifndef CYBSP_D13 #define CYBSP_D13 (P12_2) +#endif /** Arduino D14 */ +#ifndef CYBSP_D14 #define CYBSP_D14 (P6_1) +#endif /** Arduino D15 */ +#ifndef CYBSP_D15 #define CYBSP_D15 (P6_0) +#endif /** \} group_bsp_pins_arduino */ @@ -284,37 +439,69 @@ extern "C" { */ /** Cypress J2 Header pin 1 */ +#ifndef CYBSP_J2_1 #define CYBSP_J2_1 (CYBSP_A0) +#endif /** Cypress J2 Header pin 2 */ +#ifndef CYBSP_J2_2 #define CYBSP_J2_2 (P9_0) +#endif /** Cypress J2 Header pin 3 */ +#ifndef CYBSP_J2_3 #define CYBSP_J2_3 (CYBSP_A1) +#endif /** Cypress J2 Header pin 4 */ +#ifndef CYBSP_J2_4 #define CYBSP_J2_4 (P9_1) +#endif /** Cypress J2 Header pin 5 */ +#ifndef CYBSP_J2_5 #define CYBSP_J2_5 (CYBSP_A2) +#endif /** Cypress J2 Header pin 6 */ +#ifndef CYBSP_J2_6 #define CYBSP_J2_6 (P9_2) +#endif /** Cypress J2 Header pin 7 */ +#ifndef CYBSP_J2_7 #define CYBSP_J2_7 (CYBSP_A3) +#endif /** Cypress J2 Header pin 8 */ +#ifndef CYBSP_J2_8 #define CYBSP_J2_8 (P9_3) +#endif /** Cypress J2 Header pin 9 */ +#ifndef CYBSP_J2_9 #define CYBSP_J2_9 (CYBSP_A4) +#endif /** Cypress J2 Header pin 10 */ +#ifndef CYBSP_J2_10 #define CYBSP_J2_10 (P9_4) +#endif /** Cypress J2 Header pin 11 */ +#ifndef CYBSP_J2_11 #define CYBSP_J2_11 (CYBSP_A5) +#endif /** Cypress J2 Header pin 12 */ +#ifndef CYBSP_J2_12 #define CYBSP_J2_12 (P9_5) +#endif /** Cypress J2 Header pin 13 */ +#ifndef CYBSP_J2_13 #define CYBSP_J2_13 (P10_6) +#endif /** Cypress J2 Header pin 14 */ +#ifndef CYBSP_J2_14 #define CYBSP_J2_14 (P9_6) +#endif /** Cypress J2 Header pin 15 */ +#ifndef CYBSP_J2_15 #define CYBSP_J2_15 (P10_7) +#endif /** Cypress J2 Header pin 16 */ +#ifndef CYBSP_J2_16 #define CYBSP_J2_16 (P9_7) +#endif /** \} group_bsp_pins_j2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index f5a99814fe..11f1574b41 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index e6ab9018bf..4556c88ec4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index fea3f6ee6f..f99cad47c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 620923dcae..74bb3c8cbd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index ffbeca9b8e..72e55e3d19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 3080c25daa..dfb3fe373f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * * @@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index ed8102601f..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 55f9bd74fa..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 46ae60d212..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index da3188e129..23a452aeb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 5b816c8b6a..1b0d5a4229 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 682af2fcd3..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 38c3af3a06..d24d12c7df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,14 +27,14 @@ #include "cycfg_peripherals.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BLE_obj = + const cyhal_resource_inst_t CYBSP_BLE_obj = { .type = CYHAL_RSC_BLESS, .block_num = 0U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 3fa88f65c9..e829204555 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 9d396e04a2..ccaccdf0ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_TX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_TX_PORT_NUM, .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 249d1ffc72..a54e4c7ad8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -417,7 +417,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index c4e5bcf916..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,7 +25,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -42,7 +43,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +61,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,7 +79,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xDCU, @@ -96,7 +97,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,7 +115,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x34U, @@ -132,7 +133,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +151,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +169,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,34 +187,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ .memSize = 0x04000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x00040000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x00000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -226,7 +227,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = .programTime = 1300U }; -const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -244,11 +245,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512SX4byteaddr_SlaveSlot_0 + &S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 32f9b49b2e..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,19 +29,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index cb52455ed5..fdc143f8c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index c8dc287b4b..02dd496f81 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -40,16 +40,16 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index a5c53fda56..0aaf0cf2a5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -72,7 +72,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -86,7 +86,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -94,7 +94,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -102,7 +102,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -110,7 +110,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -118,14 +118,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -255,14 +255,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -293,7 +293,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -304,59 +304,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -366,7 +366,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -413,21 +413,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -474,7 +474,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -521,48 +521,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 661d759fef..5cdc4baf8e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 5557ddecdd..909b041e9f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,4 +1,3 @@ set SMIF_BANKS { 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} } - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 43d6108110..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,13 +1,6 @@ - - + + @@ -121,12 +114,12 @@ + - @@ -223,12 +216,12 @@ + - @@ -325,12 +318,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 3c5fbe94fb..f6145a495b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus index 56bf3caafe..9d53f0c44b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -82,12 +82,6 @@ - - - - - - @@ -101,8 +95,6 @@ - - @@ -280,9 +272,6 @@ - - - @@ -405,7 +394,6 @@ - @@ -423,7 +411,6 @@ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h index 0037390d26..afbd1c3455 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,26 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,28 +105,50 @@ extern "C" { */ /** LED 8; User LED1 */ +#ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_LED9 #define CYBSP_LED9 (P13_7) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_LED_RGB_RED #define CYBSP_LED_RGB_RED (P0_3) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_LED_RGB_GREEN #define CYBSP_LED_RGB_GREEN (P1_1) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_LED_RGB_BLUE #define CYBSP_LED_RGB_BLUE (P11_1) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_USER_LED3 #define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_USER_LED4 #define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_USER_LED5 #define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -121,12 +158,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -137,43 +180,77 @@ extern "C" { */ /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P12_0) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P12_1) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P12_2) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P12_4) +#endif /** \} group_bsp_pins_comm */ @@ -184,49 +261,93 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#ifndef CYBSP_A0 +#define CYBSP_A0 (P10_0) +#endif /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#ifndef CYBSP_A1 +#define CYBSP_A1 (P10_1) +#endif /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#ifndef CYBSP_A2 +#define CYBSP_A2 (P10_2) +#endif /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#ifndef CYBSP_A3 +#define CYBSP_A3 (P10_3) +#endif /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#ifndef CYBSP_A4 +#define CYBSP_A4 (P10_4) +#endif /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#ifndef CYBSP_A5 +#define CYBSP_A5 (P10_5) +#endif /** Arduino D0 */ +#ifndef CYBSP_D0 #define CYBSP_D0 (P5_0) +#endif /** Arduino D1 */ +#ifndef CYBSP_D1 #define CYBSP_D1 (P5_1) +#endif /** Arduino D2 */ +#ifndef CYBSP_D2 #define CYBSP_D2 (P5_2) +#endif /** Arduino D3 */ +#ifndef CYBSP_D3 #define CYBSP_D3 (P5_3) +#endif /** Arduino D4 */ +#ifndef CYBSP_D4 #define CYBSP_D4 (P5_4) +#endif /** Arduino D5 */ +#ifndef CYBSP_D5 #define CYBSP_D5 (P5_5) +#endif /** Arduino D6 */ +#ifndef CYBSP_D6 #define CYBSP_D6 (P5_6) +#endif /** Arduino D7 */ +#ifndef CYBSP_D7 #define CYBSP_D7 (P0_2) +#endif /** Arduino D8 */ +#ifndef CYBSP_D8 #define CYBSP_D8 (P13_0) +#endif /** Arduino D9 */ +#ifndef CYBSP_D9 #define CYBSP_D9 (P13_1) +#endif /** Arduino D10 */ +#ifndef CYBSP_D10 #define CYBSP_D10 (P12_3) +#endif /** Arduino D11 */ +#ifndef CYBSP_D11 #define CYBSP_D11 (P12_0) +#endif /** Arduino D12 */ +#ifndef CYBSP_D12 #define CYBSP_D12 (P12_1) +#endif /** Arduino D13 */ +#ifndef CYBSP_D13 #define CYBSP_D13 (P12_2) +#endif /** Arduino D14 */ +#ifndef CYBSP_D14 #define CYBSP_D14 (P6_1) +#endif /** Arduino D15 */ +#ifndef CYBSP_D15 #define CYBSP_D15 (P6_0) +#endif /** \} group_bsp_pins_arduino */ @@ -237,45 +358,85 @@ extern "C" { */ /** Cypress J2 Header pin 1 */ +#ifndef CYBSP_J2_1 #define CYBSP_J2_1 (CYBSP_A0) +#endif /** Cypress J2 Header pin 2 */ +#ifndef CYBSP_J2_2 #define CYBSP_J2_2 (P9_0) +#endif /** Cypress J2 Header pin 3 */ +#ifndef CYBSP_J2_3 #define CYBSP_J2_3 (CYBSP_A1) +#endif /** Cypress J2 Header pin 4 */ +#ifndef CYBSP_J2_4 #define CYBSP_J2_4 (P9_1) +#endif /** Cypress J2 Header pin 5 */ +#ifndef CYBSP_J2_5 #define CYBSP_J2_5 (CYBSP_A2) +#endif /** Cypress J2 Header pin 6 */ +#ifndef CYBSP_J2_6 #define CYBSP_J2_6 (P9_2) +#endif /** Cypress J2 Header pin 7 */ +#ifndef CYBSP_J2_7 #define CYBSP_J2_7 (CYBSP_A3) +#endif /** Cypress J2 Header pin 8 */ +#ifndef CYBSP_J2_8 #define CYBSP_J2_8 (P9_3) +#endif /** Cypress J2 Header pin 9 */ +#ifndef CYBSP_J2_9 #define CYBSP_J2_9 (CYBSP_A4) +#endif /** Cypress J2 Header pin 10 */ +#ifndef CYBSP_J2_10 #define CYBSP_J2_10 (P9_4) +#endif /** Cypress J2 Header pin 11 */ +#ifndef CYBSP_J2_11 #define CYBSP_J2_11 (CYBSP_A5) +#endif /** Cypress J2 Header pin 12 */ +#ifndef CYBSP_J2_12 #define CYBSP_J2_12 (P9_5) +#endif /** Cypress J2 Header pin 13 */ +#ifndef CYBSP_J2_13 #define CYBSP_J2_13 (P10_6) +#endif /** Cypress J2 Header pin 14 */ +#ifndef CYBSP_J2_14 #define CYBSP_J2_14 (NC) +#endif /** Cypress J2 Header pin 15 */ +#ifndef CYBSP_J2_15 #define CYBSP_J2_15 (P6_2) +#endif /** Cypress J2 Header pin 16 */ +#ifndef CYBSP_J2_16 #define CYBSP_J2_16 (P9_6) +#endif /** Cypress J2 Header pin 17 */ +#ifndef CYBSP_J2_17 #define CYBSP_J2_17 (P6_3) +#endif /** Cypress J2 Header pin 18 */ +#ifndef CYBSP_J2_18 #define CYBSP_J2_18 (P9_7) +#endif /** Cypress J2 Header pin 19 */ +#ifndef CYBSP_J2_19 #define CYBSP_J2_19 (P13_6) +#endif /** Cypress J2 Header pin 20 */ +#ifndef CYBSP_J2_20 #define CYBSP_J2_20 (P13_7) +#endif /** \} group_bsp_pins_j2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 4ff5ccb454..7a99d7b707 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index a9d28573c6..b78effb0c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3a0414efa3..61d4a4b17b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 0f7f5fe0df..e9a6874e34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 9be3c4aa3b..f0a3d746f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index b405a8b603..51808a1db4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index ed8102601f..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 55f9bd74fa..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 46ae60d212..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 45223d1950..41fe86f553 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 9512e17264..1bbe7b6308 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 682af2fcd3..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 181ef57d60..de38a7a37c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 8d437beab5..41388b9638 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 9d396e04a2..ccaccdf0ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_TX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_TX_PORT_NUM, .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 249d1ffc72..a54e4c7ad8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -417,7 +417,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 14d433859d..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 0ee62b1d55..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index cb52455ed5..fdc143f8c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index dd809d1506..6960498f6d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -40,16 +40,16 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index a5c53fda56..0aaf0cf2a5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -72,7 +72,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -86,7 +86,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -94,7 +94,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -102,7 +102,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -110,7 +110,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -118,14 +118,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -255,14 +255,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -293,7 +293,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -304,59 +304,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -366,7 +366,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -413,21 +413,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -474,7 +474,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -521,48 +521,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index c5b90ec621..52974c5044 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 5557ddecdd..909b041e9f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,4 +1,3 @@ set SMIF_BANKS { 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} } - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 13cf564a5a..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,13 +1,6 @@ - - + + @@ -121,12 +114,12 @@ + - @@ -223,12 +216,12 @@ + - @@ -325,12 +318,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 3c5fbe94fb..f6145a495b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus index 4ef39eb793..67a54ac238 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -75,14 +75,6 @@ - - - - - - - - @@ -96,16 +88,6 @@ - - - - - - - - - - @@ -275,8 +257,6 @@ - - @@ -285,10 +265,6 @@ - - - - @@ -411,7 +387,6 @@ - @@ -429,8 +404,6 @@ - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c deleted file mode 100644 index 4e48631123..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c +++ /dev/null @@ -1,1509 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST.c -* -* \brief -* This file provides the source code to the API for the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "SDIO_HOST.h" -#include "cy_utils.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#ifdef CY_RTOS_AWARE - - #include "cyabs_rtos.h" - - #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) - static cy_semaphore_t sdio_transfer_finished_semaphore; - static bool sema_initialized = false; -#endif - -/* Backup struct used to store and restore non retention UDB registers */ -typedef struct -{ - uint32_t CY_SDIO_UDB_WRKMULT_CTL_0; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_1; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_2; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_3; -} stc_sdio_backup_regs_t; - -/*Globals Needed for DMA */ -/*DMA channel structures*/ -cy_stc_dma_channel_config_t respChannelConfig; -cy_stc_dma_channel_config_t cmdChannelConfig; -cy_stc_dma_channel_config_t writeChannelConfig; -cy_stc_dma_channel_config_t readChannelConfig; - -/*DMA Descriptor structures*/ -cy_stc_dma_descriptor_t respDesr; -cy_stc_dma_descriptor_t cmdDesr; -cy_stc_dma_descriptor_t readDesr0; -cy_stc_dma_descriptor_t readDesr1; -cy_stc_dma_descriptor_t writeDesr0; -cy_stc_dma_descriptor_t writeDesr1; - -/*Global structure used for data keeping*/ -stc_sdio_gInternalData_t gstcInternalData; - -/*Global CRC table*/ -static uint8_t crcTable[256]; - -/*Global values used for DMA interrupt*/ -static uint32_t yCountRemainder; -static uint32_t yCounts; - -/* Global value for card interrupt */ -static uint8_t pfnCardInt_count = 0; - -/*Global structure to store UDB registers */ -static stc_sdio_backup_regs_t regs; - -static uint32_t udb_initialized = 0; - -cy_stc_syspm_callback_params_t sdio_pm_callback_params; -cy_stc_syspm_callback_t sdio_pm_callback_handler; - -/* Deep Sleep Mode API Support */ -static void SDIO_SaveConfig(void); -static void SDIO_RestoreConfig(void); - -/******************************************************************************* -* Function Name: SDIO_DeepSleepCallback -****************************************************************************//** -* -* Callback executed during Deep Sleep entry/exit -* -* \param params -* Pointer to structure that holds callback parameters for this driver. -* -* \param mode -* The state transition mode that is currently happening. -* -* \note -* Saves/Restores SDIO UDB registers -* -* \return -* CY_SYSPM_SUCCESS if the transition was successful, otherwise CY_SYSPM_FAIL -* -*******************************************************************************/ -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) -{ - CY_UNUSED_PARAMETER(params); - cy_en_syspm_status_t status = CY_SYSPM_FAIL; - - switch (mode) - { - case CY_SYSPM_CHECK_READY: - case CY_SYSPM_CHECK_FAIL: - status = CY_SYSPM_SUCCESS; - break; - - case CY_SYSPM_BEFORE_TRANSITION: - SDIO_SaveConfig(); - status = CY_SYSPM_SUCCESS; - break; - - case CY_SYSPM_AFTER_TRANSITION: - SDIO_RestoreConfig(); - status = CY_SYSPM_SUCCESS; - break; - - default: - break; - } - - return status; -} - -/******************************************************************************* -* Function Name: SDIO_Init -****************************************************************************//** -* -* Initializes the SDIO hardware -* -* \param pfuCb -* Pointer to structure that holds pointers to callback function -* see \ref stc_sdio_irq_cb_t. -* -* \note -* Sets SD Clock Frequency to 400 kHz -*******************************************************************************/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) -{ - if ( !udb_initialized ) - { - udb_initialized = 1; - SDIO_Host_Config_TriggerMuxes(); - SDIO_Host_Config_UDBs(); - } - - /*Set Number of Blocks to 1 initially, this will be updated later*/ - SDIO_SetNumBlocks(1); - - /*Enable SDIO ISR*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - - /*Enable the Status Reg to generate an interrupt*/ - SDIO_STATUS_AUX_CTL |= (0x10); - - /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ - /*First clear priority of all*/ - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; - - /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; - - /*Setup callback for card interrupt*/ - gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; - - /*Setup the DMA channels*/ - SDIO_SetupDMA(); - - /*Initialize CRC*/ - SDIO_Crc7Init(); - - /*Enable all the bit counters*/ - SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - - /*Set block byte count to 64, this will be changed later */ - SDIO_SetBlockSize(64); - - /*Set the read and write FIFOs to use the half full status*/ - (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; - (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; - - /*Set clock to 400k, and enable it*/ - SDIO_SetSdClkFrequency(400000); - SDIO_EnableIntClock(); - SDIO_EnableSdClk(); -} - - -/******************************************************************************* -* Function Name: SDIO_SendCommand -****************************************************************************//** -* -* Send an SDIO command, don't wait for it to finish. -* -* \param pstcCmdConfig -* Command configuration structure. See \ref stc_sdio_cmd_config_t. -* -*******************************************************************************/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) -{ - /*buffer to hold command data*/ - static uint8_t u8cmdBuf[6]; - - /*Populate buffer*/ - /*Element 0 is the Most Significant Byte*/ - u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; - u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); - u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); - u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); - u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); - - /*calculate the CRC of above data*/ - u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); - /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ - u8cmdBuf[5] = u8cmdBuf[5] << 1; - /*Add on the end bit*/ - u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; - - /*Load the first byte into A0*/ - SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; - - /*If a response is expected setup DMA to receive the response*/ - if (pstcCmdConfig->bResponseRequired == true) - { - /*Clear the flag in hardware that says skip response*/ - SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; - - /*Set the destination address*/ - respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); - - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); - } - else - { - /*Set the skip flag*/ - SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; - } - - /*Setup the Command DMA*/ - /*Set the source address*/ - cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); - - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); -} - - -/******************************************************************************* -* Function Name: SDIO_GetResponse -****************************************************************************//** -* -* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks -* for index errors, CRC errors, and end bit errors. -* -* \param bCmdIndexCheck -* If True check for index errors -* -* \param bCmdCrcCheck -* If True check for CRC errors -* -* \param u8cmdIdx -* Command index, used for checking the index error -* -* \param pu32Response -* location to store 32 bit response -* -* \param pu8ResponseBuf -* buffer that holds the 6 bytes of response data -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) -{ - /*Function return*/ - en_sdio_result_t enRet = Error; - /*variable to hold temporary CRC*/ - uint8_t u8TmpCrc; - /*temporary response*/ - uint32_t u32TmpResponse; - - /*Zero out the pu32Response*/ - *pu32Response = 0; - - /*Check if the CRC needs to be checked*/ - if (bCmdCrcCheck) - { - /*Calculate the CRC*/ - u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); - - /*Shift calculated CRC up by one bit to match bit position of CRC*/ - u8TmpCrc = u8TmpCrc << 1; - - /*Compare calculated CRC with received CRC*/ - if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) - { - enRet |= CommandCrcError; - } - } - - /*Check if the index needs to be checked*/ - if (bCmdIndexCheck) - { - /*The index resides in the lower 6 bits of the 1st byte of the response*/ - if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) - { - enRet |= CommandIdxError; - } - } - - /*Check the end bit*/ - if (!(pu8ResponseBuf[5] & 0x01)) - { - enRet |= CommandEndError; - } - - if (enRet == Error) - { - /*If we get here then there were no errors with the command populate the response*/ - u32TmpResponse = pu8ResponseBuf[1]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[2]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[3]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[4]; - - *pu32Response = u32TmpResponse; - - enRet = Ok; - } - - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_InitDataTransfer -****************************************************************************//** -* -* Configure the data channel for a data transfer. For a write this doesn't start -* the write, that must be done separately after the response is received. -* -* \param pstcDataConfig -* Data configuration structure. See \ref stc_sdio_data_config_t -* -* -*******************************************************************************/ -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) -{ - /*hold size of entire transfer*/ - uint32_t dataSize; - - /*calculate how many bytes are going to be sent*/ - dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; - - /*Set the block size and number of blocks*/ - SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); - SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); - - /*If we are reading data setup the DMA to receive read data*/ - if (pstcDataConfig->bRead == true) - { - /*First disable the write channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - - /*Clear any pending interrupts in the DMA*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - - /*setup the destination addresses*/ - readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); - readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ - readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - - /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the - DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility - that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA - will be SW triggered when hardware indicates all bytes have been received. - This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to - be at least 3 bytes bigger than the data size. - - Since the X loop is setup to 4, the maximum number of Y loop is 256 so one - descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. - Since we don't know the maximum number of bytes to read only two descriptors will - be used. If more than 2048 bytes need to be read then and interrupt will be enabled - The descriptor that is not currently running will be updated in the ISR to receive - more data. - - So there are three conditions to check: - 1) Are we sending less than or equal to 1024 bytes if so use one descriptor - 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors - 3) Greater than 2048, use two descriptors and the ISR - */ - - if (dataSize <= 1024) - { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - /*Setup descriptor 0 to point to nothing and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (dataSize <=2048) - { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ - - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - - /*Setup descriptor 0 to point to descriptor 1*/ - readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to nothing and disable */ - readDesr1.nextPtr = 0; - - /*Don't disable after first descriptor*/ - readDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ - readDesr1.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else /*dataSize must be greater than 2048*/ - { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ - yCounts = (dataSize / 1024); - - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); - - /*Setup the Y Ctrl for both descriptors*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - /*Setup descriptor 0 to point to descriptor 1*/ - readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ - readDesr1.nextPtr = (uint32_t)(&readDesr0); - - /*Don't disable the channel on completion of descriptor*/ - readDesr0.ctl &= ~0x01000000; - readDesr1.ctl &= ~0x01000000; - - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ - yCounts -= 2; - - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the read*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; - } - - /*Otherwise it is a write*/ - else - { - /*First disable the Read channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Clear any pending interrupts in the DMA*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - - /*setup the SRC addresses*/ - writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); - writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - - - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ - writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); - writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); - - if (dataSize <= 1024) - { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - /*Setup descriptor 0 to point to nothing and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else if (dataSize <=2048) - { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ - - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - - /*Setup descriptor 0 to point to descriptor 1*/ - writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to nothing and disable */ - writeDesr1.nextPtr = 0; - - /*Don't disable after first descriptor*/ - writeDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ - writeDesr1.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else /*dataSize must be greater than 2048*/ - { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ - yCounts = (dataSize / 1024); - - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); - - /*Setup the Y Ctrl for both descriptors*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - /*Setup descriptor 0 to point to descriptor 1*/ - writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ - writeDesr1.nextPtr = (uint32_t)(&writeDesr0); - - /*Don't disable the channel on completion of descriptor*/ - writeDesr0.ctl &= ~0x01000000; - writeDesr1.ctl &= ~0x01000000; - - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ - yCounts -= 2; - - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); - } -} - - -/******************************************************************************* -* Function Name: SDIO_SendCommandAndWait -****************************************************************************//** -* -* This function sends a command on the command channel and waits for that -* command to finish before returning. If a Command 53 is issued this function -* will handle all of the data transfer and wait to return until it is done. -* -* \param pstcCmd -* Pointer command configuration structure see \ref stc_sdio_cmd_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) -{ - /* Store the command and data configurations*/ - stc_sdio_cmd_config_t stcCmdConfig; - stc_sdio_data_config_t stcDataConfig; - - uint32_t u32CmdTimeout = 0; - - /*Returns from various function calls*/ - en_sdio_result_t enRet = Error; - en_sdio_result_t enRetTmp = Ok; - - /* Hold value of if these checks are needed */ - uint8_t bCmdIndexCheck; - uint8_t bCmdCrcCheck; - static uint8_t u8responseBuf[6]; - - /* Clear statuses */ - gstcInternalData.stcEvents.u8CmdComplete = 0; - gstcInternalData.stcEvents.u8TransComplete = 0; - gstcInternalData.stcEvents.u8CRCError = 0; - - /* Setup the command configuration */ - stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; - stcCmdConfig.u32Argument = pstcCmd->u32Arg; - -#ifdef CY_RTOS_AWARE - - cy_rslt_t result; - - /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in - * interrupt thread. - */ - if(!sema_initialized) - { - cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 ); - sema_initialized = true; - } -#else - - /* Variable used for holding timeout value */ - uint32_t u32Timeout = 0; -#endif - - /*Determine the type of response and if we need to do any checks*/ - /*Command 0 and 8 have no response, so don't wait for one*/ - if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) - { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = false; - stcCmdConfig.pu8ResponseBuf = NULL; - } - - /*Command 5's response doesn't have a CRC or index, so don't check*/ - else if (pstcCmd->u32CmdIdx == 5) - { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; - } - /*Otherwise check everything*/ - else - { - bCmdIndexCheck = true; - bCmdCrcCheck = true; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; - } - - /*Check if the command is 53, if it is then setup the data transfer*/ - if (pstcCmd->u32CmdIdx == 53) - { - /*Set the number of blocks in the global struct*/ - stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; - /*Set the size of the data transfer*/ - stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; - /*Set the direction are we reading or writing*/ - stcDataConfig.bRead = pstcCmd->bRead; - /*Set the pointer for the data*/ - stcDataConfig.pu8Data = pstcCmd->pu8Data; - - /*Get the data Transfer Ready*/ - SDIO_InitDataTransfer(&stcDataConfig); - - /*Set bit saying this was a CMD_53*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; - } - - /*Send the command*/ - SDIO_SendCommand(&stcCmdConfig); - - /*Wait for the command to finish*/ - do - { - u32CmdTimeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); - - } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); - - - if (u32CmdTimeout == SDIO_CMD_TIMEOUT) - { - enRet |= CMDTimeout; - } - else /*CMD Passed*/ - { - /*If a response is expected check it*/ - if (stcCmdConfig.bResponseRequired == true) - { - enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); - if (enRetTmp != Ok) - { - enRet |= enRetTmp; - } - else /*Response good*/ - { - /*if it was command 53, check the response to ensure there was no error*/ - if ((pstcCmd->u32CmdIdx) == 53) - { - /*Make sure none of the error bits are set*/ - if (*(pstcCmd->pu32Response) & 0x0000cf00) - { - enRet |= ResponseFlagError; - } - else /*CMD53 Response good*/ - { - /*If it was command 53 and it was a write enable the write*/ - if (pstcCmd->bRead == false && enRet == Error) - { - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the write*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - /*Enable the channel*/ - Cy_SysLib_DelayCycles(35); - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; - } - - #ifdef CY_RTOS_AWARE - /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released - * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in - * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases - * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero - * and exit. Or timeout occurs - */ - result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); - - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - if (result != CY_RSLT_SUCCESS) - #else - /* Wait for the transfer to finish */ - do - { - u32Timeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); - - if (u32Timeout == SDIO_DAT_TIMEOUT) - #endif - { - enRet |= DataTimeout; - } - - /* if it was a read it is possible there is still extra data hanging out, trigger the - DMA again. This can result in extra data being transfered so the read buffer should be - 3 bytes bigger than needed*/ - if (pstcCmd->bRead == true) - { - Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); - } - - if (enRetTmp == DataCrcError) - { - enRet |= DataCrcError; - } - }/*CMD53 response good*/ - }/*Not a CMD53*/ - } /*Response Good*/ - } /*No Response Required, thus no CMD53*/ - } /*CMD Passed*/ - -#ifndef CY_RTOS_AWARE - u32Timeout = 0; -#endif - - /*If there were no errors then indicate transfer was okay*/ - if (enRet == Error) - { - enRet = Ok; - } - - /*reset CmdTimeout value*/ - u32CmdTimeout = 0; - - /*Always Reset on exit to clean up*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - /*No longer a CMD_53*/ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); - SDIO_Reset(); - - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_CheckForEvent -****************************************************************************//** -* -* Checks to see if a specific event has occurred such a command complete or -* transfer complete. -* -* \param enEventType -* The type of event to check for. See \ref en_sdio_event_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) -{ - en_sdio_result_t enRet = Error; - - /*Disable Interrupts while modifying the global*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - - /*Switch the event to check*/ - switch ( enEventType ) - { - /*If the command is done clear the flag*/ - case SdCmdEventCmdDone: - if (gstcInternalData.stcEvents.u8CmdComplete > 0) - { - gstcInternalData.stcEvents.u8CmdComplete = 0; - enRet = Ok; - } - break; - - /*If the transfer is done check for CRC Error and clear the flag*/ - case SdCmdEventTransferDone: - if (gstcInternalData.stcEvents.u8TransComplete > 0) - { - gstcInternalData.stcEvents.u8TransComplete = 0; - enRet = Ok; - } - /*Check for CRC error and set flags*/ - if (gstcInternalData.stcEvents.u8CRCError > 0) - { - enRet = DataCrcError; - gstcInternalData.stcEvents.u8CRCError = 0; - } - break; - } - - /*Re-enable Interrupts*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_CalculateCrc7 -****************************************************************************//** -* -* Calculate the 7 bit CRC for the command channel -* -* \param pu8Data -* Data to calculate CRC on -* -* \param u8Size -* Number of bytes to calculate CRC on -* -* \return -* CRC -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) -{ - uint8_t data; - uint8_t remainder = 0; - uint32_t byte; - - for(byte = 0; byte < u8Size; ++byte) - { - data = pu8Data[byte] ^ remainder; - remainder = crcTable[data] ^ (remainder << 8); - } - - return (remainder>>1); -} - - -/******************************************************************************* -* Function Name: SDIO_Crc7Init -****************************************************************************//** -* -* Initialize 7-bit CRC Table -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ -void SDIO_Crc7Init(void) -{ - uint8_t remainder; - uint8_t bit; - uint32_t dividend; - - for(dividend = 0; dividend < 256; ++dividend) - { - remainder = dividend; - - for(bit = 8; bit > 0; --bit) - { - if (remainder & SDIO_CRC_UPPER_BIT) - { - remainder = (remainder << 1) ^ SDIO_CRC7_POLY; - } - else - { - remainder = (remainder << 1); - } - } - - crcTable[dividend] = (remainder); - } -} - - -/******************************************************************************* -* Function Name: SDIO_SetBlockSize -****************************************************************************//** -* -* Sets the size of each block -* -* \param u8ByteCount -* Size of the block -* -*******************************************************************************/ -void SDIO_SetBlockSize(uint8_t u8ByteCount) -{ - SDIO_BYTE_COUNT_REG = u8ByteCount; -} - - -/******************************************************************************* -* Function Name: SDIO_SetNumBlocks -****************************************************************************//** -* -* Sets the number of blocks to send -* -* \param u8BlockCount -* Size of the block -* -*******************************************************************************/ -void SDIO_SetNumBlocks(uint8_t u8BlockCount) -{ - SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; - SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; - /*The one is used so that we can do 256 bytes*/ - SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; - SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; -} - - -/******************************************************************************* -* Function Name: SDIO_EnableIntClock -****************************************************************************//** -* -* Enable Internal clock for the block -* -*******************************************************************************/ -void SDIO_EnableIntClock(void) -{ - SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); -} - - -/******************************************************************************* -* Function Name: SDIO_DisableIntClock -****************************************************************************//** -* -* Enable Disable clock for the block -* -*******************************************************************************/ -void SDIO_DisableIntClock(void) -{ - SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); -} - - -/******************************************************************************* -* Function Name: SDIO_EnableSdClk -****************************************************************************//** -* -* Enable SD Clock out to pin -* -*******************************************************************************/ -void SDIO_EnableSdClk(void) -{ - SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; -} - - -/******************************************************************************* -* Function Name: SDIO_DisableSdClk -****************************************************************************//** -* -* Disable SD Clock out to the pin -* -*******************************************************************************/ -void SDIO_DisableSdClk(void) -{ - SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; -} - - -/******************************************************************************* -* Function Name: SDIO_SetSdClkFrequency -****************************************************************************//** -* -* Sets the frequency of the SD Clock -* -* \param u32SdClkFreqHz -* Frequency of SD Clock in Hz. -* -* \note -* Only an integer divider is used, so the desired frequency may not be meet -*******************************************************************************/ -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) -{ - uint16_t u16Div; - /* - * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB - * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required - * SDIO operating frequency. - */ - u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); - Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); -} - - -/******************************************************************************* -* Function Name: SDIO_SetupDMA -****************************************************************************//** -* -* Configures the DMA for the SDIO block -* -*******************************************************************************/ -void SDIO_SetupDMA(void) -{ - /*Set the number of bytes to send*/ - SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); - /*Set the destination address*/ - SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; - - /*Initialize descriptor for cmd channel*/ - Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); - - /*Set flag to disable descriptor when done*/ - cmdDesr.ctl |= 0x01000000; - - /*Configure channel*/ - /*CMD channel can be preempted, and has lower priority*/ - cmdChannelConfig.descriptor = &cmdDesr; - cmdChannelConfig.preemptable = 1; - cmdChannelConfig.priority = 1; - cmdChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); - - /*Set the number of bytes to receive*/ - SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; - /*Set the source address*/ - SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; - - /*Initialize descriptor for response channel*/ - Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); - - /*Set flag to disable descriptor when done*/ - respDesr.ctl |= 0x01000000; - - /*Configure channel*/ - /*response channel can be preempted, and has lower priority*/ - respChannelConfig.descriptor = &respDesr; - respChannelConfig.preemptable = 1; - respChannelConfig.priority = 1; - respChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); - - /*Set the destination address*/ - SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; - - /*Initialize descriptor for write channel*/ - Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - - /*Configure channel*/ - /*write channel cannot be preempted, and has highest priority*/ - writeChannelConfig.descriptor = &writeDesr0; - writeChannelConfig.preemptable = 0; - writeChannelConfig.priority = 0; - writeChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); - - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); - - /*Set the source address*/ - SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; - /*Initialize descriptor for read channel*/ - Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - - /*Configure channel*/ - /*read channel cannot be preempted, and has highest priority*/ - readChannelConfig.descriptor = &readDesr0; - readChannelConfig.preemptable = 0; - readChannelConfig.priority = 0; - readChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); - - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); -} - - -/******************************************************************************* -* Function Name: SDIO_Reset -****************************************************************************//** -* -* Reset the SDIO interface -* -*******************************************************************************/ -void SDIO_Reset(void) -{ - /*Control register is in pulse mode, so this just pulses the reset*/ - SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); -} - - -/******************************************************************************* -* Function Name: SDIO_EnableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ -void SDIO_EnableChipInt(void) -{ - SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; -} - - -/******************************************************************************* -* Function Name: SDIO_DisableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ -void SDIO_DisableChipInt(void) -{ - SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; -} - - -/******************************************************************************* -* Function Name: SDIO_IRQ -****************************************************************************//** -* -* SDIO interrupt, checks for events, and calls callbacks -* -*******************************************************************************/ -void SDIO_IRQ(void) -{ - uint8_t u8Status; - - /* First read the status register */ - u8Status = SDIO_STATUS_REG; - - /* Check card interrupt */ - if (u8Status & SDIO_STS_CARD_INT ) - { - pfnCardInt_count++; - } - - /* Execute card interrupt callback if neccesary */ - if (0 != pfnCardInt_count) - { - if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) - { - gstcInternalData.pstcCallBacks.pfnCardIntCb(); - } - pfnCardInt_count--; - } - - /* If the command is complete set the flag */ - if (u8Status & SDIO_STS_CMD_DONE) - { - gstcInternalData.stcEvents.u8CmdComplete++; - } - - /* Check if a write is complete */ - if (u8Status & SDIO_STS_WRITE_DONE ) - { - - /* Clear the Write flag and CMD53 flag */ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); - - /* Check if the CRC status return was bad */ - if (u8Status & SDIO_STS_CRC_ERR) - { - /* CRC was bad, set the flag */ - gstcInternalData.stcEvents.u8CRCError++; - } - - /* Set the done flag */ - - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else - gstcInternalData.stcEvents.u8TransComplete++; - #endif - } - - /* Check if a read is complete */ - if (u8Status & SDIO_STS_READ_DONE) - { - /* Clear the read flag */ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); - - /* Check the CRC */ - if (u8Status & SDIO_STS_CRC_ERR) - { - /* CRC was bad, set the flag */ - gstcInternalData.stcEvents.u8CRCError++; - } - /* Okay we're done so set the done flag */ - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else - gstcInternalData.stcEvents.u8TransComplete++; - #endif - } - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); -} - - -/******************************************************************************* -* Function Name: SDIO_READ_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Read interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ -void SDIO_READ_DMA_IRQ(void) -{ - /*Shouldn't have to change anything unless it is the last descriptor*/ - - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) - { - /*We need to increment the destination address every time*/ - readDesr1.dst += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - } - - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) - { - /*We need to increment the destination address everytime*/ - readDesr0.dst += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - } - - /*Clear the interrupt*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - /*decrement y counts*/ - yCounts--; -} - -/******************************************************************************* -* Function Name: SDIO_WRITE_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Write interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ -void SDIO_WRITE_DMA_IRQ(void) -{ - /*We shouldn't have to change anything unless it is the last descriptor*/ - - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) - { - /*We also need to increment the destination address every-time*/ - writeDesr1.src += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - } - - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) - { - /*We also need to increment the destination address*/ - writeDesr0.src += 2048; - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - } - - /*Clear the interrupt*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - yCounts--; -} - -/******************************************************************************* -* Function Name: SDIO_Free -****************************************************************************//** -* -* Frees any system resources that were allocated by the SDIO driver. -* -*******************************************************************************/ -void SDIO_Free(void) -{ -#ifdef CY_RTOS_AWARE - cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); -#endif -} - -/******************************************************************************* -* Function Name: SDIO_SaveConfig -******************************************************************************** -* -* Saves the user configuration of the SDIO UDB non-retention registers. Call the -* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function. -* -*******************************************************************************/ -static void SDIO_SaveConfig(void) -{ - regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0]; - regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1]; - regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2]; - regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3]; -} - - -/******************************************************************************* -* Function Name: SDIO_RestoreConfig -******************************************************************************** -* -* Restores the user configuration of the SDIO UDB non-retention registers. Call -* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function. -* -*******************************************************************************/ -static void SDIO_RestoreConfig(void) -{ - UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0; - UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1; - UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2; - UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3; -} - -#if defined(__cplusplus) -} -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h deleted file mode 100644 index 06edc747bc..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h +++ /dev/null @@ -1,396 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST.h -* -* \brief -* This file provides types definition, constants and function definition for -* the SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \defgroup group_bsp_pin_state Pin States -* \defgroup group_bsp_pins Pin Mappings -* \defgroup group_bsp_macros Macros -* \defgroup group_bsp_functions Functions -* -* \defgroup group_udb_sdio UDB_SDIO -* \{ -* SDIO - Secure Digital Input Output is a standard for communicating with various - external devices such as Wifi and bluetooth devices. -*

-* The driver is currently designed to only support communication with certain -* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general -* SDIO card, or even and SD card. It is only intended to be used by the WiFi -* driver for communication. -*

-* This is not intended to be used as a general purpose API. -* -* \section group_udb_sdio_section_configuration_considerations Configuration Considerations -* Features: -* * Always Four Wire Mode -* * Supports Card Interrupt -* * Uses DMA for command and data transfer -* -* \defgroup group_udb_sdio_macros Macros -* \defgroup group_udb_sdio_functions Functions -* \defgroup group_udb_sdio_data_structures Data Structures -*/ - -#if !defined(CY_SDIO_H) -#define CY_SDIO_H - -#include "SDIO_HOST_cfg.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - -/*************************************** -* API Constants -***************************************/ - -/** -* \addtogroup group_udb_sdio_macros -* \{ -*/ - -#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ -#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ -#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ -#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ - -/*! -\defgroup group_sdio_cmd_constants Constants for the command channel -*/ -/* @{*/ -#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ -#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ -#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/ -#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/ -/*@} group_sdio_cmd_constants */ - -/*! -\defgroup group_sdio_ctrl_reg SDIO control register bits -*/ -/* @{*/ -#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ -#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ -#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ -#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ -#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ -#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ -#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ -#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ -/*@} group_sdio_ctrl_reg */ - -/*! -\defgroup group_sdio_status_reg SDIO status register bits -*/ -/* @{*/ -#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ -#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ -#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ -#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ -#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ -#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ -#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ -/*@} group_sdio_status_reg */ - -/*! -\defgroup group_sdio_crc Constants for 7bit CRC for command -*/ -/* @{*/ -#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ -#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ -/*@} group_sdio_crc */ - -/** \} group_udb_sdio_macros */ - - -/*************************************** -* Type Definitions -***************************************/ - -/** -* \addtogroup group_udb_sdio_data_structures -* \{ -*/ - -/** -* Create a type for the card interrupt call back -*/ -typedef void (* sdio_card_int_cb_t)(void); - -/** -* \brief This enum is used when checking for specific events -*/ -typedef enum en_sdio_event -{ - SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ - SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ - -}en_sdio_event_t; - -/** -* \brief Used to indicate the result of a function -*/ -typedef enum en_sdio_result -{ - Ok = 0x00, /**< No error*/ - Error = 0x01, /**< Non-specific error code*/ - CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ - CommandIdxError = 0x04, /**< The index for the command didn't match*/ - CommandEndError = 0x08, /**< There was an end bit error on the command*/ - DataCrcError = 0x10, /**< There was a data CRC Error*/ - CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ - DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ - ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ - -} en_sdio_result_t; - -/** -* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function -*/ -typedef struct stc_sdcmd_event_flag -{ - uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ - uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ - uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ - -}stc_sdio_event_flag_t; - -/** -* \brief Holds pointers to callback functions -*/ -typedef struct stc_sdio_irq_cb -{ - sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ -}stc_sdio_irq_cb_t; - -/** -* \brief Global structure used to hold data from interrupt and other functions -*/ -typedef struct stc_sdio_gInternalData -{ - stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ - stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ -}stc_sdio_gInternalData_t; - -/** -* \brief structure used for configuring command -*/ -typedef struct stc_sdio_cmd_config -{ - uint8_t u8CmdIndex; /**< Command index*/ - uint32_t u32Argument; /**< The argument of command */ - uint8_t bResponseRequired; /**< TRUE: A Response is required*/ - uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ - -}stc_sdio_cmd_config_t; - -/** -* \brief structure used for the data channel -*/ -typedef struct stc_sdio_data_config -{ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockSize; /**< Block size*/ - uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - -}stc_sdio_data_config_t; - -/** -* \brief structure used for configuring command and data -*/ -typedef struct stc_sdio_cmd -{ - uint32_t u32CmdIdx; /**< Command index*/ - uint32_t u32Arg; /**< The argument of command*/ - uint32_t *pu32Response; /**< Pointer to location to store response*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockCnt; /**< Number of blocks to send*/ - uint16_t u16BlockSize; /**< Block size*/ -}stc_sdio_cmd_t; - -/** \} group_udb_sdio_data_structures */ - -/*************************************** -* Function Prototypes -***************************************/ - -/** -* \addtogroup group_udb_sdio_functions -* \{ -*/ - -/* Main functions*/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); -void SDIO_EnableIntClock(void); -void SDIO_DisableIntClock(void); -void SDIO_EnableSdClk(void); -void SDIO_DisableSdClk(void); -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); -void SDIO_Reset(void); -void SDIO_EnableChipInt(void); -void SDIO_DisableChipInt(void); -void SDIO_Free(void); - -/*Low Level Functions*/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); -void SDIO_SetBlockSize(uint8_t u8ByteCount); -void SDIO_SetNumBlocks(uint8_t u8BlockCount); - -/*DMA setup function*/ -void SDIO_SetupDMA(void); - -/*Interrupt Function*/ -void SDIO_IRQ(void); -void SDIO_READ_DMA_IRQ(void); -void SDIO_WRITE_DMA_IRQ(void); - -void SDIO_Crc7Init(void); - -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); - -/** \endcond */ - -/** \} group_udb_sdio_functions */ - - -/*************************************** -* Hardware Registers -***************************************/ - -/** \cond INTERNAL */ - -#define SDIO_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) - -#define SDIO_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) - -#define SDIO_STATUS_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_REG) - -#define SDIO_STATUS_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_REG) - -#define SDIO_STATUS_INT_MSK (* (reg8*) \ -SDIO_HOST_bSDIO_StatusReg__MASK_REG) - -#define SDIO_STATUS_AUX_CTL (* (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG) - -#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) - -#define SDIO_CMD_COMMAND_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F0_REG) - -#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__A0_REG) - -#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F0_REG) - -#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F1_REG) - -#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F1_REG) - -#define SDIO_DAT_WRITE_REG (* (reg16 *) \ -SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) - -#define SDIO_DAT_WRITE_PTR ( (reg16 *) \ -SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) - -#define SDIO_DAT_READ_REG (* (reg16 *) \ -SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) - -#define SDIO_DAT_READ_PTR ( (reg16 *) \ -SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) - -#define SDIO_BYTE_COUNT_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) - -/** \endcond */ - -#if defined(__cplusplus) -} -#endif - -#endif /* (CY_SDIO_H) */ - -/** \} group_udb_sdio */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c deleted file mode 100644 index a2808d37c0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c +++ /dev/null @@ -1,1056 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.c -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "SDIO_HOST_cfg.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/***************************CMD DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_16CYC, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1L, - .dstXincrement = 0L, - .xCount = 5UL, - .srcYincrement = 0L, - .dstYincrement = 0L, - .yCount = 1UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Read DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0L, - .dstXincrement = 2L, - .xCount = 10UL, - .srcYincrement = 0L, - .dstYincrement = 10L, - .yCount = 2UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Resp DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0L, - .dstXincrement = 1L, - .xCount = 6UL, - .srcYincrement = 0L, - .dstYincrement = 0L, - .yCount = 1UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Write DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_4CYC, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 2L, - .dstXincrement = 0L, - .xCount = 10UL, - .srcYincrement = 10L, - .dstYincrement = 0L, - .yCount = 2UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - - - -/***************UDB Config code *****************/ - -#define CY_CFG_BASE_ADDR_COUNT 12u - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) - #define CYPACKED - #define CYPACKED_ATTR __attribute__ ((packed)) - #define CY_CFG_UNUSED __attribute__ ((unused)) - - -#elif defined(__ICCARM__) - #include - - #define CYPACKED __packed - #define CYPACKED_ATTR - #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") - - -#else - #error Unsupported toolchain -#endif - - -#ifndef CYCODE - #define CYCODE -#endif -#ifndef CYFAR - #define CYFAR -#endif - - -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) -{ - (void)memset(s, 0, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} - -CYPACKED typedef struct -{ - uint8 offset; - uint8 value; -} CYPACKED_ATTR cy_cfg_addrvalue_t; - - -/******************************************************************************* -* Function Name: cfg_write_bytes32 -******************************************************************************** -* Summary: -* This function is used for setting up the chip configuration areas that -* contain relatively sparse data. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ - -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) -{ - /* For 32-bit little-endian architectures */ - uint32 i, j = 0u; - for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) - { - uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; - baseAddr &= 0xFFFFFF00u; - while (count != 0u) - { - CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); - j++; - count--; - } - } -} - -static const uint32 CYCODE cy_cfg_addr_table[] = -{ - 0x40340002u, /* Base address: 0x40340000 Count: 2 */ - 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ - 0x40340301u, /* Base address: 0x40340300 Count: 1 */ - 0x40340405u, /* Base address: 0x40340400 Count: 5 */ - 0x40342466u, /* Base address: 0x40342400 Count: 102 */ - 0x40342632u, /* Base address: 0x40342600 Count: 50 */ - 0x4034282Bu, /* Base address: 0x40342800 Count: 43 */ - 0x40342A5Eu, /* Base address: 0x40342A00 Count: 94 */ - 0x40347005u, /* Base address: 0x40347000 Count: 5 */ - 0x40347102u, /* Base address: 0x40347100 Count: 2 */ - 0x40347202u, /* Base address: 0x40347200 Count: 2 */ - 0x40347804u, /* Base address: 0x40347800 Count: 4 */ -}; - -static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = -{ - {0x18u, 0xFFu}, - {0x1Du, 0x01u}, - {0x00u, 0x10u}, - {0x04u, 0x88u}, - {0x09u, 0x02u}, - {0x10u, 0x10u}, - {0x14u, 0x88u}, - {0x1Du, 0x01u}, - {0x20u, 0x10u}, - {0x24u, 0x88u}, - {0x28u, 0x10u}, - {0x2Cu, 0x88u}, - {0x15u, 0x40u}, - {0x04u, 0x07u}, - {0x14u, 0x47u}, - {0x1Cu, 0x2Fu}, - {0x20u, 0x03u}, - {0x28u, 0x0Fu}, - {0x01u, 0x8Eu}, - {0x03u, 0x70u}, - {0x05u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Du, 0x04u}, - {0x11u, 0x60u}, - {0x13u, 0x80u}, - {0x15u, 0x04u}, - {0x18u, 0x02u}, - {0x19u, 0xD0u}, - {0x1Bu, 0x23u}, - {0x21u, 0x01u}, - {0x23u, 0x20u}, - {0x25u, 0xD0u}, - {0x27u, 0x2Fu}, - {0x2Du, 0x10u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x48u}, - {0x30u, 0x01u}, - {0x31u, 0xE0u}, - {0x34u, 0x02u}, - {0x35u, 0x1Fu}, - {0x3Bu, 0x02u}, - {0x3Du, 0x22u}, - {0x3Eu, 0x11u}, - {0x40u, 0x52u}, - {0x41u, 0x01u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x5Cu, 0x04u}, - {0x5Du, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x86u, 0x20u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x20u}, - {0x90u, 0xBAu}, - {0x92u, 0x04u}, - {0x94u, 0x08u}, - {0x96u, 0x11u}, - {0x98u, 0x78u}, - {0x9Au, 0x02u}, - {0x9Cu, 0x18u}, - {0x9Eu, 0xC4u}, - {0xA3u, 0x01u}, - {0xA4u, 0x08u}, - {0xA6u, 0x10u}, - {0xA8u, 0xFEu}, - {0xABu, 0x01u}, - {0xADu, 0x02u}, - {0xAEu, 0x20u}, - {0xB0u, 0x01u}, - {0xB2u, 0x18u}, - {0xB3u, 0x01u}, - {0xB4u, 0x06u}, - {0xB5u, 0x02u}, - {0xB6u, 0xE0u}, - {0xBAu, 0x08u}, - {0xBFu, 0x14u}, - {0xC0u, 0x52u}, - {0xC1u, 0x01u}, - {0xC4u, 0x06u}, - {0xC5u, 0xB0u}, - {0xC7u, 0x40u}, - {0xC8u, 0x22u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xD4u, 0xDEu}, - {0xD5u, 0x40u}, - {0xD6u, 0x4Bu}, - {0xD7u, 0x04u}, - {0xDCu, 0x0Cu}, - {0xDDu, 0x04u}, - {0xDEu, 0x0Cu}, - {0xDFu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x00u, 0x08u}, - {0x04u, 0x01u}, - {0x05u, 0x07u}, - {0x08u, 0x01u}, - {0x0Au, 0x08u}, - {0x0Fu, 0x05u}, - {0x12u, 0x01u}, - {0x14u, 0x10u}, - {0x16u, 0x01u}, - {0x18u, 0x01u}, - {0x1Au, 0x04u}, - {0x1Eu, 0x0Eu}, - {0x1Fu, 0x06u}, - {0x20u, 0x01u}, - {0x22u, 0x02u}, - {0x25u, 0x03u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x01u}, - {0x32u, 0x10u}, - {0x36u, 0x0Fu}, - {0x37u, 0x07u}, - {0x3Cu, 0x80u}, - {0x40u, 0x36u}, - {0x41u, 0x01u}, - {0x42u, 0x20u}, - {0x44u, 0x05u}, - {0x45u, 0xFBu}, - {0x46u, 0xC0u}, - {0x47u, 0xE0u}, - {0x48u, 0x2Bu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x02u}, - {0x4Fu, 0x0Cu}, - {0x50u, 0x08u}, - {0x51u, 0x10u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x65u, 0x08u}, - {0x68u, 0xC0u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x71u, 0x10u}, - {0x72u, 0x50u}, - {0x73u, 0xA8u}, - {0x82u, 0x08u}, - {0x84u, 0x07u}, - {0x86u, 0xF8u}, - {0x8Cu, 0x0Eu}, - {0x8Eu, 0xD1u}, - {0x92u, 0x21u}, - {0x96u, 0x01u}, - {0x98u, 0x04u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x04u}, - {0xA4u, 0xB9u}, - {0xA6u, 0x06u}, - {0xA8u, 0x89u}, - {0xAAu, 0x72u}, - {0xAEu, 0x60u}, - {0xB0u, 0x80u}, - {0xB2u, 0x7Fu}, - {0xBAu, 0x08u}, - {0xBCu, 0x08u}, - {0xBEu, 0x01u}, - {0xC0u, 0x42u}, - {0xC1u, 0x05u}, - {0xC4u, 0x06u}, - {0xC6u, 0x40u}, - {0xC7u, 0xB0u}, - {0xC8u, 0x28u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x03u, 0x40u}, - {0x09u, 0x10u}, - {0x0Cu, 0x2Au}, - {0x0Du, 0x30u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x0Au}, - {0x15u, 0x30u}, - {0x17u, 0x0Au}, - {0x1Du, 0x0Cu}, - {0x1Eu, 0x14u}, - {0x20u, 0x02u}, - {0x22u, 0x29u}, - {0x23u, 0x35u}, - {0x24u, 0x30u}, - {0x25u, 0x03u}, - {0x28u, 0x03u}, - {0x29u, 0x20u}, - {0x2Au, 0x28u}, - {0x2Cu, 0x0Cu}, - {0x2Du, 0x0Au}, - {0x2Fu, 0x30u}, - {0x30u, 0x01u}, - {0x31u, 0x70u}, - {0x32u, 0x30u}, - {0x33u, 0x0Cu}, - {0x34u, 0x0Cu}, - {0x35u, 0x03u}, - {0x36u, 0x02u}, - {0x38u, 0x28u}, - {0x39u, 0x28u}, - {0x3Eu, 0x55u}, - {0x3Fu, 0x15u}, - {0x40u, 0x42u}, - {0x41u, 0x05u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x7Fu}, - {0x5Cu, 0x04u}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x82u, 0x01u}, - {0x86u, 0x01u}, - {0x8Au, 0x02u}, - {0x8Cu, 0x01u}, - {0x98u, 0x01u}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x01u}, - {0xA8u, 0x01u}, - {0xACu, 0x03u}, - {0xAEu, 0x04u}, - {0xB4u, 0x07u}, - {0xB6u, 0x07u}, - {0xBCu, 0xA0u}, - {0xC0u, 0x42u}, - {0xC1u, 0x05u}, - {0xC4u, 0x06u}, - {0xC7u, 0xB4u}, - {0xC8u, 0x30u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Fu}, - {0xDEu, 0x0Fu}, - {0xDFu, 0x04u}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x28u, 0x10u}, - {0xA8u, 0xE1u}, - {0xACu, 0x52u}, - {0xB0u, 0xAAu}, - {0xB4u, 0x01u}, - {0xA8u, 0xA1u}, - {0xE8u, 0x02u}, - {0xA8u, 0x87u}, - {0xACu, 0x53u}, - {0x00u, 0x01u}, - {0x10u, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x01u}, -}; - - - -CYPACKED typedef struct -{ -void *address; -uint16 size; -} CYPACKED_ATTR cfg_memset_t; - - -CYPACKED typedef struct -{ - void *dest; - const void *src; - size_t size; -} CYPACKED_ATTR cfg_memcpy_t; - -static const cfg_memset_t CYCODE cfg_memset_list[] = -{ - /* address, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), 116u}, -}; - -/* UDB_UDBPAIR4_UDBSNG0 Address: CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG0_VAL[] = -{ - 0x42u, 0x00u, 0x25u, 0x0Au, 0x50u, 0x00u, 0x08u, 0x00u, 0x48u, 0x00u, 0x10u, 0x05u, 0x04u, 0x00u, 0x00u, 0x00u, - 0x61u, 0x00u, 0x06u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x00u, 0x41u, 0x0Cu, 0x26u, 0x03u, 0x00u, 0x00u, 0x04u, 0x0Au, - 0x48u, 0x05u, 0x10u, 0x00u, 0x40u, 0x00u, 0x18u, 0x05u, 0x04u, 0x00u, 0x00u, 0x05u, 0x02u, 0x00u, 0x00u, 0x00u, - 0x07u, 0x0Cu, 0x40u, 0x03u, 0x07u, 0x00u, 0x38u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x22u, 0x00u, 0x44u, 0x05u, - 0x42u, 0x05u, 0x00u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x71u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR3_UDBSNG1 Address: CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG1_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x88u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x02u, 0x88u, 0x01u, 0x00u, - 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x88u, 0x03u, 0x00u, 0x01u, 0xBCu, 0x00u, 0x40u, 0x39u, 0x22u, 0x46u, 0xC5u, - 0x00u, 0x00u, 0x04u, 0x01u, 0x28u, 0xA2u, 0x56u, 0x4Du, 0x51u, 0x00u, 0x2Eu, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, - 0x00u, 0x60u, 0x00u, 0x80u, 0x1Fu, 0x00u, 0x60u, 0x1Fu, 0x00u, 0x80u, 0x20u, 0x00u, 0x20u, 0x80u, 0x40u, 0x05u, - 0x64u, 0x03u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x06u, 0x11u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0xA0u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x73u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x00u, 0x00u, 0x40u, 0x40u, 0x10u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = -{ - 0x04u, 0x20u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x79u, 0x00u, 0x82u, 0x11u, 0x48u, 0x2Eu, 0x95u, - 0x09u, 0x08u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x8Du, 0x00u, 0x72u, 0x20u, 0x08u, 0x00u, 0x00u, - 0x2Eu, 0x00u, 0x11u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, - 0x38u, 0xE0u, 0x02u, 0x07u, 0x04u, 0x18u, 0x01u, 0x07u, 0x00u, 0x00u, 0x82u, 0x22u, 0x82u, 0xAAu, 0x14u, 0x00u, - 0x41u, 0x05u, 0x63u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0xF0u, 0x21u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x08u, 0x03u, 0x08u, 0x00u, 0x18u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x58u, 0xECu, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR0_UDBSNG0 Address: CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG0_VAL[] = -{ - 0x95u, 0x08u, 0x6Au, 0x00u, 0x26u, 0x62u, 0xD9u, 0x9Du, 0x82u, 0x00u, 0x40u, 0x42u, 0x00u, 0x00u, 0x80u, 0x00u, - 0x00u, 0x00u, 0x90u, 0x32u, 0x4Eu, 0x00u, 0xB1u, 0x01u, 0x92u, 0x00u, 0x6Du, 0x00u, 0x00u, 0xB5u, 0x04u, 0x4Au, - 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0xF2u, 0x00u, 0x09u, 0x00u, 0x66u, 0x01u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x3Fu, 0xE0u, 0xC0u, 0x1Fu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x2Au, 0x0Au, 0x2Au, 0x0Au, 0x00u, 0x00u, - 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR1_UDBSNG0 Address: CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG0_VAL[] = -{ - 0x00u, 0x01u, 0x00u, 0x00u, 0xABu, 0x00u, 0x00u, 0x03u, 0x2Bu, 0xC9u, 0x54u, 0x12u, 0x02u, 0x00u, 0x00u, 0x40u, - 0xAAu, 0x00u, 0x01u, 0x01u, 0x81u, 0x05u, 0x2Au, 0xBAu, 0xAAu, 0x00u, 0x00u, 0x40u, 0x08u, 0xB3u, 0x00u, 0x4Cu, - 0x04u, 0x20u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x01u, 0x10u, 0x01u, 0x00u, 0x80u, 0x20u, 0xB1u, 0x00u, 0x04u, - 0x19u, 0x00u, 0x07u, 0x80u, 0x61u, 0x00u, 0x80u, 0x7Fu, 0x2Au, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x55u, 0x04u, - 0x24u, 0x06u, 0x00u, 0x00u, 0x01u, 0x0Eu, 0x00u, 0xC4u, 0x31u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, - 0x40u, 0x03u, 0x00u, 0x10u -}; - -/* UDB_UDBPAIR0_UDBSNG1 Address: CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG1_VAL[] = -{ - 0x00u, 0x00u, 0x80u, 0x03u, 0x7Bu, 0x04u, 0x80u, 0x00u, 0x33u, 0x1Cu, 0xCCu, 0x00u, 0x04u, 0x03u, 0x00u, 0x00u, - 0x8Au, 0x00u, 0x71u, 0x04u, 0xB9u, 0x00u, 0x42u, 0x0Cu, 0x00u, 0x03u, 0x20u, 0x00u, 0x00u, 0x14u, 0x00u, 0x00u, - 0x00u, 0x00u, 0xA0u, 0x03u, 0x0Au, 0x1Cu, 0xD0u, 0x00u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, - 0x00u, 0x07u, 0x00u, 0x18u, 0xF8u, 0x00u, 0x07u, 0x00u, 0x80u, 0x08u, 0x20u, 0x00u, 0x20u, 0x00u, 0x40u, 0x05u, - 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x0Bu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x25u, 0x40u, 0x13u, 0x30u, - 0x54u, 0xF1u, 0x1Fu, 0xF6u, 0xF5u, 0x33u, 0x05u, 0x12u, 0x33u, 0x51u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x21u, 0x32u, 0x75u, 0x37u, 0x23u, 0xF5u, 0x51u, 0x14u, 0x54u, 0x32u, 0x11u, 0x41u, - 0x33u, 0x51u, 0xFFu, 0x0Fu, 0x5Fu, 0xFFu, 0x2Fu, 0x22u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x14u, 0x01u, 0x01u, 0x11u, 0x10u, 0x44u, 0x53u, 0x33u, 0x14u, 0x11u, 0x40u, 0x01u, 0x01u, 0x33u, 0x4Cu, 0x04u, - 0x11u, 0x01u, 0x3Bu, 0x01u, 0x01u, 0x10u, 0x11u, 0x00u, 0x62u, 0x10u, 0x11u, 0x13u, 0x11u, 0x19u, 0x11u, 0x16u, - 0x09u, 0x73u, 0x10u, 0x66u, 0x11u, 0x11u, 0x11u, 0x11u, 0x12u, 0x11u, 0x11u, 0x14u, 0x11u, 0x14u, 0x11u, 0x11u -}; - -/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0xF5u, 0x5Fu, - 0x22u, 0xFFu, 0x04u, 0xF1u, 0x56u, 0x63u, 0x61u, 0x12u, 0xF7u, 0x04u, 0x37u, 0x16u, 0x63u, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, 0x52u, 0x75u, 0x60u, 0x45u, 0x04u, 0x14u, 0x31u, 0x44u, 0x12u, 0x76u, 0x13u, - 0x51u, 0x73u, 0x70u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x25u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x00u, 0xF5u, - 0x4Fu, 0x06u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x03u, 0x06u, 0x00u, 0xA1u, 0x06u, 0x0Cu, 0x36u, 0xF5u, 0x0Du, 0x10u, 0xF3u, 0x01u, 0x00u, 0xFFu, 0x3Fu, 0x0Fu, - 0x15u, 0x00u, 0xFBu, 0x01u, 0x03u, 0x10u, 0x11u, 0x4Cu, 0x11u, 0x52u, 0x90u, 0xC1u, 0xD2u, 0x15u, 0xC3u, 0x5Fu, - 0x36u, 0x0Fu, 0x23u, 0x3Cu, 0x00u, 0x11u, 0x15u, 0x11u, 0x11u, 0x31u, 0x14u, 0x1Fu, 0x11u, 0x8Fu, 0x11u, 0xC1u -}; - -/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x11u, 0xFFu, 0x45u, - 0xFFu, 0x5Fu, 0xF5u, 0x44u, 0x4Fu, 0x36u, 0x43u, 0x73u, 0x13u, 0xFFu, 0x23u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x6Fu, 0x24u, 0x45u, 0x44u, 0x1Fu, 0x63u, 0x17u, 0x1Fu, 0xFFu, 0xFFu, 0x4Fu, 0xFFu, - 0x13u, 0x14u, 0x63u, 0x07u, 0x55u, 0xF7u, 0xF7u, 0x72u, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x05u, 0x2Fu, 0x10u, - 0xF0u, 0xF3u, 0xF0u, 0x10u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x01u, 0x00u, 0x8Du, 0x16u, 0x21u, 0x0Fu, 0x1Fu, 0x1Fu, 0xAFu, 0xB0u, 0x0Fu, 0xADu, 0x00u, 0xFFu, 0x4Fu, 0x00u, - 0x05u, 0x0Du, 0x0Au, 0x41u, 0x00u, 0xAAu, 0x01u, 0xF1u, 0xC4u, 0x10u, 0xF0u, 0x04u, 0xF3u, 0x1Fu, 0xC4u, 0x3Fu, - 0x1Fu, 0x03u, 0xF0u, 0xF0u, 0x88u, 0x01u, 0x3Fu, 0x01u, 0x11u, 0xB1u, 0x57u, 0x81u, 0x11u, 0xC1u, 0x1Du, 0x14u -}; - -/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x36u, 0x34u, 0x32u, - 0x06u, 0x14u, 0xF5u, 0x46u, 0x43u, 0xF6u, 0xF3u, 0x43u, 0xFFu, 0x37u, 0x5Fu, 0xFFu, 0x5Fu, 0xF2u, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x45u, 0xF4u, 0x37u, 0x40u, 0xF0u, 0xF2u, 0x7Fu, 0xF4u, 0xF4u, 0xFFu, 0xF3u, 0x03u, - 0x73u, 0xF0u, 0x77u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF2u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x00u, 0x06u, 0xBFu, 0x17u, 0x11u, 0x7Fu, 0x71u, 0x11u, 0x5Fu, 0x70u, 0x5Fu, 0xFFu, 0x06u, 0xFFu, 0x0Fu, 0x07u, - 0x7Fu, 0x3Fu, 0x0Fu, 0xF6u, 0x00u, 0x2Fu, 0x7Fu, 0x48u, 0xF4u, 0x30u, 0xB0u, 0x5Fu, 0x11u, 0x0Fu, 0x91u, 0xFFu, - 0x1Fu, 0x0Au, 0xF3u, 0xFBu, 0x15u, 0x11u, 0x1Fu, 0xA1u, 0x11u, 0x81u, 0x11u, 0x12u, 0x14u, 0x11u, 0x1Fu, 0x31u -}; - -/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x17u, 0xF5u, 0x65u, - 0x77u, 0x77u, 0x7Fu, 0x05u, 0x14u, 0xF4u, 0x5Fu, 0x0Fu, 0x1Fu, 0x5Fu, 0x43u, 0x5Fu, 0xFFu, 0xF2u, 0xFFu, 0x05u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x23u, 0x7Fu, 0x52u, 0x64u, 0x55u, 0x75u, 0xFFu, 0xFFu, 0xF5u, 0xFFu, 0x11u, 0xFFu, - 0x1Fu, 0x52u, 0x13u, 0x40u, 0xFFu, 0xF3u, 0xFFu, 0xF5u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x25u, 0x00u, 0x30u, - 0x00u, 0x00u, 0x00u, 0x13u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x00u, 0x81u, 0x1Fu, 0x11u, 0x11u, 0x5Fu, 0x91u, 0x10u, 0xFFu, 0x33u, 0x0Fu, 0xFFu, 0x30u, 0xFFu, 0x4Fu, 0x31u, - 0x1Fu, 0xFFu, 0x06u, 0x06u, 0x0Au, 0x28u, 0x08u, 0x66u, 0x11u, 0x10u, 0xF9u, 0x17u, 0x20u, 0x3Fu, 0x10u, 0x2Fu, - 0x1Fu, 0x00u, 0xF1u, 0xF6u, 0x1Bu, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x33u, 0x31u, 0x11u, 0x17u, 0x11u, 0x11u, 0x1Bu -}; - -/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, 0x43u, 0xFFu, 0x30u, - 0xF0u, 0x22u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Fu, 0x5Fu, 0x53u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x42u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0xF3u, 0x1Fu, 0x15u, 0x11u, 0x13u, 0x13u, 0x41u, 0xF1u, 0x31u, 0x3Fu, - 0x1Fu, 0x53u, 0x03u, 0xF0u, 0x4Fu, 0xFFu, 0x2Fu, 0x13u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x01u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x23u, 0x11u, 0x1Fu, 0x11u, 0x31u, 0x7Fu, 0x61u, 0x17u, 0xBFu, 0x8Cu, 0x8Fu, 0xFFu, 0x39u, 0x1Fu, 0x95u, 0x1Cu, - 0x1Fu, 0xFFu, 0x6Cu, 0x7Fu, 0x33u, 0x1Fu, 0x7Fu, 0xFFu, 0x44u, 0x13u, 0x11u, 0x11u, 0x13u, 0x81u, 0x7Cu, 0x12u, - 0x11u, 0xCCu, 0x16u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI0_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI1_VAL[] = -{ - 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x20u, 0xF1u, 0x0Fu, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x10u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI2_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x0Au, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Au, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x13u, 0x0Au, 0x00u, 0x0Du, 0x16u, 0x1Fu, 0x11u, 0x1Fu, - 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0xF4u, 0xF0u, 0x10u, 0x10u, 0x50u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x01u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x12u, 0x11u, 0xBFu, 0x11u, 0x11u, 0x1Du, 0x01u, 0x11u, 0x12u, 0x11u, 0x11u, 0x01u, 0xF1u, 0x10u, - 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, - 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI3_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x03u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI4_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI5_VAL[] = -{ - 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI6_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, 0x03u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI7_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x0Au, 0x1Fu, 0x08u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x02u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, 0x10u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u -}; - -/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI8_VAL[] = -{ - 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0xF0u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x1Du, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI9_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI10_VAL[] = -{ - 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x0Cu, 0x1Fu, 0x03u, 0x06u, 0x1Fu, 0x1Fu, 0x05u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, 0x00u, 0xF0u, 0x00u, 0x00u, 0x00u, 0xFFu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI11_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), BS_UDB_UDBPAIR4_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), BS_UDB_UDBPAIR3_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), BS_UDB_UDBPAIR0_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), BS_UDB_UDBPAIR1_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), BS_UDB_UDBPAIR0_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, -}; - -void SDIO_Host_Config_TriggerMuxes(void) -{ - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); - - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); -} - -void SDIO_Host_Config_UDBs(void) -{ - size_t i; - - /* Power on the UDB array */ - CY_SET_REG32(0x402101F0u, 0x05FA0003u); - - /* Zero out critical memory blocks before beginning configuration */ - for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - { - const cfg_memset_t *ms = &cfg_memset_list[i]; - CYMEMZERO(ms->address, ms->size); - } - - /* Copy device configuration data into registers */ - for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) - { - const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; - CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); - } - - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - - /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ - CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); - - /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C4C4Cu); - - /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x4C4C444Cu); - - /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x044C4C44u); - - /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C4Cu); - - /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x004C4C44u); - - /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x0C4C040Cu); - - /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x008C8C8Cu); - - /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - - /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x4C4C444Cu); - - /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x008C808Cu); - - /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x8C8C0404u); - - /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x048F808Fu); - - /* Enable UDB array and digital routing */ - CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); -} - -#if defined(__cplusplus) -} -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h deleted file mode 100644 index 39febda573..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h +++ /dev/null @@ -1,931 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.h -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#if !defined(CY_SDIO_CFG_H) -#define CY_SDIO_CFG_H - -#include - -#include "cy_dma.h" -#include "cy_sysclk.h" -#include "cy_trigmux.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u -#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u -#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u -#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu -#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u - -#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u -#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u - -#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu -#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu - -#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu -#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu - -#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu -#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu -#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu -#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu -#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu -#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu -#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu -#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu - -#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u -#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u -#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u -#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u - -#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u -#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u -#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u -#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u -#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u -#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u - - -#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u -#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u -#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u -#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u -#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u -#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u - - -#define CYDEV_UDB_DSI0_BASE 0x40346000u -#define CYDEV_UDB_DSI1_BASE 0x40346080u -#define CYDEV_UDB_DSI2_BASE 0x40346100u -#define CYDEV_UDB_DSI3_BASE 0x40346180u -#define CYDEV_UDB_DSI4_BASE 0x40346200u -#define CYDEV_UDB_DSI5_BASE 0x40346280u -#define CYDEV_UDB_DSI6_BASE 0x40346300u -#define CYDEV_UDB_DSI7_BASE 0x40346380u -#define CYDEV_UDB_DSI8_BASE 0x40346400u -#define CYDEV_UDB_DSI9_BASE 0x40346480u -#define CYDEV_UDB_DSI10_BASE 0x40346500u -#define CYDEV_UDB_DSI11_BASE 0x40346580u - -#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u - -/*************Defines for UDBs from Creator*****************************/ -/***********These come for cyfitter.h**********************************/ - -/* TFT_DMA */ -#define TFT_DMA_DW__BLOCK_HW DW0 -#define TFT_DMA_DW__BLOCK_NUMBER 0u -#define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2 -#define TFT_DMA_DW__CHANNEL_NUMBER 2u -#define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2 -#define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2 - -/* TFT_CTRL */ -#define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u -#define TFT_CTRL_Sync_ctrl_reg__0__POS 0 -#define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u -#define TFT_CTRL_Sync_ctrl_reg__1__POS 1 -#define TFT_CTRL_Sync_ctrl_reg__2__MASK 0x04u -#define TFT_CTRL_Sync_ctrl_reg__2__POS 2 -#define TFT_CTRL_Sync_ctrl_reg__3__MASK 0x08u -#define TFT_CTRL_Sync_ctrl_reg__3__POS 3 -#define TFT_CTRL_Sync_ctrl_reg__4__MASK 0x10u -#define TFT_CTRL_Sync_ctrl_reg__4__POS 4 -#define TFT_CTRL_Sync_ctrl_reg__5__MASK 0x20u -#define TFT_CTRL_Sync_ctrl_reg__5__POS 5 -#define TFT_CTRL_Sync_ctrl_reg__6__MASK 0x40u -#define TFT_CTRL_Sync_ctrl_reg__6__POS 6 -#define TFT_CTRL_Sync_ctrl_reg__7__MASK 0x80u -#define TFT_CTRL_Sync_ctrl_reg__7__POS 7 -#define TFT_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG 0x4034192Cu -#define TFT_CTRL_Sync_ctrl_reg__CONTROL_REG 0x4034172Cu -#define TFT_CTRL_Sync_ctrl_reg__CONTROL_ST_REG 0x4034032Cu -#define TFT_CTRL_Sync_ctrl_reg__COUNT_REG 0x4034172Cu -#define TFT_CTRL_Sync_ctrl_reg__COUNT_ST_REG 0x4034032Cu -#define TFT_CTRL_Sync_ctrl_reg__MASK 0xFFu -#define TFT_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG 0x4034042Cu -#define TFT_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG 0x4034042Cu -#define TFT_CTRL_Sync_ctrl_reg__PERIOD_REG 0x4034182Cu -#define TFT_CTRL_Sync_ctrl_reg__RC_CFG0 0x40342ADCu -#define TFT_CTRL_Sync_ctrl_reg__RC_CFG1 0x40342AE0u -#define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u -#define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u - -/* SDIO_HOST */ -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x4034001Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x4034011Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x403426C0u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x403426C4u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x403426C8u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x403426CCu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x403426D0u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x403426E4u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x403426E8u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x403426ECu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x403426F0u -#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x4034021Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__MSK_DP_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__PER_DP_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x40342854u -#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x40342858u -#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341620u -#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_REG 0x40341620u -#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x40342854u -#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x40342858u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341620u -#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340018u -#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340118u -#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342640u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342644u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342648u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034264Cu -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342650u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342664u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342668u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034266Cu -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342670u -#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340218u -#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034265Cu -#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342660u -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x403426D4u -#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x403426D8u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_REG 0x4034161Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_REG 0x4034161Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x403426D4u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x403426D8u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034161Cu -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u -#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u -#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u -#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0 -#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u -#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1 -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u -#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2 -#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u -#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3 -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u -#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4 -#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u -#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6 -#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u -#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7 -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340314u -#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340314u -#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu -#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x403424D4u -#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x403424D8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342040u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342044u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342048u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034204Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342050u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342064u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342068u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034206Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342070u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034205Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342060u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403420C0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403420C4u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403420C8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403420CCu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403420D0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403420E4u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403420E8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403420ECu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403420F0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__MSK_DP_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__PER_DP_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342440u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342444u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342448u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x4034244Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342450u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342464u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342468u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x4034246Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342470u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x4034245Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342460u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x40340014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x40340114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x403424C0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x403424C4u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x403424C8u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x403424CCu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x403424D0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x403424E4u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x403424E8u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x403424ECu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x403424F0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x40340214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341028u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341128u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341228u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341328u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341528u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340028u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341028u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341128u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340128u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341228u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341328u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342A40u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342A44u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342A48u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x40342A4Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342A50u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342A64u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342A68u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x40342A6Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342A70u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340228u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341528u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__MSK_DP_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__PER_DP_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x4034002Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x4034102Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x4034112Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x4034012Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x4034122Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x4034132Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x4034192Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x40342AC0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x40342AC4u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x40342AC8u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x40342ACCu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x40342AD0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x40342AE4u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x40342AE8u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x40342AECu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x40342AF0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x4034022Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x4034142Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x4034152Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x40342ADCu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x40342AE0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342840u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342844u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342848u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034284Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342850u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342864u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342868u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034286Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342870u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x40341024u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x40341124u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x40341224u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x40341324u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x40341424u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x40341524u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x40340024u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x40341024u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x40341124u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x40340124u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x40341224u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x40341324u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403428C0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403428C4u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403428C8u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403428CCu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403428D0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403428E4u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403428E8u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403428ECu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403428F0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x40340224u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x40341424u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x40341524u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403428DCu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403428E0u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x4034000Cu -#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x4034010Cu -#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403422C0u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403422C4u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403422C8u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403422CCu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403422D0u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403422E4u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403422E8u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403422ECu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403422F0u -#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x4034020Cu -#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403422DCu -#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403422E0u -#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x4034160Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x4034160Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403422DCu -#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403422E0u -#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403422D4u -#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403422D8u -#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x4034160Cu -#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u -#define SDIO_HOST_bSDIO_StatusReg__0__POS 0 -#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u -#define SDIO_HOST_bSDIO_StatusReg__1__POS 1 -#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341614u -#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u -#define SDIO_HOST_bSDIO_StatusReg__2__POS 2 -#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u -#define SDIO_HOST_bSDIO_StatusReg__3__POS 3 -#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341614u -#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u -#define SDIO_HOST_bSDIO_StatusReg__6__POS 6 -#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu -#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x403424D4u -#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x403424D8u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340314u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340314u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341614u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x40340008u -#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x40340108u -#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x40342240u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x40342244u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x40342248u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x4034224Cu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x40342250u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x40342264u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x40342268u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x4034226Cu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x40342270u -#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x40340208u -#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x4034225Cu -#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x40342260u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x40340308u -#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x40340308u -#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x4034225Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x40342260u -#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x40342254u -#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x40342258u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x403420D4u -#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x403420D8u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x403420D4u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x403420D8u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341604u -#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0 -#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u -#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1 -#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u -#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1 -#define SDIO_HOST_Internal_Clock__DIV_IDX 0 -#define SDIO_HOST_Internal_Clock__DIV_NUM 0 -#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT -#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1 -#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u -#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3 -#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u -#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3 -#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0 -#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u -#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0 -#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u -#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0 -#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1 -#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u -#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1 -#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u -#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 - - -/***************************CMD DMA***************************************/ -#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) -#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) -#define SDIO_HOST_CMD_DMA_HW (DW0) -#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_CMD_DMA_PRIORITY (1u) -#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; - -/***************************Read DMA***************************************/ -#define SDIO_HOST_Read_DMA_DW_BLOCK (1u) -#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) -#define SDIO_HOST_Read_DMA_HW (DW1) -#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Read_DMA_PRIORITY (0u) -#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Read_DMA_PREEMPTABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; - -/***************************Resp DMA***************************************/ -#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) -#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) -#define SDIO_HOST_Resp_DMA_HW (DW0) -#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Resp_DMA_PRIORITY (1u) -#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; - -/***************************Write DMA***************************************/ -#define SDIO_HOST_Write_DMA_DW_BLOCK (1u) -#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) -#define SDIO_HOST_Write_DMA_HW (DW1) -#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Write_DMA_PRIORITY (0u) -#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Write_DMA_PREEMPTABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; - -/***************************SDIO Clock**************************************/ -/* The peripheral clock divider number */ -#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0) -/* The peripheral clock divider type */ -#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) - -/*Function for configuring TriggerMuxes*/ -void SDIO_Host_Config_TriggerMuxes(void); - -/*Function for configuring UDBs*/ -void SDIO_Host_Config_UDBs(void); - -/* SDIO_HOST_Read_Int */ -#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Read_Int__INTC_NUMBER 69u -#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Read_Int_INTC_NUMBER 69u - -/* SDIO_HOST_sdio_int */ -#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_sdio_int__INTC_NUMBER 122u -#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_sdio_int_INTC_NUMBER 122u - -/* SDIO_HOST_Write_Int */ -#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Write_Int__INTC_NUMBER 67u -#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Write_Int_INTC_NUMBER 67u - -#if defined(__cplusplus) -} -#endif - -#endif /* !defined(CY_SDIO_CFG_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h index 501c6a8589..effde09b28 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,28 +101,50 @@ extern "C" { */ /** LED 8; User LED1 */ +#ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_LED9 #define CYBSP_LED9 (P13_7) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_LED_RGB_RED #define CYBSP_LED_RGB_RED (P0_3) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_LED_RGB_GREEN #define CYBSP_LED_RGB_GREEN (P1_1) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_LED_RGB_BLUE #define CYBSP_LED_RGB_BLUE (P11_1) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_USER_LED3 #define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_USER_LED4 #define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_USER_LED5 #define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -122,12 +155,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -138,76 +177,140 @@ extern "C" { */ /** Pin: WIFI SDIO D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif /** Pin: WIFI SDIO D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif /** Pin: WIFI SDIO D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif /** Pin: WIFI SDIO D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif /** Pin: WIFI SDIO CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif /** Pin: WIFI SDIO CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif /** Pin: WIFI ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif /** Pin: WIFI Host Wakeup */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P2_7) +#endif /** Pin: BT UART RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P3_0) +#endif /** Pin: BT UART TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P3_1) +#endif /** Pin: BT UART RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P3_2) +#endif /** Pin: BT UART CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P3_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P3_4) +#endif /** Pin: BT Host Wakeup */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P3_5) +#endif /** Pin: BT Device Wakeup */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P4_0) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P12_0) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P12_1) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P12_2) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P12_4) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) @@ -223,49 +326,93 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#ifndef CYBSP_A0 +#define CYBSP_A0 (P10_0) +#endif /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#ifndef CYBSP_A1 +#define CYBSP_A1 (P10_1) +#endif /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#ifndef CYBSP_A2 +#define CYBSP_A2 (P10_2) +#endif /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#ifndef CYBSP_A3 +#define CYBSP_A3 (P10_3) +#endif /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#ifndef CYBSP_A4 +#define CYBSP_A4 (P10_4) +#endif /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#ifndef CYBSP_A5 +#define CYBSP_A5 (P10_5) +#endif /** Arduino D0 */ +#ifndef CYBSP_D0 #define CYBSP_D0 (P5_0) +#endif /** Arduino D1 */ +#ifndef CYBSP_D1 #define CYBSP_D1 (P5_1) +#endif /** Arduino D2 */ +#ifndef CYBSP_D2 #define CYBSP_D2 (P5_2) +#endif /** Arduino D3 */ +#ifndef CYBSP_D3 #define CYBSP_D3 (P5_3) +#endif /** Arduino D4 */ +#ifndef CYBSP_D4 #define CYBSP_D4 (P5_4) +#endif /** Arduino D5 */ +#ifndef CYBSP_D5 #define CYBSP_D5 (P5_5) +#endif /** Arduino D6 */ +#ifndef CYBSP_D6 #define CYBSP_D6 (P5_6) +#endif /** Arduino D7 */ +#ifndef CYBSP_D7 #define CYBSP_D7 (P0_2) +#endif /** Arduino D8 */ +#ifndef CYBSP_D8 #define CYBSP_D8 (P13_0) +#endif /** Arduino D9 */ +#ifndef CYBSP_D9 #define CYBSP_D9 (P13_1) +#endif /** Arduino D10 */ +#ifndef CYBSP_D10 #define CYBSP_D10 (P12_3) +#endif /** Arduino D11 */ +#ifndef CYBSP_D11 #define CYBSP_D11 (P12_0) +#endif /** Arduino D12 */ +#ifndef CYBSP_D12 #define CYBSP_D12 (P12_1) +#endif /** Arduino D13 */ +#ifndef CYBSP_D13 #define CYBSP_D13 (P12_2) +#endif /** Arduino D14 */ +#ifndef CYBSP_D14 #define CYBSP_D14 (P6_1) +#endif /** Arduino D15 */ +#ifndef CYBSP_D15 #define CYBSP_D15 (P6_0) +#endif /** \} group_bsp_pins_arduino */ @@ -276,45 +423,85 @@ extern "C" { */ /** Cypress J2 Header pin 1 */ +#ifndef CYBSP_J2_1 #define CYBSP_J2_1 (CYBSP_A0) +#endif /** Cypress J2 Header pin 2 */ +#ifndef CYBSP_J2_2 #define CYBSP_J2_2 (P9_0) +#endif /** Cypress J2 Header pin 3 */ +#ifndef CYBSP_J2_3 #define CYBSP_J2_3 (CYBSP_A1) +#endif /** Cypress J2 Header pin 4 */ +#ifndef CYBSP_J2_4 #define CYBSP_J2_4 (P9_1) +#endif /** Cypress J2 Header pin 5 */ +#ifndef CYBSP_J2_5 #define CYBSP_J2_5 (CYBSP_A2) +#endif /** Cypress J2 Header pin 6 */ +#ifndef CYBSP_J2_6 #define CYBSP_J2_6 (P9_2) +#endif /** Cypress J2 Header pin 7 */ +#ifndef CYBSP_J2_7 #define CYBSP_J2_7 (CYBSP_A3) +#endif /** Cypress J2 Header pin 8 */ +#ifndef CYBSP_J2_8 #define CYBSP_J2_8 (P9_3) +#endif /** Cypress J2 Header pin 9 */ +#ifndef CYBSP_J2_9 #define CYBSP_J2_9 (CYBSP_A4) +#endif /** Cypress J2 Header pin 10 */ +#ifndef CYBSP_J2_10 #define CYBSP_J2_10 (P9_4) +#endif /** Cypress J2 Header pin 11 */ +#ifndef CYBSP_J2_11 #define CYBSP_J2_11 (CYBSP_A5) +#endif /** Cypress J2 Header pin 12 */ +#ifndef CYBSP_J2_12 #define CYBSP_J2_12 (P9_5) +#endif /** Cypress J2 Header pin 13 */ +#ifndef CYBSP_J2_13 #define CYBSP_J2_13 (P10_6) +#endif /** Cypress J2 Header pin 14 */ +#ifndef CYBSP_J2_14 #define CYBSP_J2_14 (NC) +#endif /** Cypress J2 Header pin 15 */ +#ifndef CYBSP_J2_15 #define CYBSP_J2_15 (P6_2) +#endif /** Cypress J2 Header pin 16 */ +#ifndef CYBSP_J2_16 #define CYBSP_J2_16 (P9_6) +#endif /** Cypress J2 Header pin 17 */ +#ifndef CYBSP_J2_17 #define CYBSP_J2_17 (P6_3) +#endif /** Cypress J2 Header pin 18 */ +#ifndef CYBSP_J2_18 #define CYBSP_J2_18 (P9_7) +#endif /** Cypress J2 Header pin 19 */ +#ifndef CYBSP_J2_19 #define CYBSP_J2_19 (P13_6) +#endif /** Cypress J2 Header pin 20 */ +#ifndef CYBSP_J2_20 #define CYBSP_J2_20 (P13_7) +#endif /** \} group_bsp_pins_j2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 4ff5ccb454..7a99d7b707 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index a9d28573c6..b78effb0c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3a0414efa3..61d4a4b17b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 0f7f5fe0df..e9a6874e34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 9be3c4aa3b..f0a3d746f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index b405a8b603..51808a1db4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *

Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index ed8102601f..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 55f9bd74fa..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 46ae60d212..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 45223d1950..41fe86f553 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 9512e17264..1bbe7b6308 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 682af2fcd3..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 181ef57d60..de38a7a37c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 8d437beab5..41388b9638 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 9d396e04a2..ccaccdf0ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_TX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_TX_PORT_NUM, .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 249d1ffc72..a54e4c7ad8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -417,7 +417,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 14d433859d..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 0ee62b1d55..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index 56e95d20c8..f8200c70ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index b26ae3cc61..e23fab508d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -41,7 +41,7 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 1e8c349ee2..1aed94281c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -75,7 +75,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -89,7 +89,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -97,7 +97,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -105,7 +105,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -113,7 +113,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -121,14 +121,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -264,14 +264,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -302,7 +302,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -313,59 +313,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -375,7 +375,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -422,21 +422,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -483,7 +483,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -530,48 +530,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 0535600be0..bace2bf4d1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 5557ddecdd..909b041e9f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,4 +1,3 @@ set SMIF_BANKS { 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} } - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 13cf564a5a..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,13 +1,6 @@ - - + + @@ -121,12 +114,12 @@ + - @@ -223,12 +216,12 @@ + - @@ -325,12 +318,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 3c5fbe94fb..f6145a495b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index 474024e377..4059eac047 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -75,14 +75,6 @@ - - - - - - - - @@ -96,16 +88,6 @@ - - - - - - - - - - @@ -275,9 +257,6 @@ - - - @@ -286,9 +265,6 @@ - - - @@ -417,7 +393,6 @@ - @@ -435,8 +410,6 @@ - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h index 5e70332211..d8d83a8b18 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,28 +101,50 @@ extern "C" { */ /** LED 8; User LED1 */ +#ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_LED9 #define CYBSP_LED9 (P13_7) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_LED_RGB_RED #define CYBSP_LED_RGB_RED (P0_3) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_LED_RGB_GREEN #define CYBSP_LED_RGB_GREEN (P1_1) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_LED_RGB_BLUE #define CYBSP_LED_RGB_BLUE (P11_1) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_USER_LED3 #define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_USER_LED4 #define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_USER_LED5 #define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -122,12 +155,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -138,76 +177,140 @@ extern "C" { */ /** Pin: WIFI SDIO D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif /** Pin: WIFI SDIO D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif /** Pin: WIFI SDIO D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif /** Pin: WIFI SDIO D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif /** Pin: WIFI SDIO CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif /** Pin: WIFI SDIO CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif /** Pin: WIFI ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif /** Pin: WIFI Host Wakeup */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P2_7) +#endif /** Pin: BT UART RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P3_0) +#endif /** Pin: BT UART TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P3_1) +#endif /** Pin: BT UART RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P3_2) +#endif /** Pin: BT UART CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P3_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P3_4) +#endif /** Pin: BT Host Wakeup */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P3_5) +#endif /** Pin: BT Device Wakeup */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P4_0) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P12_0) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P12_1) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P12_2) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P12_4) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) @@ -223,49 +326,93 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#ifndef CYBSP_A0 +#define CYBSP_A0 (P10_0) +#endif /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#ifndef CYBSP_A1 +#define CYBSP_A1 (P10_1) +#endif /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#ifndef CYBSP_A2 +#define CYBSP_A2 (P10_2) +#endif /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#ifndef CYBSP_A3 +#define CYBSP_A3 (P10_3) +#endif /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#ifndef CYBSP_A4 +#define CYBSP_A4 (P10_4) +#endif /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#ifndef CYBSP_A5 +#define CYBSP_A5 (P10_5) +#endif /** Arduino D0 */ +#ifndef CYBSP_D0 #define CYBSP_D0 (P5_0) +#endif /** Arduino D1 */ +#ifndef CYBSP_D1 #define CYBSP_D1 (P5_1) +#endif /** Arduino D2 */ +#ifndef CYBSP_D2 #define CYBSP_D2 (P5_2) +#endif /** Arduino D3 */ +#ifndef CYBSP_D3 #define CYBSP_D3 (P5_3) +#endif /** Arduino D4 */ +#ifndef CYBSP_D4 #define CYBSP_D4 (P5_4) +#endif /** Arduino D5 */ +#ifndef CYBSP_D5 #define CYBSP_D5 (P5_5) +#endif /** Arduino D6 */ +#ifndef CYBSP_D6 #define CYBSP_D6 (P5_6) +#endif /** Arduino D7 */ +#ifndef CYBSP_D7 #define CYBSP_D7 (P0_2) +#endif /** Arduino D8 */ +#ifndef CYBSP_D8 #define CYBSP_D8 (P13_0) +#endif /** Arduino D9 */ +#ifndef CYBSP_D9 #define CYBSP_D9 (P13_1) +#endif /** Arduino D10 */ +#ifndef CYBSP_D10 #define CYBSP_D10 (P12_3) +#endif /** Arduino D11 */ +#ifndef CYBSP_D11 #define CYBSP_D11 (P12_0) +#endif /** Arduino D12 */ +#ifndef CYBSP_D12 #define CYBSP_D12 (P12_1) +#endif /** Arduino D13 */ +#ifndef CYBSP_D13 #define CYBSP_D13 (P12_2) +#endif /** Arduino D14 */ +#ifndef CYBSP_D14 #define CYBSP_D14 (P6_1) +#endif /** Arduino D15 */ +#ifndef CYBSP_D15 #define CYBSP_D15 (P6_0) +#endif /** \} group_bsp_pins_arduino */ @@ -276,45 +423,85 @@ extern "C" { */ /** Cypress J2 Header pin 1 */ +#ifndef CYBSP_J2_1 #define CYBSP_J2_1 (CYBSP_A0) +#endif /** Cypress J2 Header pin 2 */ +#ifndef CYBSP_J2_2 #define CYBSP_J2_2 (P9_0) +#endif /** Cypress J2 Header pin 3 */ +#ifndef CYBSP_J2_3 #define CYBSP_J2_3 (CYBSP_A1) +#endif /** Cypress J2 Header pin 4 */ +#ifndef CYBSP_J2_4 #define CYBSP_J2_4 (P9_1) +#endif /** Cypress J2 Header pin 5 */ +#ifndef CYBSP_J2_5 #define CYBSP_J2_5 (CYBSP_A2) +#endif /** Cypress J2 Header pin 6 */ +#ifndef CYBSP_J2_6 #define CYBSP_J2_6 (P9_2) +#endif /** Cypress J2 Header pin 7 */ +#ifndef CYBSP_J2_7 #define CYBSP_J2_7 (CYBSP_A3) +#endif /** Cypress J2 Header pin 8 */ +#ifndef CYBSP_J2_8 #define CYBSP_J2_8 (P9_3) +#endif /** Cypress J2 Header pin 9 */ +#ifndef CYBSP_J2_9 #define CYBSP_J2_9 (CYBSP_A4) +#endif /** Cypress J2 Header pin 10 */ +#ifndef CYBSP_J2_10 #define CYBSP_J2_10 (P9_4) +#endif /** Cypress J2 Header pin 11 */ +#ifndef CYBSP_J2_11 #define CYBSP_J2_11 (CYBSP_A5) +#endif /** Cypress J2 Header pin 12 */ +#ifndef CYBSP_J2_12 #define CYBSP_J2_12 (P9_5) +#endif /** Cypress J2 Header pin 13 */ +#ifndef CYBSP_J2_13 #define CYBSP_J2_13 (P10_6) +#endif /** Cypress J2 Header pin 14 */ +#ifndef CYBSP_J2_14 #define CYBSP_J2_14 (NC) +#endif /** Cypress J2 Header pin 15 */ +#ifndef CYBSP_J2_15 #define CYBSP_J2_15 (P6_2) +#endif /** Cypress J2 Header pin 16 */ +#ifndef CYBSP_J2_16 #define CYBSP_J2_16 (P9_6) +#endif /** Cypress J2 Header pin 17 */ +#ifndef CYBSP_J2_17 #define CYBSP_J2_17 (P6_3) +#endif /** Cypress J2 Header pin 18 */ +#ifndef CYBSP_J2_18 #define CYBSP_J2_18 (P9_7) +#endif /** Cypress J2 Header pin 19 */ +#ifndef CYBSP_J2_19 #define CYBSP_J2_19 (P13_6) +#endif /** Cypress J2 Header pin 20 */ +#ifndef CYBSP_J2_20 #define CYBSP_J2_20 (P13_7) +#endif /** \} group_bsp_pins_j2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index b16001ceba..7fbcad279d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld index 15f6a886e2..a987e9bd98 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf index 05bbaa0f44..fe9af7acbb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -112,13 +112,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 9811ac6b7b..8fd5a3d43d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,8 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* Copyright 2020 Arm Limited +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,10 +42,8 @@ ;* limitations under the License. ;******************************************************************************/ -#include "../../../partition/region_defs.h" - #if !defined(MBED_ROM_START) - #define MBED_ROM_START NS_CODE_START + #define MBED_ROM_START 0x10000000 #endif ;* MBED_APP_START is being used by the bootloader build script and @@ -58,7 +55,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE NS_CODE_SIZE + #define MBED_ROM_SIZE 0x001D0000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -70,19 +67,19 @@ #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START NS_DATA_START + #define MBED_RAM_START 0x08000000 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE NS_DATA_SIZE + #define MBED_RAM_SIZE 0x000EA000 #endif #if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE + #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Shared memory area between Non-secure and Secure -#define MBED_DATA_SHARED_SIZE NS_DATA_SHARED_SIZE +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -95,6 +92,9 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -136,7 +136,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -166,27 +166,15 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 ALIGN 4 EMPTY RAM_START+RAM_SIZE-MBED_BOOT_STACK_SIZE-MBED_DATA_SHARED_SIZE-ImageLimit(RW_IRAM1) - { + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY -MBED_BOOT_STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - } - - ; Stack area overflowed within RAM - ScatterAssert(ImageBase(ARM_LIB_STACK) + ImageLength(ARM_LIB_STACK) == RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE) - - ; Shared region - ARM_LIB_SHARED RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY MBED_DATA_SHARED_SIZE - { - } - - ; Shared area overflowed within RAM - ScatterAssert(ImageBase(ARM_LIB_SHARED) + ImageLength(ARM_LIB_SHARED) == RAM_START+RAM_SIZE) - - + } + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld index ade73b9451..6b29f396c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,8 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* Copyright 2020 Arm Limited +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,10 +40,8 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -#include "../../../partition/region_defs.h" - #if !defined(MBED_ROM_START) - #define MBED_ROM_START NS_CODE_START + #define MBED_ROM_START 0x10000000 #endif /* MBED_APP_START is being used by the bootloader build script and @@ -52,11 +49,11 @@ ENTRY(Reset_Handler) * is equal to MBED_ROM_START */ #if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START + #define MBED_APP_START MBED_ROM_START #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE NS_CODE_SIZE + #define MBED_ROM_SIZE 0x001D0000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -64,24 +61,26 @@ ENTRY(Reset_Handler) * is equal to MBED_ROM_SIZE */ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START NS_DATA_START + #define MBED_RAM_START 0x08000000 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE NS_DATA_SIZE + #define MBED_RAM_SIZE 0x000EA000 #endif -/* Size of the stack section in CM4 SRAM area */ #if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE + #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Shared memory area between Non-Secure and Secure */ -#define MBED_DATA_SHARED_SIZE NS_DATA_SHARED_SIZE +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard @@ -158,7 +157,7 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { /* Cortex-M4 flash vector table */ . = ALIGN(4); @@ -331,26 +330,20 @@ SECTIONS __end__ = .; end = __end__; KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - MBED_BOOT_STACK_SIZE - MBED_DATA_SHARED_SIZE; - . = ALIGN(4); - __StackLimit = .; + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; __HeapLimit = .; } > ram - __StackTop = (__StackLimit + MBED_BOOT_STACK_SIZE + 3) & 0xFFFFFFFC; + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; PROVIDE(__stack = __StackTop); - .shared __StackTop (NOLOAD): - { - __SharedStart = .; - . += MBED_DATA_SHARED_SIZE; - KEEP(*(.shared*)) - __SharedLimit = .; - } > ram + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - /* Check if Shared area overflowed within RAM */ - ASSERT(__SharedLimit == ORIGIN(ram) + LENGTH(ram), "Shared area overflowed within RAM") /* Used for the digital signature of the secure application and the Bootloader SDK application. * The size of the section depends on the required data size. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf index 22ac13a47f..397826cf1a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -85,10 +85,10 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h deleted file mode 100644 index b9d720c2e9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017-2018 Arm Limited - * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARM_LTD_DEVICE_CFG_H__ -#define __ARM_LTD_DEVICE_CFG_H__ - -#ifdef TFM_MULTI_CORE_MULTI_CLIENT_CALL -#define NUM_MAILBOX_QUEUE_SLOT 4 -#endif - -#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index 6a85b1da71..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -5,7 +5,7 @@ * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 2848f6cc4f..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -5,7 +5,7 @@ * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 535bd1ed8f..216bafabba 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -5,7 +5,7 @@ * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index b6f7ced0b9..23a452aeb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -5,7 +5,7 @@ * Clock configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 3ea923987d..1b0d5a4229 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -5,7 +5,7 @@ * Clock configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index ef281fd8fb..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -6,7 +6,7 @@ * design. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 39df796171..a5c7a71428 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -5,7 +5,7 @@ * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index c5f1df025b..f0d829ce64 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -5,7 +5,7 @@ * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 3eb7a6ac87..8c0f8aadb6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t SWDIO_config = +const cy_stc_gpio_pin_config_t SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t SWDIO_obj = + const cyhal_resource_inst_t SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = SWDIO_PORT_NUM, .channel_num = SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t SWCLK_config = +const cy_stc_gpio_pin_config_t SWCLK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t SWCLK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t SWCLK_obj = + const cyhal_resource_inst_t SWCLK_obj = { .type = CYHAL_RSC_GPIO, .block_num = SWCLK_PORT_NUM, .channel_num = SWCLK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,7 +307,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index d06861b5c4..89ac456a16 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -129,7 +129,7 @@ extern "C" { #define SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index ee3b282a70..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,7 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1342 +* QSPI Configurator: 2.0.0.1483 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 10a8af3d3e..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,7 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1342 +* QSPI Configurator: 2.0.0.1483 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index f57771f4ed..609e3bc919 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 6bbce9b165..68d50613d1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 6b995a703e..cf3349c542 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -70,7 +70,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -84,7 +84,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -92,7 +92,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -100,7 +100,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -108,7 +108,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -116,14 +116,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -280,7 +280,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -291,59 +291,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -353,7 +353,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -400,21 +400,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -461,7 +461,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -508,48 +508,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index ef001e8ad0..5089edcc28 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 33e1b31276..48a0967b23 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,5 +1,5 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 6df618b3a8..58e8231d08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index 45281b60a0..2151e21575 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,5 +1,5 @@ - + @@ -387,6 +387,10 @@ + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp_types.h index 831f42ab41..64377cbb67 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -41,7 +44,7 @@ extern "C" { *
    *
  • WCO uses external 32.768 kHz square wave input at P0[1]. Pin P0[0] should be left floating.
    • *
  • External clock is not supported since pin P0[5] is used as BT_HOST_WAKE signal
    • -*
+* * *
Peripheral Default HAL Settings:
* | Resource | Parameter | Value | Remarks | @@ -72,14 +75,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -96,12 +107,18 @@ extern "C" { */ /** LED 4; User LED1 (red) */ +#ifndef CYBSP_LED4 #define CYBSP_LED4 (P11_1) +#endif /** LED 4; User LED1 (red) */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED4) +#endif /** LED 4; User LED1 (red) */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -112,12 +129,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -128,60 +151,110 @@ extern "C" { */ /** Pin: WIFI SDIO D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif /** Pin: WIFI SDIO D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif /** Pin: WIFI SDIO D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif /** Pin: WIFI SDIO D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif /** Pin: WIFI SDIO CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif /** Pin: WIFI SDIO CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif /** Pin: WIFI ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif /** Pin: WIFI Host Wakeup */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P2_7) +#endif /** Pin: BT UART RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P3_0) +#endif /** Pin: BT UART TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P3_1) +#endif /** Pin: BT UART RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P9_2) +#endif /** Pin: BT UART CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P9_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P0_2) +#endif /** Pin: BT Host Wakeup */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P0_5) +#endif /** Pin: BT Device Wakeup */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P0_3) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P10_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P10_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_4) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_5) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index d9f249300a..70210e6765 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld index 5611270447..c4b744affc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index 68b322da34..d943f2eb76 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx5_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 4f8eeead26..f50a59217b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index f6fbe4ad7b..c7170ad30d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf index 07f3242517..f6e8888afa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx5_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index 5c04762fc0..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -5,7 +5,7 @@ * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 1edc10a968..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -5,7 +5,7 @@ * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 4bbd612ff0..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -5,7 +5,7 @@ * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 010a85c475..23a452aeb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -5,7 +5,7 @@ * Clock configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index a0dbefee1c..1b0d5a4229 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -5,7 +5,7 @@ * Clock configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 1ac635472c..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -6,7 +6,7 @@ * design. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 536c297f4d..a5c7a71428 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -5,7 +5,7 @@ * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 2a7e1f8dfe..24abac7fb6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -5,7 +5,7 @@ * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index cb4eabed5d..ccaccdf0ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_TX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_TX_PORT_NUM, .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 9315746a67..a54e4c7ad8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -417,7 +417,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 14d433859d..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 0ee62b1d55..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index d06d58bb2e..f8200c70ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 9753893b9f..02dd496f81 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -36,7 +36,7 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK @@ -47,8 +47,8 @@ void init_cycfg_routing(void); #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 6731557e3e..33dad6ec94 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -72,7 +72,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -86,7 +86,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -94,7 +94,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -102,7 +102,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -110,7 +110,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -118,7 +118,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, @@ -126,14 +126,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 5U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -256,14 +256,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -294,7 +294,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -305,59 +305,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -367,7 +367,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -414,21 +414,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -475,7 +475,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -522,48 +522,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index f6bce8c5ea..14e8674fbc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 5557ddecdd..909b041e9f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,4 +1,3 @@ set SMIF_BANKS { 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} } - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 43d6108110..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,13 +1,6 @@ - - + + @@ -121,12 +114,12 @@ + - @@ -223,12 +216,12 @@ + - @@ -325,12 +318,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 6df618b3a8..58e8231d08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h index b5b5ed2f76..28d7f9c6f3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,12 +101,18 @@ extern "C" { */ /** LED 4; User LED1 (red) */ +#ifndef CYBSP_LED4 #define CYBSP_LED4 (P13_7) +#endif /** LED 4; User LED1 (red) */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED4) +#endif /** LED 4; User LED1 (red) */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -106,12 +123,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -122,67 +145,123 @@ extern "C" { */ /** Pin: WIFI SDIO D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif /** Pin: WIFI SDIO D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif /** Pin: WIFI SDIO D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif /** Pin: WIFI SDIO D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif /** Pin: WIFI SDIO CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif /** Pin: WIFI SDIO CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif /** Pin: WIFI ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif /** Pin: WIFI Host Wakeup */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P0_4) +#endif /** Pin: BT UART RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P3_0) +#endif /** Pin: BT UART TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P3_1) +#endif /** Pin: BT UART RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P3_2) +#endif /** Pin: BT UART CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P3_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P3_4) +#endif /** Pin: BT Host Wakeup */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P4_0) +#endif /** Pin: BT Device Wakeup */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P3_5) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index f5a99814fe..11f1574b41 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index e6ab9018bf..4556c88ec4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index fea3f6ee6f..f99cad47c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 620923dcae..74bb3c8cbd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index ffbeca9b8e..72e55e3d19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 3080c25daa..dfb3fe373f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index 02ae0e3d07..a6b6f0024c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -5,7 +5,7 @@ * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 35e7743bc4..922d15d422 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -5,7 +5,7 @@ * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 4bbd612ff0..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -5,7 +5,7 @@ * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 1ac635472c..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -6,7 +6,7 @@ * design. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index bb0377b584..6a7bdfc535 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_ECO_IN_obj = + const cyhal_resource_inst_t CYBSP_ECO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_ECO_IN_PORT_NUM, .channel_num = CYBSP_ECO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = + const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_ECO_OUT_PORT_NUM, .channel_num = CYBSP_ECO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -187,7 +187,7 @@ const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWCLK_obj = + const cyhal_resource_inst_t CYBSP_SWCLK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWCLK_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 7012cd39d9..9deaeb62ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index b10821c976..82cd0ac6ff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 5e541bb902..6b41dd0a59 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index c8c86aca69..7195301d04 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 1182097db4..891fa6a171 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 3548daf234..22226cf4bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -67,7 +67,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -81,7 +81,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -89,7 +89,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -97,7 +97,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -105,7 +105,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -113,14 +113,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -233,14 +233,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -271,7 +271,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -282,59 +282,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -344,7 +344,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -391,21 +391,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -452,7 +452,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -499,48 +499,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index cfcee72bcb..4c3ce8cf50 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 61dc1091a6..34dd53fc32 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,4 +1,3 @@ set SMIF_BANKS { 0 {addr 0x18000000 size 0x1000000 psize 0x0000200 esize 0x0001000} } - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index a4c24aff9c..48e2d57e22 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h index 0e916ed080..9d42d4735c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,16 +101,26 @@ extern "C" { */ /** LED 3; User LED1 */ +#ifndef CYBSP_LED3 #define CYBSP_LED3 (P13_7) +#endif /** LED 4; User LED2 */ +#ifndef CYBSP_LED4 #define CYBSP_LED4 (P1_5) +#endif /** LED 3; User LED1 */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED3) +#endif /** LED 4; User LED2 */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED4) +#endif /** LED 3; User LED1 */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -109,12 +130,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -125,39 +152,69 @@ extern "C" { */ /** Pin: UART RX */ +#ifndef CYBSP_UART_RX #define CYBSP_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_UART_TX #define CYBSP_UART_TX (P5_1) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** \} group_bsp_pins_comm */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 1a7e1db522..1b90b6b4b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld index c37386fb06..5629824b5d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf index f48b2e9e1a..97d3a8c9a7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -112,13 +112,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index 77d3f7112a..37b32f07bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld index da76487fb8..7c8b13a05c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf index 076a8ff914..42a971cffd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -85,10 +85,10 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index f6d711f7d8..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -5,7 +5,7 @@ * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 524def4b08..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -5,7 +5,7 @@ * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100644 new mode 100755 index 58331948ac..216bafabba --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -5,7 +5,7 @@ * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index d8536e6416..41fe86f553 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -5,7 +5,7 @@ * Clock configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 72184ddcfa..1bbe7b6308 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -5,7 +5,7 @@ * Clock configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index a65f54b7c3..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -6,7 +6,7 @@ * design. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index d94841ef46..de38a7a37c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -5,7 +5,7 @@ * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index d80c807711..055eb022e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -5,7 +5,7 @@ * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 3089001684..cdb1f009af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, .channel_num = CYBSP_CSD_SLD4_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,7 +379,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 14c32a7a83..26fcc4765a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 02fef723d9..a6da7bbb57 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -25,7 +25,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -43,7 +43,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -61,7 +61,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -79,7 +79,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x21U, @@ -97,7 +97,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -115,7 +115,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x12U, @@ -133,7 +133,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -151,7 +151,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -169,7 +169,7 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -187,34 +187,34 @@ const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS512S_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ - .memSize = 0x2000000U, + .memSize = 0x4000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x0001000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x0000100U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FS512S_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -222,12 +222,12 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0 = /* The max time for the erase type-1 cycle-time in ms. */ .eraseTime = 725U, /* The max time for the chip-erase cycle-time in ms. */ - .chipEraseTime = 360000U, + .chipEraseTime = 720000U, /* The max time for the page-program cycle-time in us. */ .programTime = 2000U }; -const cy_stc_smif_mem_config_t S25FS256S_4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FS512S_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -245,11 +245,11 @@ const cy_stc_smif_mem_config_t S25FS256S_4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FS512S_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FS256S_4byteaddr_SlaveSlot_0 + &S25FS512S_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 70bd05c369..b6706c921a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -29,19 +29,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FS512S_SlaveSlot_0_writeStsRegQeCmd; -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS512S_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t S25FS256S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t S25FS512S_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index b662fd392d..d311d24949 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 159927dde1..801f4ba806 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -39,14 +39,14 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_9_pin_4_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_9_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 042227cd2a..275f0bda53 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -72,7 +72,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -86,7 +86,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -94,7 +94,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -102,7 +102,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -110,7 +110,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -118,14 +118,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -255,14 +255,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -293,7 +293,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -304,59 +304,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -366,7 +366,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -413,21 +413,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -474,7 +474,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -521,48 +521,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 6b1f627403..62088dd3a0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library: 1.3.1.1474 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 7171676b45..87a0e23244 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -5,7 +5,7 @@ 0 - S25FS256S-4byteaddr + S25FS512S true None 0x18000000 @@ -14,7 +14,7 @@ true false QUAD_SPI_DATA_0_3 - S25FS256S-4byteaddr + S25FS512S true diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c deleted file mode 100644 index 4e48631123..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c +++ /dev/null @@ -1,1509 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST.c -* -* \brief -* This file provides the source code to the API for the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "SDIO_HOST.h" -#include "cy_utils.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#ifdef CY_RTOS_AWARE - - #include "cyabs_rtos.h" - - #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) - static cy_semaphore_t sdio_transfer_finished_semaphore; - static bool sema_initialized = false; -#endif - -/* Backup struct used to store and restore non retention UDB registers */ -typedef struct -{ - uint32_t CY_SDIO_UDB_WRKMULT_CTL_0; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_1; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_2; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_3; -} stc_sdio_backup_regs_t; - -/*Globals Needed for DMA */ -/*DMA channel structures*/ -cy_stc_dma_channel_config_t respChannelConfig; -cy_stc_dma_channel_config_t cmdChannelConfig; -cy_stc_dma_channel_config_t writeChannelConfig; -cy_stc_dma_channel_config_t readChannelConfig; - -/*DMA Descriptor structures*/ -cy_stc_dma_descriptor_t respDesr; -cy_stc_dma_descriptor_t cmdDesr; -cy_stc_dma_descriptor_t readDesr0; -cy_stc_dma_descriptor_t readDesr1; -cy_stc_dma_descriptor_t writeDesr0; -cy_stc_dma_descriptor_t writeDesr1; - -/*Global structure used for data keeping*/ -stc_sdio_gInternalData_t gstcInternalData; - -/*Global CRC table*/ -static uint8_t crcTable[256]; - -/*Global values used for DMA interrupt*/ -static uint32_t yCountRemainder; -static uint32_t yCounts; - -/* Global value for card interrupt */ -static uint8_t pfnCardInt_count = 0; - -/*Global structure to store UDB registers */ -static stc_sdio_backup_regs_t regs; - -static uint32_t udb_initialized = 0; - -cy_stc_syspm_callback_params_t sdio_pm_callback_params; -cy_stc_syspm_callback_t sdio_pm_callback_handler; - -/* Deep Sleep Mode API Support */ -static void SDIO_SaveConfig(void); -static void SDIO_RestoreConfig(void); - -/******************************************************************************* -* Function Name: SDIO_DeepSleepCallback -****************************************************************************//** -* -* Callback executed during Deep Sleep entry/exit -* -* \param params -* Pointer to structure that holds callback parameters for this driver. -* -* \param mode -* The state transition mode that is currently happening. -* -* \note -* Saves/Restores SDIO UDB registers -* -* \return -* CY_SYSPM_SUCCESS if the transition was successful, otherwise CY_SYSPM_FAIL -* -*******************************************************************************/ -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) -{ - CY_UNUSED_PARAMETER(params); - cy_en_syspm_status_t status = CY_SYSPM_FAIL; - - switch (mode) - { - case CY_SYSPM_CHECK_READY: - case CY_SYSPM_CHECK_FAIL: - status = CY_SYSPM_SUCCESS; - break; - - case CY_SYSPM_BEFORE_TRANSITION: - SDIO_SaveConfig(); - status = CY_SYSPM_SUCCESS; - break; - - case CY_SYSPM_AFTER_TRANSITION: - SDIO_RestoreConfig(); - status = CY_SYSPM_SUCCESS; - break; - - default: - break; - } - - return status; -} - -/******************************************************************************* -* Function Name: SDIO_Init -****************************************************************************//** -* -* Initializes the SDIO hardware -* -* \param pfuCb -* Pointer to structure that holds pointers to callback function -* see \ref stc_sdio_irq_cb_t. -* -* \note -* Sets SD Clock Frequency to 400 kHz -*******************************************************************************/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) -{ - if ( !udb_initialized ) - { - udb_initialized = 1; - SDIO_Host_Config_TriggerMuxes(); - SDIO_Host_Config_UDBs(); - } - - /*Set Number of Blocks to 1 initially, this will be updated later*/ - SDIO_SetNumBlocks(1); - - /*Enable SDIO ISR*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - - /*Enable the Status Reg to generate an interrupt*/ - SDIO_STATUS_AUX_CTL |= (0x10); - - /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ - /*First clear priority of all*/ - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; - - /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; - - /*Setup callback for card interrupt*/ - gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; - - /*Setup the DMA channels*/ - SDIO_SetupDMA(); - - /*Initialize CRC*/ - SDIO_Crc7Init(); - - /*Enable all the bit counters*/ - SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - - /*Set block byte count to 64, this will be changed later */ - SDIO_SetBlockSize(64); - - /*Set the read and write FIFOs to use the half full status*/ - (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; - (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; - - /*Set clock to 400k, and enable it*/ - SDIO_SetSdClkFrequency(400000); - SDIO_EnableIntClock(); - SDIO_EnableSdClk(); -} - - -/******************************************************************************* -* Function Name: SDIO_SendCommand -****************************************************************************//** -* -* Send an SDIO command, don't wait for it to finish. -* -* \param pstcCmdConfig -* Command configuration structure. See \ref stc_sdio_cmd_config_t. -* -*******************************************************************************/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) -{ - /*buffer to hold command data*/ - static uint8_t u8cmdBuf[6]; - - /*Populate buffer*/ - /*Element 0 is the Most Significant Byte*/ - u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; - u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); - u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); - u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); - u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); - - /*calculate the CRC of above data*/ - u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); - /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ - u8cmdBuf[5] = u8cmdBuf[5] << 1; - /*Add on the end bit*/ - u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; - - /*Load the first byte into A0*/ - SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; - - /*If a response is expected setup DMA to receive the response*/ - if (pstcCmdConfig->bResponseRequired == true) - { - /*Clear the flag in hardware that says skip response*/ - SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; - - /*Set the destination address*/ - respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); - - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); - } - else - { - /*Set the skip flag*/ - SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; - } - - /*Setup the Command DMA*/ - /*Set the source address*/ - cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); - - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); -} - - -/******************************************************************************* -* Function Name: SDIO_GetResponse -****************************************************************************//** -* -* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks -* for index errors, CRC errors, and end bit errors. -* -* \param bCmdIndexCheck -* If True check for index errors -* -* \param bCmdCrcCheck -* If True check for CRC errors -* -* \param u8cmdIdx -* Command index, used for checking the index error -* -* \param pu32Response -* location to store 32 bit response -* -* \param pu8ResponseBuf -* buffer that holds the 6 bytes of response data -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) -{ - /*Function return*/ - en_sdio_result_t enRet = Error; - /*variable to hold temporary CRC*/ - uint8_t u8TmpCrc; - /*temporary response*/ - uint32_t u32TmpResponse; - - /*Zero out the pu32Response*/ - *pu32Response = 0; - - /*Check if the CRC needs to be checked*/ - if (bCmdCrcCheck) - { - /*Calculate the CRC*/ - u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); - - /*Shift calculated CRC up by one bit to match bit position of CRC*/ - u8TmpCrc = u8TmpCrc << 1; - - /*Compare calculated CRC with received CRC*/ - if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) - { - enRet |= CommandCrcError; - } - } - - /*Check if the index needs to be checked*/ - if (bCmdIndexCheck) - { - /*The index resides in the lower 6 bits of the 1st byte of the response*/ - if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) - { - enRet |= CommandIdxError; - } - } - - /*Check the end bit*/ - if (!(pu8ResponseBuf[5] & 0x01)) - { - enRet |= CommandEndError; - } - - if (enRet == Error) - { - /*If we get here then there were no errors with the command populate the response*/ - u32TmpResponse = pu8ResponseBuf[1]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[2]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[3]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[4]; - - *pu32Response = u32TmpResponse; - - enRet = Ok; - } - - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_InitDataTransfer -****************************************************************************//** -* -* Configure the data channel for a data transfer. For a write this doesn't start -* the write, that must be done separately after the response is received. -* -* \param pstcDataConfig -* Data configuration structure. See \ref stc_sdio_data_config_t -* -* -*******************************************************************************/ -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) -{ - /*hold size of entire transfer*/ - uint32_t dataSize; - - /*calculate how many bytes are going to be sent*/ - dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; - - /*Set the block size and number of blocks*/ - SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); - SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); - - /*If we are reading data setup the DMA to receive read data*/ - if (pstcDataConfig->bRead == true) - { - /*First disable the write channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - - /*Clear any pending interrupts in the DMA*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - - /*setup the destination addresses*/ - readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); - readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ - readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - - /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the - DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility - that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA - will be SW triggered when hardware indicates all bytes have been received. - This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to - be at least 3 bytes bigger than the data size. - - Since the X loop is setup to 4, the maximum number of Y loop is 256 so one - descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. - Since we don't know the maximum number of bytes to read only two descriptors will - be used. If more than 2048 bytes need to be read then and interrupt will be enabled - The descriptor that is not currently running will be updated in the ISR to receive - more data. - - So there are three conditions to check: - 1) Are we sending less than or equal to 1024 bytes if so use one descriptor - 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors - 3) Greater than 2048, use two descriptors and the ISR - */ - - if (dataSize <= 1024) - { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - /*Setup descriptor 0 to point to nothing and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (dataSize <=2048) - { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ - - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - - /*Setup descriptor 0 to point to descriptor 1*/ - readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to nothing and disable */ - readDesr1.nextPtr = 0; - - /*Don't disable after first descriptor*/ - readDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ - readDesr1.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else /*dataSize must be greater than 2048*/ - { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ - yCounts = (dataSize / 1024); - - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); - - /*Setup the Y Ctrl for both descriptors*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - /*Setup descriptor 0 to point to descriptor 1*/ - readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ - readDesr1.nextPtr = (uint32_t)(&readDesr0); - - /*Don't disable the channel on completion of descriptor*/ - readDesr0.ctl &= ~0x01000000; - readDesr1.ctl &= ~0x01000000; - - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ - yCounts -= 2; - - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the read*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; - } - - /*Otherwise it is a write*/ - else - { - /*First disable the Read channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Clear any pending interrupts in the DMA*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - - /*setup the SRC addresses*/ - writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); - writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - - - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ - writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); - writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); - - if (dataSize <= 1024) - { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - /*Setup descriptor 0 to point to nothing and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else if (dataSize <=2048) - { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ - - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - - /*Setup descriptor 0 to point to descriptor 1*/ - writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to nothing and disable */ - writeDesr1.nextPtr = 0; - - /*Don't disable after first descriptor*/ - writeDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ - writeDesr1.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else /*dataSize must be greater than 2048*/ - { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ - yCounts = (dataSize / 1024); - - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); - - /*Setup the Y Ctrl for both descriptors*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - /*Setup descriptor 0 to point to descriptor 1*/ - writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ - writeDesr1.nextPtr = (uint32_t)(&writeDesr0); - - /*Don't disable the channel on completion of descriptor*/ - writeDesr0.ctl &= ~0x01000000; - writeDesr1.ctl &= ~0x01000000; - - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ - yCounts -= 2; - - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); - } -} - - -/******************************************************************************* -* Function Name: SDIO_SendCommandAndWait -****************************************************************************//** -* -* This function sends a command on the command channel and waits for that -* command to finish before returning. If a Command 53 is issued this function -* will handle all of the data transfer and wait to return until it is done. -* -* \param pstcCmd -* Pointer command configuration structure see \ref stc_sdio_cmd_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) -{ - /* Store the command and data configurations*/ - stc_sdio_cmd_config_t stcCmdConfig; - stc_sdio_data_config_t stcDataConfig; - - uint32_t u32CmdTimeout = 0; - - /*Returns from various function calls*/ - en_sdio_result_t enRet = Error; - en_sdio_result_t enRetTmp = Ok; - - /* Hold value of if these checks are needed */ - uint8_t bCmdIndexCheck; - uint8_t bCmdCrcCheck; - static uint8_t u8responseBuf[6]; - - /* Clear statuses */ - gstcInternalData.stcEvents.u8CmdComplete = 0; - gstcInternalData.stcEvents.u8TransComplete = 0; - gstcInternalData.stcEvents.u8CRCError = 0; - - /* Setup the command configuration */ - stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; - stcCmdConfig.u32Argument = pstcCmd->u32Arg; - -#ifdef CY_RTOS_AWARE - - cy_rslt_t result; - - /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in - * interrupt thread. - */ - if(!sema_initialized) - { - cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 ); - sema_initialized = true; - } -#else - - /* Variable used for holding timeout value */ - uint32_t u32Timeout = 0; -#endif - - /*Determine the type of response and if we need to do any checks*/ - /*Command 0 and 8 have no response, so don't wait for one*/ - if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) - { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = false; - stcCmdConfig.pu8ResponseBuf = NULL; - } - - /*Command 5's response doesn't have a CRC or index, so don't check*/ - else if (pstcCmd->u32CmdIdx == 5) - { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; - } - /*Otherwise check everything*/ - else - { - bCmdIndexCheck = true; - bCmdCrcCheck = true; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; - } - - /*Check if the command is 53, if it is then setup the data transfer*/ - if (pstcCmd->u32CmdIdx == 53) - { - /*Set the number of blocks in the global struct*/ - stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; - /*Set the size of the data transfer*/ - stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; - /*Set the direction are we reading or writing*/ - stcDataConfig.bRead = pstcCmd->bRead; - /*Set the pointer for the data*/ - stcDataConfig.pu8Data = pstcCmd->pu8Data; - - /*Get the data Transfer Ready*/ - SDIO_InitDataTransfer(&stcDataConfig); - - /*Set bit saying this was a CMD_53*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; - } - - /*Send the command*/ - SDIO_SendCommand(&stcCmdConfig); - - /*Wait for the command to finish*/ - do - { - u32CmdTimeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); - - } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); - - - if (u32CmdTimeout == SDIO_CMD_TIMEOUT) - { - enRet |= CMDTimeout; - } - else /*CMD Passed*/ - { - /*If a response is expected check it*/ - if (stcCmdConfig.bResponseRequired == true) - { - enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); - if (enRetTmp != Ok) - { - enRet |= enRetTmp; - } - else /*Response good*/ - { - /*if it was command 53, check the response to ensure there was no error*/ - if ((pstcCmd->u32CmdIdx) == 53) - { - /*Make sure none of the error bits are set*/ - if (*(pstcCmd->pu32Response) & 0x0000cf00) - { - enRet |= ResponseFlagError; - } - else /*CMD53 Response good*/ - { - /*If it was command 53 and it was a write enable the write*/ - if (pstcCmd->bRead == false && enRet == Error) - { - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the write*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - /*Enable the channel*/ - Cy_SysLib_DelayCycles(35); - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; - } - - #ifdef CY_RTOS_AWARE - /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released - * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in - * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases - * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero - * and exit. Or timeout occurs - */ - result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); - - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - if (result != CY_RSLT_SUCCESS) - #else - /* Wait for the transfer to finish */ - do - { - u32Timeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); - - if (u32Timeout == SDIO_DAT_TIMEOUT) - #endif - { - enRet |= DataTimeout; - } - - /* if it was a read it is possible there is still extra data hanging out, trigger the - DMA again. This can result in extra data being transfered so the read buffer should be - 3 bytes bigger than needed*/ - if (pstcCmd->bRead == true) - { - Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); - } - - if (enRetTmp == DataCrcError) - { - enRet |= DataCrcError; - } - }/*CMD53 response good*/ - }/*Not a CMD53*/ - } /*Response Good*/ - } /*No Response Required, thus no CMD53*/ - } /*CMD Passed*/ - -#ifndef CY_RTOS_AWARE - u32Timeout = 0; -#endif - - /*If there were no errors then indicate transfer was okay*/ - if (enRet == Error) - { - enRet = Ok; - } - - /*reset CmdTimeout value*/ - u32CmdTimeout = 0; - - /*Always Reset on exit to clean up*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - /*No longer a CMD_53*/ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); - SDIO_Reset(); - - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_CheckForEvent -****************************************************************************//** -* -* Checks to see if a specific event has occurred such a command complete or -* transfer complete. -* -* \param enEventType -* The type of event to check for. See \ref en_sdio_event_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) -{ - en_sdio_result_t enRet = Error; - - /*Disable Interrupts while modifying the global*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - - /*Switch the event to check*/ - switch ( enEventType ) - { - /*If the command is done clear the flag*/ - case SdCmdEventCmdDone: - if (gstcInternalData.stcEvents.u8CmdComplete > 0) - { - gstcInternalData.stcEvents.u8CmdComplete = 0; - enRet = Ok; - } - break; - - /*If the transfer is done check for CRC Error and clear the flag*/ - case SdCmdEventTransferDone: - if (gstcInternalData.stcEvents.u8TransComplete > 0) - { - gstcInternalData.stcEvents.u8TransComplete = 0; - enRet = Ok; - } - /*Check for CRC error and set flags*/ - if (gstcInternalData.stcEvents.u8CRCError > 0) - { - enRet = DataCrcError; - gstcInternalData.stcEvents.u8CRCError = 0; - } - break; - } - - /*Re-enable Interrupts*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_CalculateCrc7 -****************************************************************************//** -* -* Calculate the 7 bit CRC for the command channel -* -* \param pu8Data -* Data to calculate CRC on -* -* \param u8Size -* Number of bytes to calculate CRC on -* -* \return -* CRC -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) -{ - uint8_t data; - uint8_t remainder = 0; - uint32_t byte; - - for(byte = 0; byte < u8Size; ++byte) - { - data = pu8Data[byte] ^ remainder; - remainder = crcTable[data] ^ (remainder << 8); - } - - return (remainder>>1); -} - - -/******************************************************************************* -* Function Name: SDIO_Crc7Init -****************************************************************************//** -* -* Initialize 7-bit CRC Table -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ -void SDIO_Crc7Init(void) -{ - uint8_t remainder; - uint8_t bit; - uint32_t dividend; - - for(dividend = 0; dividend < 256; ++dividend) - { - remainder = dividend; - - for(bit = 8; bit > 0; --bit) - { - if (remainder & SDIO_CRC_UPPER_BIT) - { - remainder = (remainder << 1) ^ SDIO_CRC7_POLY; - } - else - { - remainder = (remainder << 1); - } - } - - crcTable[dividend] = (remainder); - } -} - - -/******************************************************************************* -* Function Name: SDIO_SetBlockSize -****************************************************************************//** -* -* Sets the size of each block -* -* \param u8ByteCount -* Size of the block -* -*******************************************************************************/ -void SDIO_SetBlockSize(uint8_t u8ByteCount) -{ - SDIO_BYTE_COUNT_REG = u8ByteCount; -} - - -/******************************************************************************* -* Function Name: SDIO_SetNumBlocks -****************************************************************************//** -* -* Sets the number of blocks to send -* -* \param u8BlockCount -* Size of the block -* -*******************************************************************************/ -void SDIO_SetNumBlocks(uint8_t u8BlockCount) -{ - SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; - SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; - /*The one is used so that we can do 256 bytes*/ - SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; - SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; -} - - -/******************************************************************************* -* Function Name: SDIO_EnableIntClock -****************************************************************************//** -* -* Enable Internal clock for the block -* -*******************************************************************************/ -void SDIO_EnableIntClock(void) -{ - SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); -} - - -/******************************************************************************* -* Function Name: SDIO_DisableIntClock -****************************************************************************//** -* -* Enable Disable clock for the block -* -*******************************************************************************/ -void SDIO_DisableIntClock(void) -{ - SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); -} - - -/******************************************************************************* -* Function Name: SDIO_EnableSdClk -****************************************************************************//** -* -* Enable SD Clock out to pin -* -*******************************************************************************/ -void SDIO_EnableSdClk(void) -{ - SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; -} - - -/******************************************************************************* -* Function Name: SDIO_DisableSdClk -****************************************************************************//** -* -* Disable SD Clock out to the pin -* -*******************************************************************************/ -void SDIO_DisableSdClk(void) -{ - SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; -} - - -/******************************************************************************* -* Function Name: SDIO_SetSdClkFrequency -****************************************************************************//** -* -* Sets the frequency of the SD Clock -* -* \param u32SdClkFreqHz -* Frequency of SD Clock in Hz. -* -* \note -* Only an integer divider is used, so the desired frequency may not be meet -*******************************************************************************/ -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) -{ - uint16_t u16Div; - /* - * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB - * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required - * SDIO operating frequency. - */ - u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); - Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); -} - - -/******************************************************************************* -* Function Name: SDIO_SetupDMA -****************************************************************************//** -* -* Configures the DMA for the SDIO block -* -*******************************************************************************/ -void SDIO_SetupDMA(void) -{ - /*Set the number of bytes to send*/ - SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); - /*Set the destination address*/ - SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; - - /*Initialize descriptor for cmd channel*/ - Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); - - /*Set flag to disable descriptor when done*/ - cmdDesr.ctl |= 0x01000000; - - /*Configure channel*/ - /*CMD channel can be preempted, and has lower priority*/ - cmdChannelConfig.descriptor = &cmdDesr; - cmdChannelConfig.preemptable = 1; - cmdChannelConfig.priority = 1; - cmdChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); - - /*Set the number of bytes to receive*/ - SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; - /*Set the source address*/ - SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; - - /*Initialize descriptor for response channel*/ - Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); - - /*Set flag to disable descriptor when done*/ - respDesr.ctl |= 0x01000000; - - /*Configure channel*/ - /*response channel can be preempted, and has lower priority*/ - respChannelConfig.descriptor = &respDesr; - respChannelConfig.preemptable = 1; - respChannelConfig.priority = 1; - respChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); - - /*Set the destination address*/ - SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; - - /*Initialize descriptor for write channel*/ - Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - - /*Configure channel*/ - /*write channel cannot be preempted, and has highest priority*/ - writeChannelConfig.descriptor = &writeDesr0; - writeChannelConfig.preemptable = 0; - writeChannelConfig.priority = 0; - writeChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); - - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); - - /*Set the source address*/ - SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; - /*Initialize descriptor for read channel*/ - Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - - /*Configure channel*/ - /*read channel cannot be preempted, and has highest priority*/ - readChannelConfig.descriptor = &readDesr0; - readChannelConfig.preemptable = 0; - readChannelConfig.priority = 0; - readChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); - - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); -} - - -/******************************************************************************* -* Function Name: SDIO_Reset -****************************************************************************//** -* -* Reset the SDIO interface -* -*******************************************************************************/ -void SDIO_Reset(void) -{ - /*Control register is in pulse mode, so this just pulses the reset*/ - SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); -} - - -/******************************************************************************* -* Function Name: SDIO_EnableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ -void SDIO_EnableChipInt(void) -{ - SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; -} - - -/******************************************************************************* -* Function Name: SDIO_DisableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ -void SDIO_DisableChipInt(void) -{ - SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; -} - - -/******************************************************************************* -* Function Name: SDIO_IRQ -****************************************************************************//** -* -* SDIO interrupt, checks for events, and calls callbacks -* -*******************************************************************************/ -void SDIO_IRQ(void) -{ - uint8_t u8Status; - - /* First read the status register */ - u8Status = SDIO_STATUS_REG; - - /* Check card interrupt */ - if (u8Status & SDIO_STS_CARD_INT ) - { - pfnCardInt_count++; - } - - /* Execute card interrupt callback if neccesary */ - if (0 != pfnCardInt_count) - { - if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) - { - gstcInternalData.pstcCallBacks.pfnCardIntCb(); - } - pfnCardInt_count--; - } - - /* If the command is complete set the flag */ - if (u8Status & SDIO_STS_CMD_DONE) - { - gstcInternalData.stcEvents.u8CmdComplete++; - } - - /* Check if a write is complete */ - if (u8Status & SDIO_STS_WRITE_DONE ) - { - - /* Clear the Write flag and CMD53 flag */ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); - - /* Check if the CRC status return was bad */ - if (u8Status & SDIO_STS_CRC_ERR) - { - /* CRC was bad, set the flag */ - gstcInternalData.stcEvents.u8CRCError++; - } - - /* Set the done flag */ - - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else - gstcInternalData.stcEvents.u8TransComplete++; - #endif - } - - /* Check if a read is complete */ - if (u8Status & SDIO_STS_READ_DONE) - { - /* Clear the read flag */ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); - - /* Check the CRC */ - if (u8Status & SDIO_STS_CRC_ERR) - { - /* CRC was bad, set the flag */ - gstcInternalData.stcEvents.u8CRCError++; - } - /* Okay we're done so set the done flag */ - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else - gstcInternalData.stcEvents.u8TransComplete++; - #endif - } - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); -} - - -/******************************************************************************* -* Function Name: SDIO_READ_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Read interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ -void SDIO_READ_DMA_IRQ(void) -{ - /*Shouldn't have to change anything unless it is the last descriptor*/ - - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) - { - /*We need to increment the destination address every time*/ - readDesr1.dst += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - } - - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) - { - /*We need to increment the destination address everytime*/ - readDesr0.dst += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - } - - /*Clear the interrupt*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - /*decrement y counts*/ - yCounts--; -} - -/******************************************************************************* -* Function Name: SDIO_WRITE_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Write interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ -void SDIO_WRITE_DMA_IRQ(void) -{ - /*We shouldn't have to change anything unless it is the last descriptor*/ - - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) - { - /*We also need to increment the destination address every-time*/ - writeDesr1.src += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - } - - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) - { - /*We also need to increment the destination address*/ - writeDesr0.src += 2048; - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - } - - /*Clear the interrupt*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - yCounts--; -} - -/******************************************************************************* -* Function Name: SDIO_Free -****************************************************************************//** -* -* Frees any system resources that were allocated by the SDIO driver. -* -*******************************************************************************/ -void SDIO_Free(void) -{ -#ifdef CY_RTOS_AWARE - cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); -#endif -} - -/******************************************************************************* -* Function Name: SDIO_SaveConfig -******************************************************************************** -* -* Saves the user configuration of the SDIO UDB non-retention registers. Call the -* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function. -* -*******************************************************************************/ -static void SDIO_SaveConfig(void) -{ - regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0]; - regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1]; - regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2]; - regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3]; -} - - -/******************************************************************************* -* Function Name: SDIO_RestoreConfig -******************************************************************************** -* -* Restores the user configuration of the SDIO UDB non-retention registers. Call -* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function. -* -*******************************************************************************/ -static void SDIO_RestoreConfig(void) -{ - UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0; - UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1; - UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2; - UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3; -} - -#if defined(__cplusplus) -} -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h deleted file mode 100644 index 06edc747bc..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h +++ /dev/null @@ -1,396 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST.h -* -* \brief -* This file provides types definition, constants and function definition for -* the SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \defgroup group_bsp_pin_state Pin States -* \defgroup group_bsp_pins Pin Mappings -* \defgroup group_bsp_macros Macros -* \defgroup group_bsp_functions Functions -* -* \defgroup group_udb_sdio UDB_SDIO -* \{ -* SDIO - Secure Digital Input Output is a standard for communicating with various - external devices such as Wifi and bluetooth devices. -*

-* The driver is currently designed to only support communication with certain -* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general -* SDIO card, or even and SD card. It is only intended to be used by the WiFi -* driver for communication. -*

-* This is not intended to be used as a general purpose API. -* -* \section group_udb_sdio_section_configuration_considerations Configuration Considerations -* Features: -* * Always Four Wire Mode -* * Supports Card Interrupt -* * Uses DMA for command and data transfer -* -* \defgroup group_udb_sdio_macros Macros -* \defgroup group_udb_sdio_functions Functions -* \defgroup group_udb_sdio_data_structures Data Structures -*/ - -#if !defined(CY_SDIO_H) -#define CY_SDIO_H - -#include "SDIO_HOST_cfg.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - -/*************************************** -* API Constants -***************************************/ - -/** -* \addtogroup group_udb_sdio_macros -* \{ -*/ - -#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ -#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ -#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ -#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ - -/*! -\defgroup group_sdio_cmd_constants Constants for the command channel -*/ -/* @{*/ -#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ -#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ -#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/ -#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/ -/*@} group_sdio_cmd_constants */ - -/*! -\defgroup group_sdio_ctrl_reg SDIO control register bits -*/ -/* @{*/ -#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ -#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ -#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ -#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ -#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ -#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ -#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ -#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ -/*@} group_sdio_ctrl_reg */ - -/*! -\defgroup group_sdio_status_reg SDIO status register bits -*/ -/* @{*/ -#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ -#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ -#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ -#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ -#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ -#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ -#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ -/*@} group_sdio_status_reg */ - -/*! -\defgroup group_sdio_crc Constants for 7bit CRC for command -*/ -/* @{*/ -#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ -#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ -/*@} group_sdio_crc */ - -/** \} group_udb_sdio_macros */ - - -/*************************************** -* Type Definitions -***************************************/ - -/** -* \addtogroup group_udb_sdio_data_structures -* \{ -*/ - -/** -* Create a type for the card interrupt call back -*/ -typedef void (* sdio_card_int_cb_t)(void); - -/** -* \brief This enum is used when checking for specific events -*/ -typedef enum en_sdio_event -{ - SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ - SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ - -}en_sdio_event_t; - -/** -* \brief Used to indicate the result of a function -*/ -typedef enum en_sdio_result -{ - Ok = 0x00, /**< No error*/ - Error = 0x01, /**< Non-specific error code*/ - CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ - CommandIdxError = 0x04, /**< The index for the command didn't match*/ - CommandEndError = 0x08, /**< There was an end bit error on the command*/ - DataCrcError = 0x10, /**< There was a data CRC Error*/ - CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ - DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ - ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ - -} en_sdio_result_t; - -/** -* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function -*/ -typedef struct stc_sdcmd_event_flag -{ - uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ - uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ - uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ - -}stc_sdio_event_flag_t; - -/** -* \brief Holds pointers to callback functions -*/ -typedef struct stc_sdio_irq_cb -{ - sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ -}stc_sdio_irq_cb_t; - -/** -* \brief Global structure used to hold data from interrupt and other functions -*/ -typedef struct stc_sdio_gInternalData -{ - stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ - stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ -}stc_sdio_gInternalData_t; - -/** -* \brief structure used for configuring command -*/ -typedef struct stc_sdio_cmd_config -{ - uint8_t u8CmdIndex; /**< Command index*/ - uint32_t u32Argument; /**< The argument of command */ - uint8_t bResponseRequired; /**< TRUE: A Response is required*/ - uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ - -}stc_sdio_cmd_config_t; - -/** -* \brief structure used for the data channel -*/ -typedef struct stc_sdio_data_config -{ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockSize; /**< Block size*/ - uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - -}stc_sdio_data_config_t; - -/** -* \brief structure used for configuring command and data -*/ -typedef struct stc_sdio_cmd -{ - uint32_t u32CmdIdx; /**< Command index*/ - uint32_t u32Arg; /**< The argument of command*/ - uint32_t *pu32Response; /**< Pointer to location to store response*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockCnt; /**< Number of blocks to send*/ - uint16_t u16BlockSize; /**< Block size*/ -}stc_sdio_cmd_t; - -/** \} group_udb_sdio_data_structures */ - -/*************************************** -* Function Prototypes -***************************************/ - -/** -* \addtogroup group_udb_sdio_functions -* \{ -*/ - -/* Main functions*/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); -void SDIO_EnableIntClock(void); -void SDIO_DisableIntClock(void); -void SDIO_EnableSdClk(void); -void SDIO_DisableSdClk(void); -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); -void SDIO_Reset(void); -void SDIO_EnableChipInt(void); -void SDIO_DisableChipInt(void); -void SDIO_Free(void); - -/*Low Level Functions*/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); -void SDIO_SetBlockSize(uint8_t u8ByteCount); -void SDIO_SetNumBlocks(uint8_t u8BlockCount); - -/*DMA setup function*/ -void SDIO_SetupDMA(void); - -/*Interrupt Function*/ -void SDIO_IRQ(void); -void SDIO_READ_DMA_IRQ(void); -void SDIO_WRITE_DMA_IRQ(void); - -void SDIO_Crc7Init(void); - -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); - -/** \endcond */ - -/** \} group_udb_sdio_functions */ - - -/*************************************** -* Hardware Registers -***************************************/ - -/** \cond INTERNAL */ - -#define SDIO_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) - -#define SDIO_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) - -#define SDIO_STATUS_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_REG) - -#define SDIO_STATUS_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_REG) - -#define SDIO_STATUS_INT_MSK (* (reg8*) \ -SDIO_HOST_bSDIO_StatusReg__MASK_REG) - -#define SDIO_STATUS_AUX_CTL (* (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG) - -#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) - -#define SDIO_CMD_COMMAND_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F0_REG) - -#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__A0_REG) - -#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F0_REG) - -#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F1_REG) - -#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F1_REG) - -#define SDIO_DAT_WRITE_REG (* (reg16 *) \ -SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) - -#define SDIO_DAT_WRITE_PTR ( (reg16 *) \ -SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) - -#define SDIO_DAT_READ_REG (* (reg16 *) \ -SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) - -#define SDIO_DAT_READ_PTR ( (reg16 *) \ -SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) - -#define SDIO_BYTE_COUNT_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) - -/** \endcond */ - -#if defined(__cplusplus) -} -#endif - -#endif /* (CY_SDIO_H) */ - -/** \} group_udb_sdio */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c deleted file mode 100644 index e89c7c74b5..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ /dev/null @@ -1,1037 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.c -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "SDIO_HOST_cfg.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/***************************CMD DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_16CYC, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1L, - .dstXincrement = 0L, - .xCount = 5UL, - .srcYincrement = 0L, - .dstYincrement = 0L, - .yCount = 1UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Read DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0L, - .dstXincrement = 2L, - .xCount = 10UL, - .srcYincrement = 0L, - .dstYincrement = 10L, - .yCount = 2UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Resp DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0L, - .dstXincrement = 1L, - .xCount = 6UL, - .srcYincrement = 0L, - .dstYincrement = 0L, - .yCount = 1UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Write DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_4CYC, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 2L, - .dstXincrement = 0L, - .xCount = 10UL, - .srcYincrement = 10L, - .dstYincrement = 0L, - .yCount = 2UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - - - -/***************UDB Config code *****************/ - -#define CY_CFG_BASE_ADDR_COUNT 12u - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) - #define CYPACKED - #define CYPACKED_ATTR __attribute__ ((packed)) - #define CY_CFG_UNUSED __attribute__ ((unused)) - - -#elif defined(__ICCARM__) - #include - - #define CYPACKED __packed - #define CYPACKED_ATTR - #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") - - -#else - #error Unsupported toolchain -#endif - - -#ifndef CYCODE - #define CYCODE -#endif -#ifndef CYFAR - #define CYFAR -#endif - - -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) -{ - (void)memset(s, 0, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} - -CYPACKED typedef struct -{ - uint8 offset; - uint8 value; -} CYPACKED_ATTR cy_cfg_addrvalue_t; - - -/******************************************************************************* -* Function Name: cfg_write_bytes32 -******************************************************************************** -* Summary: -* This function is used for setting up the chip configuration areas that -* contain relatively sparse data. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ - -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) -{ - /* For 32-bit little-endian architectures */ - uint32 i, j = 0u; - for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) - { - uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; - baseAddr &= 0xFFFFFF00u; - while (count != 0u) - { - CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); - j++; - count--; - } - } -} - -static const uint32 CYCODE cy_cfg_addr_table[] = -{ - 0x40340002u, /* Base address: 0x40340000 Count: 2 */ - 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ - 0x40340301u, /* Base address: 0x40340300 Count: 1 */ - 0x40340405u, /* Base address: 0x40340400 Count: 5 */ - 0x4034205Cu, /* Base address: 0x40342000 Count: 92 */ - 0x40342238u, /* Base address: 0x40342200 Count: 56 */ - 0x4034242Cu, /* Base address: 0x40342400 Count: 44 */ - 0x4034262Eu, /* Base address: 0x40342600 Count: 46 */ - 0x40342837u, /* Base address: 0x40342800 Count: 55 */ - 0x40342A29u, /* Base address: 0x40342A00 Count: 41 */ - 0x40347104u, /* Base address: 0x40347100 Count: 4 */ - 0x40347804u, /* Base address: 0x40347800 Count: 4 */ -}; - -static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = -{ -{0x00u, 0xFFu}, - {0x09u, 0x01u}, - {0x09u, 0x01u}, - {0x0Du, 0x02u}, - {0x10u, 0x10u}, - {0x14u, 0x88u}, - {0x18u, 0x10u}, - {0x1Cu, 0x88u}, - {0x20u, 0x10u}, - {0x24u, 0x88u}, - {0x28u, 0x10u}, - {0x2Cu, 0x88u}, - {0x19u, 0x40u}, - {0x10u, 0x07u}, - {0x18u, 0x47u}, - {0x24u, 0x03u}, - {0x28u, 0x0Fu}, - {0x2Cu, 0x2Fu}, - {0x00u, 0x01u}, - {0x0Eu, 0x0Eu}, - {0x10u, 0x08u}, - {0x18u, 0x01u}, - {0x1Au, 0x08u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x22u, 0x01u}, - {0x28u, 0x01u}, - {0x2Au, 0x04u}, - {0x2Eu, 0x01u}, - {0x30u, 0x0Fu}, - {0x3Cu, 0x02u}, - {0x40u, 0x63u}, - {0x41u, 0x04u}, - {0x42u, 0x10u}, - {0x44u, 0x02u}, - {0x45u, 0x0Fu}, - {0x46u, 0xECu}, - {0x47u, 0xB0u}, - {0x48u, 0x2Du}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x02u}, - {0x4Fu, 0x0Cu}, - {0x50u, 0x08u}, - {0x51u, 0x10u}, - {0x5Cu, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x65u, 0x08u}, - {0x68u, 0xC0u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x71u, 0x10u}, - {0x72u, 0x50u}, - {0x73u, 0xA8u}, - {0x81u, 0x01u}, - {0x83u, 0x02u}, - {0x85u, 0x02u}, - {0x89u, 0x02u}, - {0x8Du, 0x02u}, - {0x91u, 0x30u}, - {0x93u, 0x04u}, - {0x95u, 0x06u}, - {0x97u, 0x38u}, - {0x99u, 0x20u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x10u}, - {0x9Du, 0x06u}, - {0x9Fu, 0x38u}, - {0xA3u, 0x02u}, - {0xA5u, 0x02u}, - {0xA6u, 0x01u}, - {0xABu, 0x01u}, - {0xB1u, 0x01u}, - {0xB2u, 0x01u}, - {0xB3u, 0x20u}, - {0xB5u, 0x10u}, - {0xB7u, 0x0Eu}, - {0xBDu, 0x80u}, - {0xBEu, 0x04u}, - {0xBFu, 0x14u}, - {0xC0u, 0x54u}, - {0xC1u, 0x06u}, - {0xC2u, 0x32u}, - {0xC6u, 0xF0u}, - {0xC7u, 0x0Eu}, - {0xC8u, 0x18u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCFu, 0x2Fu}, - {0xD0u, 0x08u}, - {0xD1u, 0x10u}, - {0xDCu, 0x04u}, - {0xDDu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xDFu, 0x04u}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE6u, 0x08u}, - {0xE7u, 0x03u}, - {0xE8u, 0x08u}, - {0xEAu, 0x18u}, - {0xEBu, 0x03u}, - {0xF0u, 0x58u}, - {0xF1u, 0xECu}, - {0x00u, 0x18u}, - {0x01u, 0x15u}, - {0x03u, 0x20u}, - {0x04u, 0x43u}, - {0x06u, 0x34u}, - {0x07u, 0x35u}, - {0x08u, 0x40u}, - {0x0Cu, 0x5Au}, - {0x0Eu, 0x25u}, - {0x0Fu, 0x4Au}, - {0x11u, 0x20u}, - {0x13u, 0x15u}, - {0x14u, 0x40u}, - {0x15u, 0x40u}, - {0x17u, 0x0Au}, - {0x18u, 0x20u}, - {0x19u, 0x10u}, - {0x1Bu, 0x25u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x0Au}, - {0x1Fu, 0x40u}, - {0x20u, 0x20u}, - {0x21u, 0x0Cu}, - {0x23u, 0x03u}, - {0x24u, 0x40u}, - {0x2Au, 0x20u}, - {0x2Cu, 0x45u}, - {0x2Eu, 0x3Au}, - {0x30u, 0x40u}, - {0x32u, 0x0Eu}, - {0x33u, 0x70u}, - {0x34u, 0x01u}, - {0x35u, 0x0Cu}, - {0x36u, 0x31u}, - {0x37u, 0x03u}, - {0x3Au, 0xA8u}, - {0x3Cu, 0xA8u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x54u}, - {0x40u, 0x42u}, - {0x41u, 0x05u}, - {0x45u, 0x20u}, - {0x46u, 0x06u}, - {0x48u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Du, 0xA0u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x66u, 0x40u}, - {0x67u, 0x40u}, - {0x68u, 0x10u}, - {0x69u, 0x50u}, - {0x02u, 0x60u}, - {0x08u, 0x87u}, - {0x0Au, 0x78u}, - {0x0Eu, 0x08u}, - {0x12u, 0x21u}, - {0x14u, 0x04u}, - {0x18u, 0xB9u}, - {0x1Au, 0x06u}, - {0x1Cu, 0x89u}, - {0x1Eu, 0x72u}, - {0x20u, 0x04u}, - {0x24u, 0x8Eu}, - {0x26u, 0x51u}, - {0x2Au, 0x04u}, - {0x2Eu, 0x01u}, - {0x30u, 0x80u}, - {0x34u, 0x7Fu}, - {0x3Au, 0x20u}, - {0x3Cu, 0x20u}, - {0x3Eu, 0x01u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x44u, 0x01u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x77u}, - {0x5Cu, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x80u, 0x40u}, - {0x84u, 0x8Eu}, - {0x86u, 0x71u}, - {0x88u, 0x40u}, - {0x8Eu, 0x21u}, - {0x90u, 0x40u}, - {0x92u, 0x02u}, - {0x96u, 0x18u}, - {0x98u, 0x03u}, - {0x9Au, 0x04u}, - {0x9Cu, 0xCCu}, - {0x9Eu, 0x33u}, - {0xA0u, 0x08u}, - {0xA4u, 0x40u}, - {0xA8u, 0x46u}, - {0xAAu, 0xB1u}, - {0xACu, 0x10u}, - {0xAEu, 0x08u}, - {0xB2u, 0xF8u}, - {0xB4u, 0x07u}, - {0xB6u, 0x07u}, - {0xBAu, 0xA8u}, - {0xBCu, 0xA8u}, - {0xC0u, 0x43u}, - {0xC1u, 0x02u}, - {0xC4u, 0x01u}, - {0xC5u, 0x40u}, - {0xC6u, 0xB0u}, - {0xC8u, 0x0Au}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x00u, 0x40u}, - {0x01u, 0x14u}, - {0x03u, 0x20u}, - {0x04u, 0x33u}, - {0x05u, 0x3Cu}, - {0x06u, 0x44u}, - {0x08u, 0x97u}, - {0x09u, 0x3Cu}, - {0x0Au, 0x48u}, - {0x0Du, 0x01u}, - {0x11u, 0x03u}, - {0x12u, 0x91u}, - {0x15u, 0x03u}, - {0x16u, 0x08u}, - {0x1Bu, 0x03u}, - {0x1Cu, 0x13u}, - {0x1Eu, 0xECu}, - {0x1Fu, 0x03u}, - {0x20u, 0xADu}, - {0x21u, 0x04u}, - {0x22u, 0x52u}, - {0x27u, 0x2Cu}, - {0x29u, 0x02u}, - {0x2Eu, 0x12u}, - {0x2Fu, 0x04u}, - {0x30u, 0x07u}, - {0x31u, 0x18u}, - {0x33u, 0x07u}, - {0x34u, 0xF8u}, - {0x35u, 0x20u}, - {0x39u, 0x02u}, - {0x3Au, 0x22u}, - {0x3Cu, 0x22u}, - {0x3Fu, 0x15u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x01u, 0x20u}, - {0x0Bu, 0x40u}, - {0x0Du, 0x10u}, - {0x11u, 0x32u}, - {0x13u, 0x09u}, - {0x15u, 0x0Au}, - {0x17u, 0x31u}, - {0x23u, 0x34u}, - {0x29u, 0x33u}, - {0x2Bu, 0x08u}, - {0x2Du, 0x0Cu}, - {0x31u, 0x0Cu}, - {0x33u, 0x01u}, - {0x35u, 0x02u}, - {0x37u, 0x70u}, - {0x39u, 0x02u}, - {0x3Fu, 0x55u}, - {0x40u, 0x16u}, - {0x41u, 0x02u}, - {0x44u, 0x04u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x76u}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0xE8u, 0x63u}, - {0xECu, 0x53u}, - {0xF0u, 0x54u}, - {0xF4u, 0x01u}, - {0x00u, 0x01u}, - {0x10u, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x01u}, -}; - - - -CYPACKED typedef struct -{ -void *address; -uint16 size; -} CYPACKED_ATTR cfg_memset_t; - - -CYPACKED typedef struct -{ - void *dest; - const void *src; - size_t size; -} CYPACKED_ATTR cfg_memcpy_t; - -static const cfg_memset_t CYCODE cfg_memset_list[] = -{ - /* address, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, -}; - -/* UDB_UDBPAIR5_UDBSNG1 Address: CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_UDBSNG1_VAL[] = { - 0x08u, 0x00u, 0x00u, 0x00u, 0x42u, 0x00u, 0x2Du, 0x00u, 0x08u, 0x24u, 0x00u, 0x00u, 0x22u, 0x24u, 0x45u, 0x00u, - 0x00u, 0x10u, 0x10u, 0x08u, 0x00u, 0x70u, 0x00u, 0x83u, 0x08u, 0x24u, 0x00u, 0x00u, 0x00u, 0x4Eu, 0x00u, 0xB0u, - 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x8Fu, 0x3Cu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, - 0x00u, 0xC0u, 0x00u, 0x1Fu, 0x60u, 0x00u, 0x1Fu, 0x20u, 0x80u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x10u, 0x41u, - 0x46u, 0x02u, 0x00u, 0x00u, 0x05u, 0x00u, 0x04u, 0x0Bu, 0x14u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = { - 0x08u, 0x0Au, 0x00u, 0xD0u, 0x02u, 0xB9u, 0x00u, 0x42u, 0x2Bu, 0x02u, 0x00u, 0x00u, 0x2Bu, 0x00u, 0x54u, 0x80u, - 0x2Au, 0x00u, 0x01u, 0x20u, 0x40u, 0x33u, 0x00u, 0xCCu, 0x04u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0xA0u, - 0x2Au, 0x00u, 0x00u, 0x00u, 0x01u, 0x8Au, 0x2Au, 0x71u, 0x20u, 0x7Bu, 0x00u, 0x80u, 0x00u, 0x04u, 0x00u, 0x00u, - 0x19u, 0xF8u, 0x07u, 0xF8u, 0x00u, 0x00u, 0x61u, 0x07u, 0x8Au, 0x80u, 0x00u, 0x0Au, 0x00u, 0x0Au, 0x45u, 0x40u, - 0x52u, 0x06u, 0x00u, 0x00u, 0x04u, 0x4Cu, 0x0Eu, 0x00u, 0x07u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, - 0x40u, 0x03u, 0x00u, 0x10u}; - -/* UDB_UDBPAIR4_UDBSNG1 Address: CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x00u, 0x19u, 0x00u, 0x12u, 0x00u, 0x2Du, 0x00u, 0x04u, 0x00u, 0x00u, 0x11u, - 0x02u, 0x08u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x05u, 0x00u, 0x03u, 0x10u, 0x08u, - 0x15u, 0x00u, 0x2Au, 0x10u, 0x00u, 0x00u, 0x04u, 0x00u, 0x0Eu, 0x0Fu, 0x31u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x07u, 0x00u, 0x10u, 0x3Fu, 0x00u, 0x3Fu, 0x0Cu, 0x00u, 0x00u, 0xA0u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x04u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x06u, 0x40u, 0xB0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR3_UDBSNG0 Address: CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG0_VAL[] = { - 0x3Cu, 0x00u, 0x00u, 0xC0u, 0x00u, 0x80u, 0x10u, 0x40u, 0x0Cu, 0x80u, 0x60u, 0x40u, 0x02u, 0x10u, 0x00u, 0x25u, - 0x04u, 0x80u, 0x08u, 0x40u, 0x00u, 0x19u, 0x10u, 0x22u, 0x04u, 0x00u, 0x0Bu, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x80u, - 0x10u, 0x00u, 0x00u, 0x24u, 0x00u, 0x40u, 0x00u, 0x80u, 0x7Cu, 0x25u, 0x00u, 0x1Au, 0x00u, 0x08u, 0x10u, 0x80u, - 0x01u, 0xC0u, 0x02u, 0x00u, 0x70u, 0x07u, 0x0Cu, 0x38u, 0x00u, 0x00u, 0x80u, 0x82u, 0x00u, 0xA2u, 0x04u, 0x00u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xDEu, 0x40u, 0x4Bu, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR2_UDBSNG1 Address: CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x80u, 0x03u, 0x00u, 0xC9u, 0x00u, 0x12u, 0x00u, 0x00u, 0x00u, 0x01u, 0x70u, 0x01u, 0x00u, 0x80u, - 0x40u, 0x00u, 0x00u, 0x40u, 0x40u, 0xB3u, 0xAAu, 0x4Cu, 0xEAu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x40u, - 0x40u, 0xB1u, 0xAAu, 0x04u, 0x43u, 0x00u, 0x00u, 0x01u, 0x4Cu, 0x05u, 0x00u, 0xBAu, 0x00u, 0x20u, 0x40u, 0x80u, - 0x03u, 0x7Fu, 0xC0u, 0x80u, 0x0Cu, 0x7Fu, 0x30u, 0x00u, 0xA2u, 0x00u, 0x08u, 0x22u, 0x08u, 0x22u, 0x51u, 0x04u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x05u, 0xB0u, 0x40u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = { - 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF5u, 0x7Fu, 0xF3u, 0x11u, - 0xF3u, 0x11u, 0xFFu, 0xF2u, 0xFFu, 0x2Fu, 0xFFu, 0xFFu, 0x00u, 0x11u, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF7u, 0x5Fu, 0xFFu, 0x2Fu, 0x10u, 0x22u, 0x62u, 0x00u, 0x34u, - 0x2Fu, 0x62u, 0x73u, 0x00u, 0x11u, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x0Fu, 0x0Fu, 0x27u, - 0x20u, 0x22u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x11u, 0x40u, 0x1Du, 0x11u, 0x00u, 0xDDu, 0x11u, 0x10u, 0x10u, 0x11u, 0x00u, 0xD1u, 0x63u, 0x03u, 0x01u, - 0x13u, 0x37u, 0x00u, 0x13u, 0x11u, 0x00u, 0x13u, 0x16u, 0x11u, 0x11u, 0x16u, 0x19u, 0x11u, 0x01u, 0x11u, 0x11u, - 0x19u, 0x11u, 0x11u, 0x91u, 0x41u, 0x11u, 0x21u, 0x11u, 0x16u, 0x11u, 0x11u, 0x13u, 0x81u, 0x11u, 0x11u, 0x11u}; - -/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = { - 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x42u, 0x36u, - 0x26u, 0x33u, 0x35u, 0xF5u, 0xF0u, 0x54u, 0x14u, 0x62u, 0x5Fu, 0x0Fu, 0x04u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x24u, 0x45u, 0x7Fu, 0x50u, 0x26u, 0x64u, 0xFFu, 0x3Fu, 0x32u, 0x42u, 0xF3u, 0x32u, - 0x3Fu, 0x7Fu, 0x37u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x02u, 0x05u, - 0xF6u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x13u, 0xF0u, 0x10u, 0x14u, 0x00u, 0x01u, 0x01u, 0x10u, 0x0Du, 0x63u, 0x00u, 0x70u, 0x10u, 0x08u, 0x30u, - 0x13u, 0x11u, 0x30u, 0x10u, 0x50u, 0x30u, 0x1Fu, 0xC1u, 0x33u, 0x10u, 0x0Fu, 0x01u, 0x31u, 0x0Du, 0x1Cu, 0x25u, - 0x11u, 0x01u, 0x12u, 0xFBu, 0x02u, 0x12u, 0x15u, 0x1Cu, 0x11u, 0x11u, 0x11u, 0x15u, 0x11u, 0x61u, 0x16u, 0x11u}; - -/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = { - 0x06u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, 0x33u, 0x35u, 0x44u, - 0x77u, 0x57u, 0xF2u, 0xFFu, 0xF4u, 0xFFu, 0x40u, 0xFFu, 0x32u, 0x63u, 0xFFu, 0xFFu, 0x3Fu, 0x5Fu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x34u, 0x13u, 0x46u, 0x56u, 0x35u, 0x41u, 0x40u, 0x57u, 0x67u, 0x55u, - 0x3Fu, 0x63u, 0xF6u, 0xFFu, 0x4Fu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x00u, 0x00u, - 0x40u, 0x22u, 0x00u, 0xF0u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x11u, 0xF3u, 0x10u, 0x12u, 0x02u, 0x96u, 0x01u, 0x00u, 0x74u, 0xD1u, 0x00u, 0xF7u, 0x03u, 0x03u, 0x16u, - 0x1Fu, 0x31u, 0x10u, 0x00u, 0x03u, 0x10u, 0x41u, 0x35u, 0x10u, 0x16u, 0x0Fu, 0x76u, 0x11u, 0xB0u, 0xD1u, 0xDFu, - 0x09u, 0x00u, 0x0Fu, 0xFBu, 0x01u, 0x11u, 0x17u, 0x11u, 0x11u, 0x15u, 0xD5u, 0x1Du, 0x27u, 0x15u, 0x1Fu, 0x11u}; - -/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x41u, 0x53u, 0x15u, - 0x45u, 0x11u, 0xF4u, 0xF3u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0x33u, 0x63u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x31u, 0x02u, 0x14u, 0x56u, 0xF1u, 0x77u, 0x77u, 0x37u, 0xF0u, 0x56u, 0x73u, 0x45u, - 0x33u, 0x63u, 0xFFu, 0x03u, 0x15u, 0xF2u, 0xF2u, 0xF2u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xB0u, 0x00u, 0xF0u, 0x17u, 0x1Fu, 0x02u, 0x1Fu, 0x60u, 0xA3u, 0xF4u, 0x15u, 0xA0u, 0xF1u, 0x0Fu, 0x00u, 0x31u, - 0x0Fu, 0xF3u, 0x3Au, 0x20u, 0x51u, 0x3Au, 0x13u, 0xF3u, 0xC0u, 0x10u, 0x4Au, 0x11u, 0x20u, 0x10u, 0x01u, 0xF1u, - 0x0Fu, 0x00u, 0x0Fu, 0xFFu, 0x41u, 0x11u, 0x41u, 0x4Du, 0x11u, 0x71u, 0x11u, 0x1Fu, 0xFCu, 0x11u, 0x1Fu, 0x1Cu}; - -/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = { - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, 0xF4u, 0x55u, 0x4Fu, - 0xF3u, 0x5Fu, 0x55u, 0x27u, 0x31u, 0x63u, 0x71u, 0x61u, 0x3Fu, 0x63u, 0x0Fu, 0x5Fu, 0xFFu, 0xFFu, 0xFFu, 0x12u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x64u, 0x31u, 0x70u, 0x77u, 0xF6u, 0x2Fu, 0x1Fu, 0x25u, 0x4Fu, 0xF7u, 0x3Fu, - 0x32u, 0x63u, 0x3Fu, 0x75u, 0xF4u, 0x1Fu, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, - 0x04u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x70u, 0x30u, 0x26u, 0x14u, 0x2Fu, 0x0Cu, 0xA5u, 0x10u, 0x18u, 0x11u, 0x0Fu, 0xF0u, 0xF7u, 0x3Fu, 0x00u, 0x11u, - 0x0Fu, 0xFFu, 0xF8u, 0x16u, 0xF7u, 0x1Fu, 0x10u, 0x11u, 0xF4u, 0x13u, 0xFFu, 0x67u, 0x13u, 0x15u, 0x07u, 0xF1u, - 0x3Fu, 0xCDu, 0x2Fu, 0x4Fu, 0xF6u, 0x12u, 0x12u, 0x11u, 0x11u, 0x19u, 0x11u, 0x21u, 0xFFu, 0x11u, 0x1Fu, 0x11u}; - -/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x32u, 0xF3u, 0xF4u, - 0xFFu, 0x45u, 0xFFu, 0x43u, 0x12u, 0x35u, 0x33u, 0xFFu, 0x3Fu, 0x5Fu, 0x34u, 0xF0u, 0xFFu, 0x2Fu, 0xFFu, 0x12u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0xF3u, 0xFFu, 0x44u, 0x1Fu, 0xF2u, 0x04u, 0x01u, 0x2Fu, - 0x30u, 0x2Fu, 0x3Fu, 0xFFu, 0xF0u, 0x10u, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xF5u, 0x17u, 0x11u, 0x16u, 0x11u, 0x2Cu, 0x1Fu, 0x17u, 0x9Fu, 0x41u, 0x6Fu, 0xF4u, 0x1Fu, 0x33u, 0xCCu, 0x11u, - 0x63u, 0x1Fu, 0x29u, 0x71u, 0xF5u, 0x2Fu, 0x73u, 0x13u, 0xF1u, 0x13u, 0x11u, 0x1Au, 0x11u, 0x31u, 0x6Fu, 0x11u, - 0x11u, 0x1Fu, 0x11u, 0x1Au, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI0_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI2_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI3_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x15u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI4_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI5_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI6_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x09u, 0x1Fu, - 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0x03u, 0xFFu, 0xF0u, 0xFFu, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x01u, 0x11u, - 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x10u, 0xD1u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI7_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x04u, 0x12u, 0x10u, 0x0Du, 0x1Fu, 0x1Fu, 0x10u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0xFFu, 0x0Fu, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x0Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x21u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI8_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x20u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI9_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI10_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI11_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), BS_UDB_UDBPAIR5_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), BS_UDB_UDBPAIR4_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), BS_UDB_UDBPAIR3_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), BS_UDB_UDBPAIR2_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, -}; - -void SDIO_Host_Config_TriggerMuxes(void) -{ - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB10, TRIG14_OUT_TR_GROUP0_INPUT49, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT6, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB14, TRIG14_OUT_TR_GROUP0_INPUT48, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB9, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); -} - -void SDIO_Host_Config_UDBs(void) -{ - - size_t i; - - /* Power on the UDB array */ - CY_SET_REG32(0x402101F0u, 0x05FA0003u); - - /* Zero out critical memory blocks before beginning configuration */ - for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - { - const cfg_memset_t *ms = &cfg_memset_list[i]; - CYMEMZERO(ms->address, ms->size); - } - - /* Copy device configuration data into registers */ - for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) - { - const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; - CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); - } - - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - - /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ - CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); - - /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C404Cu); - - /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x044C4C44u); - - /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x004C444Cu); - - /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C44u); - - /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x4C4C404Cu); - - /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x004C4C4Cu); - - /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x0C8C8C8Cu); - - /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x004C404Cu); - - /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x004C444Cu); - - /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - - /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x4C4C0400u); - - /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - - /* Enable UDB array and digital routing */ - CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); - } - -#if defined(__cplusplus) -} -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h deleted file mode 100644 index 60ab730b5d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ /dev/null @@ -1,869 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.h -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#if !defined(CY_SDIO_CFG_H) -#define CY_SDIO_CFG_H - -#include - -#include "cy_dma.h" -#include "cy_sysclk.h" -#include "cy_trigmux.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u -#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u -#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u -#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu -#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u - -#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u -#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u - -#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu -#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu - -#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu -#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu - -#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu -#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu -#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu -#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu -#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu -#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu -#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu -#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu - -#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u -#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u -#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u -#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u - -#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u -#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u -#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u -#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u -#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u -#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u - - -#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u -#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u -#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u -#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u -#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u -#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u - - -#define CYDEV_UDB_DSI0_BASE 0x40346000u -#define CYDEV_UDB_DSI1_BASE 0x40346080u -#define CYDEV_UDB_DSI2_BASE 0x40346100u -#define CYDEV_UDB_DSI3_BASE 0x40346180u -#define CYDEV_UDB_DSI4_BASE 0x40346200u -#define CYDEV_UDB_DSI5_BASE 0x40346280u -#define CYDEV_UDB_DSI6_BASE 0x40346300u -#define CYDEV_UDB_DSI7_BASE 0x40346380u -#define CYDEV_UDB_DSI8_BASE 0x40346400u -#define CYDEV_UDB_DSI9_BASE 0x40346480u -#define CYDEV_UDB_DSI10_BASE 0x40346500u -#define CYDEV_UDB_DSI11_BASE 0x40346580u - -#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u - -/*************Defines for UDBs from Creator*****************************/ -/***********These come for cyfitter.h**********************************/ - -/* SDIO_HOST_bSDIO */ -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x40340008u -#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x40340108u -#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x40342240u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x40342244u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x40342248u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x4034224Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x40342250u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x40342264u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x40342268u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x4034226Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x40342270u -#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x40340208u -#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x4034225Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x40342260u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341724u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341724u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341724u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341724u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341824u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341824u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341824u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341824u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341724u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340324u -#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341724u -#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340324u -#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340424u -#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340424u -#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341824u -#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x403428DCu -#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x403428E0u -#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x403428D4u -#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x403428D8u -#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341624u -#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341824u -#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340424u -#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340424u -#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x403428DCu -#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x403428E0u -#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x403428D4u -#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x403428D8u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340324u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340324u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341624u -#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340000u -#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340100u -#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342040u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342044u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342048u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034204Cu -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342050u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342064u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342068u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034206Cu -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342070u -#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340200u -#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034205Cu -#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342060u -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034192Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034172Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034032Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034172Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034032Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034182Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x40342ADCu -#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x40342AE0u -#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x40342AD4u -#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x40342AD8u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034182Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x40342ADCu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x40342AE0u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x40342AD4u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x40342AD8u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034192Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034032Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034032Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034162Cu -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u -#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u -#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u -#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0 -#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u -#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1 -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341818u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341818u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341818u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341818u -#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u -#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2 -#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u -#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3 -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341818u -#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u -#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4 -#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u -#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6 -#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u -#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7 -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340318u -#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341718u -#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340318u -#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu -#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340418u -#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340418u -#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341818u -#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x4034265Cu -#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x40342660u -#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x40342654u -#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x40342658u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340010u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340110u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342440u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342444u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342448u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034244Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342450u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342464u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342468u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034246Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342470u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340210u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__MSK_DP_AUX_CTL_REG 0x40340410u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__PER_DP_AUX_CTL_REG 0x40340410u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034245Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342460u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340014u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340114u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403424C0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403424C4u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403424C8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403424CCu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403424D0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403424E4u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403424E8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403424ECu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403424F0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340214u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341028u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341128u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341228u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341328u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341428u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341528u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340028u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341028u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341128u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340128u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341228u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341328u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342A40u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342A44u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342A48u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x40342A4Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342A50u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342A64u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342A68u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x40342A6Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342A70u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340228u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341428u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341528u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__MSK_DP_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__PER_DP_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x4034002Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x4034102Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x4034112Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x4034012Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x4034122Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x4034132Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x4034192Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x40342AC0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x40342AC4u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x40342AC8u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x40342ACCu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x40342AD0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x40342AE4u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x40342AE8u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x40342AECu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x40342AF0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x4034022Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x4034142Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x4034152Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x40342ADCu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x40342AE0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340020u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340120u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342840u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342844u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342848u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x4034284Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342850u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342864u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342868u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x4034286Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342870u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340220u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_A0_REG 0x40341024u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_A1_REG 0x40341124u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_D0_REG 0x40341224u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_D1_REG 0x40341324u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_DP_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_F0_REG 0x40341424u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_F1_REG 0x40341524u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x40340024u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x40341024u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x40341124u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x40340124u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x40341224u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x40341324u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x403428C0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x403428C4u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x403428C8u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x403428CCu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x403428D0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x403428E4u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x403428E8u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x403428ECu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x403428F0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x40340224u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x40341424u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x40341524u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x40340424u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x40340424u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x403428DCu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x403428E0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340018u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340118u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342640u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342644u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342648u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034264Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342650u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342664u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342668u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034266Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342670u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340218u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340418u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340418u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034265Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342660u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x4034001Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x4034011Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403426C0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403426C4u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403426C8u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403426CCu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403426D0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403426E4u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403426E8u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403426ECu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403426F0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x4034021Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x40340004u -#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x40340104u -#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403420C0u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403420C4u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403420C8u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403420CCu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403420D0u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403420E4u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403420E8u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403420ECu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403420F0u -#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x40340204u -#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403420D4u -#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403420D8u -#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u -#define SDIO_HOST_bSDIO_StatusReg__0__POS 0 -#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u -#define SDIO_HOST_bSDIO_StatusReg__1__POS 1 -#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341618u -#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u -#define SDIO_HOST_bSDIO_StatusReg__2__POS 2 -#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u -#define SDIO_HOST_bSDIO_StatusReg__3__POS 3 -#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341818u -#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341618u -#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u -#define SDIO_HOST_bSDIO_StatusReg__6__POS 6 -#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu -#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341818u -#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340418u -#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340418u -#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x4034265Cu -#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x40342660u -#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x40342654u -#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x40342658u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340318u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340318u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341618u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x4034000Cu -#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x4034010Cu -#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x403422C0u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x403422C4u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x403422C8u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x403422CCu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x403422D0u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x403422E4u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x403422E8u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x403422ECu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x403422F0u -#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x4034020Cu -#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x4034040Cu -#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x4034040Cu -#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x403422DCu -#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x403422E0u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x4034030Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x4034170Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x4034030Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x4034040Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x4034040Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x403422DCu -#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x403422E0u -#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x403422D4u -#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x403422D8u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340310u -#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341710u -#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340310u -#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340410u -#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340410u -#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x4034245Cu -#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x40342460u -#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x40342454u -#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x40342458u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341610u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341610u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341810u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340410u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340410u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x4034245Cu -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x40342460u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x40342454u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x40342458u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340310u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340310u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341610u -#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0 -#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u -#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1 -#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u -#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1 -#define SDIO_HOST_Internal_Clock__DIV_IDX 0 -#define SDIO_HOST_Internal_Clock__DIV_NUM 0 -#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT -#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1 -#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u -#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3 -#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u -#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3 -#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0 -#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u -#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0 -#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u -#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0 -#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1 -#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u -#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1 -#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u -#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 - - -/***************************CMD DMA***************************************/ -#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) -#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) -#define SDIO_HOST_CMD_DMA_HW (DW0) -#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_CMD_DMA_PRIORITY (1u) -#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) -#define SDIO_HOST_CMD_DMA_BUFFERABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; - -/***************************Read DMA***************************************/ -#define SDIO_HOST_Read_DMA_DW_BLOCK (1u) -#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) -#define SDIO_HOST_Read_DMA_HW (DW1) -#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Read_DMA_PRIORITY (0u) -#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Read_DMA_PREEMPTABLE (false) -#define SDIO_HOST_Read_DMA_BUFFERABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; - -/***************************Resp DMA***************************************/ -#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) -#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) -#define SDIO_HOST_Resp_DMA_HW (DW0) -#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Resp_DMA_PRIORITY (1u) -#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) -#define SDIO_HOST_Resp_DMA_BUFFERABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; - -/***************************Write DMA***************************************/ -#define SDIO_HOST_Write_DMA_DW_BLOCK (1u) -#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) -#define SDIO_HOST_Write_DMA_HW (DW1) -#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Write_DMA_PRIORITY (0u) -#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Write_DMA_PREEMPTABLE (false) -#define SDIO_HOST_Write_DMA_BUFFERABLE (true) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; - -/***************************SDIO Clock**************************************/ -/** The peripheral clock divider number */ -#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)SDIO_HOST_Internal_Clock__DIV_NUM) -/** The peripheral clock divider type */ -#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE) - -/*Function for configuring TriggerMuxes*/ -void SDIO_Host_Config_TriggerMuxes(void); - -/*Function for configuring UDBs*/ -void SDIO_Host_Config_UDBs(void); - -/* SDIO_HOST_Read_Int */ -#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Read_Int__INTC_NUMBER 69u -#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Read_Int_INTC_NUMBER 69u - -/* SDIO_HOST_sdio_int */ -#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_sdio_int__INTC_NUMBER 122u -#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_sdio_int_INTC_NUMBER 122u - -/* SDIO_HOST_Write_Int */ -#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Write_Int__INTC_NUMBER 67u -#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Write_Int_INTC_NUMBER 67u - -#if defined(__cplusplus) -} -#endif - -#endif /* !defined(CY_SDIO_CFG_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h index ca88869e21..eeff0219d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,16 +101,26 @@ extern "C" { */ /** LED 8; User LED1 */ +#ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_LED9 #define CYBSP_LED9 (P11_0) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) +#endif /** LED 9; User LED2 */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -109,12 +130,18 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P1_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -125,79 +152,147 @@ extern "C" { */ /** Pin: CYBSP_WIFI_SDIO_D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P12_1) +#endif /** Pin: CYBSP_WIFI_SDIO_D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P12_2) +#endif /** Pin: CYBSP_WIFI_SDIO_D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P12_3) +#endif /** Pin: CYBSP_WIFI_SDIO_D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P12_4) +#endif /** Pin: CYBSP_WIFI_SDIO_CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P12_5) +#endif /** Pin: CYBSP_WIFI_SDIO_CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P12_0) +#endif /** Pin: CYBSP_WIFI_WL_REG_ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P6_2) +#endif /** Pin: CYBSP_WIFI_HOST_WAKE */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P6_0) +#endif /** Pin: CYBSP_BT_UART_RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P8_0) +#endif /** Pin: CYBSP_BT_UART_TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P8_1) +#endif /** Pin: CYBSP_BT_UART_RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P8_2) +#endif /** Pin: CYBSP_BT_UART_CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P8_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P6_3) +#endif /** Pin: CYBSP_BT_HOST_WAKE */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P8_4) +#endif /** Pin: CYBSP_BT_DEVICE_WAKE */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P6_1) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RTS #define CYBSP_DEBUG_UART_RTS (P5_2) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_CTS #define CYBSP_DEBUG_UART_CTS (P5_3) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P1_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P1_1) +#endif /** Pin: CYBSP_TDO_SWO */ +#ifndef CYBSP_TDO_SWO #define CYBSP_TDO_SWO (P6_4) +#endif /** Pin: CYBSP_TMS_SWDIO */ +#ifndef CYBSP_TMS_SWDIO #define CYBSP_TMS_SWDIO (P6_6) +#endif /** Pin: CYBSP_SWCLK */ +#ifndef CYBSP_SWCLK #define CYBSP_SWCLK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P0_2) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P0_3) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P0_4) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P0_5) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) @@ -213,49 +308,93 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#ifndef CYBSP_A0 +#define CYBSP_A0 (P10_0) +#endif /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#ifndef CYBSP_A1 +#define CYBSP_A1 (P10_1) +#endif /** Arduino A2 */ -#define CYBSP_A2 P6_4 +#ifndef CYBSP_A2 +#define CYBSP_A2 (P6_4) +#endif /** Arduino A3 */ -#define CYBSP_A3 P6_5 +#ifndef CYBSP_A3 +#define CYBSP_A3 (P6_5) +#endif /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#ifndef CYBSP_A4 +#define CYBSP_A4 (P10_4) +#endif /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#ifndef CYBSP_A5 +#define CYBSP_A5 (P10_5) +#endif /** Arduino D0 */ +#ifndef CYBSP_D0 #define CYBSP_D0 (P5_0) +#endif /** Arduino D1 */ +#ifndef CYBSP_D1 #define CYBSP_D1 (P5_1) +#endif /** Arduino D2 */ +#ifndef CYBSP_D2 #define CYBSP_D2 (P5_2) +#endif /** Arduino D3 */ +#ifndef CYBSP_D3 #define CYBSP_D3 (P5_3) +#endif /** Arduino D4 */ +#ifndef CYBSP_D4 #define CYBSP_D4 (P5_4) +#endif /** Arduino D5 */ +#ifndef CYBSP_D5 #define CYBSP_D5 (P5_5) +#endif /** Arduino D6 */ +#ifndef CYBSP_D6 #define CYBSP_D6 (P5_6) +#endif /** Arduino D7 */ +#ifndef CYBSP_D7 #define CYBSP_D7 (P5_7) +#endif /** Arduino D8 */ +#ifndef CYBSP_D8 #define CYBSP_D8 (NC) +#endif /** Arduino D9 */ +#ifndef CYBSP_D9 #define CYBSP_D9 (NC) +#endif /** Arduino D10 */ +#ifndef CYBSP_D10 #define CYBSP_D10 (P0_5) +#endif /** Arduino D11 */ +#ifndef CYBSP_D11 #define CYBSP_D11 (P0_2) +#endif /** Arduino D12 */ +#ifndef CYBSP_D12 #define CYBSP_D12 (P0_3) +#endif /** Arduino D13 */ +#ifndef CYBSP_D13 #define CYBSP_D13 (P0_4) +#endif /** Arduino D14 */ +#ifndef CYBSP_D14 #define CYBSP_D14 (NC) +#endif /** Arduino D15 */ +#ifndef CYBSP_D15 #define CYBSP_D15 (NC) +#endif /** \} group_bsp_pins_arduino */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 4ff5ccb454..7a99d7b707 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index a9d28573c6..b78effb0c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3a0414efa3..61d4a4b17b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 0f7f5fe0df..e9a6874e34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 9be3c4aa3b..f0a3d746f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index b405a8b603..51808a1db4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *

Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index ed8102601f..04783e4b97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 55f9bd74fa..f469a01ea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 46ae60d212..216bafabba 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 45223d1950..41fe86f553 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 9512e17264..1bbe7b6308 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 682af2fcd3..0d31cfa23b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 181ef57d60..de38a7a37c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index ae1ee444a6..28234b34be 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 5ea5df83bd..47ec41cdba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_RX_obj = + const cyhal_resource_inst_t CYBSP_CSD_RX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_RX_PORT_NUM, .channel_num = CYBSP_CSD_RX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index ace7a770b0..d9240fabfb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -57,7 +57,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -81,7 +81,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -105,7 +105,7 @@ extern "C" { #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -129,7 +129,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -153,7 +153,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -177,7 +177,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -201,7 +201,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -225,7 +225,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -249,7 +249,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -273,7 +273,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -297,7 +297,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -321,7 +321,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -345,7 +345,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -369,7 +369,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -393,7 +393,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -417,7 +417,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 417ad4426e..ec8db9f48e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,7 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1367 +* QSPI Configurator: 2.0.0.1483 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 086f1db736..a5af025903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,7 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1367 +* QSPI Configurator: 2.0.0.1483 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index cb52455ed5..fdc143f8c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index b26ae3cc61..d1dd5c4389 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -40,14 +40,14 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 56b1a8aaf7..6adcc6ef0a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -69,7 +69,7 @@ #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -83,7 +83,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .cco_Freq = 355U, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -91,7 +91,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -99,7 +99,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -107,7 +107,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -115,14 +115,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -246,14 +246,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -284,7 +284,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -295,59 +295,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -357,7 +357,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -404,21 +404,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -465,7 +465,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -512,48 +512,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 372336c342..36ed3c918d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (libs/psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index c90a8a3b8d..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,5 +1,5 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 0491776b02..77056075af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus index 57df770d92..993a963963 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -75,14 +75,6 @@ - - - - - - - - @@ -96,16 +88,6 @@ - - - - - - - - - - @@ -275,8 +257,6 @@ - - @@ -285,10 +265,6 @@ - - - - @@ -405,7 +381,6 @@ - @@ -423,8 +398,6 @@ - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c deleted file mode 100644 index 4e48631123..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c +++ /dev/null @@ -1,1509 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST.c -* -* \brief -* This file provides the source code to the API for the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "SDIO_HOST.h" -#include "cy_utils.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#ifdef CY_RTOS_AWARE - - #include "cyabs_rtos.h" - - #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) - static cy_semaphore_t sdio_transfer_finished_semaphore; - static bool sema_initialized = false; -#endif - -/* Backup struct used to store and restore non retention UDB registers */ -typedef struct -{ - uint32_t CY_SDIO_UDB_WRKMULT_CTL_0; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_1; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_2; - uint32_t CY_SDIO_UDB_WRKMULT_CTL_3; -} stc_sdio_backup_regs_t; - -/*Globals Needed for DMA */ -/*DMA channel structures*/ -cy_stc_dma_channel_config_t respChannelConfig; -cy_stc_dma_channel_config_t cmdChannelConfig; -cy_stc_dma_channel_config_t writeChannelConfig; -cy_stc_dma_channel_config_t readChannelConfig; - -/*DMA Descriptor structures*/ -cy_stc_dma_descriptor_t respDesr; -cy_stc_dma_descriptor_t cmdDesr; -cy_stc_dma_descriptor_t readDesr0; -cy_stc_dma_descriptor_t readDesr1; -cy_stc_dma_descriptor_t writeDesr0; -cy_stc_dma_descriptor_t writeDesr1; - -/*Global structure used for data keeping*/ -stc_sdio_gInternalData_t gstcInternalData; - -/*Global CRC table*/ -static uint8_t crcTable[256]; - -/*Global values used for DMA interrupt*/ -static uint32_t yCountRemainder; -static uint32_t yCounts; - -/* Global value for card interrupt */ -static uint8_t pfnCardInt_count = 0; - -/*Global structure to store UDB registers */ -static stc_sdio_backup_regs_t regs; - -static uint32_t udb_initialized = 0; - -cy_stc_syspm_callback_params_t sdio_pm_callback_params; -cy_stc_syspm_callback_t sdio_pm_callback_handler; - -/* Deep Sleep Mode API Support */ -static void SDIO_SaveConfig(void); -static void SDIO_RestoreConfig(void); - -/******************************************************************************* -* Function Name: SDIO_DeepSleepCallback -****************************************************************************//** -* -* Callback executed during Deep Sleep entry/exit -* -* \param params -* Pointer to structure that holds callback parameters for this driver. -* -* \param mode -* The state transition mode that is currently happening. -* -* \note -* Saves/Restores SDIO UDB registers -* -* \return -* CY_SYSPM_SUCCESS if the transition was successful, otherwise CY_SYSPM_FAIL -* -*******************************************************************************/ -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) -{ - CY_UNUSED_PARAMETER(params); - cy_en_syspm_status_t status = CY_SYSPM_FAIL; - - switch (mode) - { - case CY_SYSPM_CHECK_READY: - case CY_SYSPM_CHECK_FAIL: - status = CY_SYSPM_SUCCESS; - break; - - case CY_SYSPM_BEFORE_TRANSITION: - SDIO_SaveConfig(); - status = CY_SYSPM_SUCCESS; - break; - - case CY_SYSPM_AFTER_TRANSITION: - SDIO_RestoreConfig(); - status = CY_SYSPM_SUCCESS; - break; - - default: - break; - } - - return status; -} - -/******************************************************************************* -* Function Name: SDIO_Init -****************************************************************************//** -* -* Initializes the SDIO hardware -* -* \param pfuCb -* Pointer to structure that holds pointers to callback function -* see \ref stc_sdio_irq_cb_t. -* -* \note -* Sets SD Clock Frequency to 400 kHz -*******************************************************************************/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) -{ - if ( !udb_initialized ) - { - udb_initialized = 1; - SDIO_Host_Config_TriggerMuxes(); - SDIO_Host_Config_UDBs(); - } - - /*Set Number of Blocks to 1 initially, this will be updated later*/ - SDIO_SetNumBlocks(1); - - /*Enable SDIO ISR*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - - /*Enable the Status Reg to generate an interrupt*/ - SDIO_STATUS_AUX_CTL |= (0x10); - - /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ - /*First clear priority of all*/ - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; - - /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; - - /*Setup callback for card interrupt*/ - gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; - - /*Setup the DMA channels*/ - SDIO_SetupDMA(); - - /*Initialize CRC*/ - SDIO_Crc7Init(); - - /*Enable all the bit counters*/ - SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - - /*Set block byte count to 64, this will be changed later */ - SDIO_SetBlockSize(64); - - /*Set the read and write FIFOs to use the half full status*/ - (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; - (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; - - /*Set clock to 400k, and enable it*/ - SDIO_SetSdClkFrequency(400000); - SDIO_EnableIntClock(); - SDIO_EnableSdClk(); -} - - -/******************************************************************************* -* Function Name: SDIO_SendCommand -****************************************************************************//** -* -* Send an SDIO command, don't wait for it to finish. -* -* \param pstcCmdConfig -* Command configuration structure. See \ref stc_sdio_cmd_config_t. -* -*******************************************************************************/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) -{ - /*buffer to hold command data*/ - static uint8_t u8cmdBuf[6]; - - /*Populate buffer*/ - /*Element 0 is the Most Significant Byte*/ - u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; - u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); - u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); - u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); - u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); - - /*calculate the CRC of above data*/ - u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); - /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ - u8cmdBuf[5] = u8cmdBuf[5] << 1; - /*Add on the end bit*/ - u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; - - /*Load the first byte into A0*/ - SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; - - /*If a response is expected setup DMA to receive the response*/ - if (pstcCmdConfig->bResponseRequired == true) - { - /*Clear the flag in hardware that says skip response*/ - SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; - - /*Set the destination address*/ - respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); - - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); - } - else - { - /*Set the skip flag*/ - SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; - } - - /*Setup the Command DMA*/ - /*Set the source address*/ - cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); - - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); -} - - -/******************************************************************************* -* Function Name: SDIO_GetResponse -****************************************************************************//** -* -* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks -* for index errors, CRC errors, and end bit errors. -* -* \param bCmdIndexCheck -* If True check for index errors -* -* \param bCmdCrcCheck -* If True check for CRC errors -* -* \param u8cmdIdx -* Command index, used for checking the index error -* -* \param pu32Response -* location to store 32 bit response -* -* \param pu8ResponseBuf -* buffer that holds the 6 bytes of response data -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) -{ - /*Function return*/ - en_sdio_result_t enRet = Error; - /*variable to hold temporary CRC*/ - uint8_t u8TmpCrc; - /*temporary response*/ - uint32_t u32TmpResponse; - - /*Zero out the pu32Response*/ - *pu32Response = 0; - - /*Check if the CRC needs to be checked*/ - if (bCmdCrcCheck) - { - /*Calculate the CRC*/ - u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); - - /*Shift calculated CRC up by one bit to match bit position of CRC*/ - u8TmpCrc = u8TmpCrc << 1; - - /*Compare calculated CRC with received CRC*/ - if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) - { - enRet |= CommandCrcError; - } - } - - /*Check if the index needs to be checked*/ - if (bCmdIndexCheck) - { - /*The index resides in the lower 6 bits of the 1st byte of the response*/ - if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) - { - enRet |= CommandIdxError; - } - } - - /*Check the end bit*/ - if (!(pu8ResponseBuf[5] & 0x01)) - { - enRet |= CommandEndError; - } - - if (enRet == Error) - { - /*If we get here then there were no errors with the command populate the response*/ - u32TmpResponse = pu8ResponseBuf[1]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[2]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[3]; - u32TmpResponse = u32TmpResponse << 8; - u32TmpResponse |= pu8ResponseBuf[4]; - - *pu32Response = u32TmpResponse; - - enRet = Ok; - } - - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_InitDataTransfer -****************************************************************************//** -* -* Configure the data channel for a data transfer. For a write this doesn't start -* the write, that must be done separately after the response is received. -* -* \param pstcDataConfig -* Data configuration structure. See \ref stc_sdio_data_config_t -* -* -*******************************************************************************/ -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) -{ - /*hold size of entire transfer*/ - uint32_t dataSize; - - /*calculate how many bytes are going to be sent*/ - dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; - - /*Set the block size and number of blocks*/ - SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); - SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); - - /*If we are reading data setup the DMA to receive read data*/ - if (pstcDataConfig->bRead == true) - { - /*First disable the write channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - - /*Clear any pending interrupts in the DMA*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - - /*setup the destination addresses*/ - readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); - readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ - readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - - /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the - DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility - that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA - will be SW triggered when hardware indicates all bytes have been received. - This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to - be at least 3 bytes bigger than the data size. - - Since the X loop is setup to 4, the maximum number of Y loop is 256 so one - descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. - Since we don't know the maximum number of bytes to read only two descriptors will - be used. If more than 2048 bytes need to be read then and interrupt will be enabled - The descriptor that is not currently running will be updated in the ISR to receive - more data. - - So there are three conditions to check: - 1) Are we sending less than or equal to 1024 bytes if so use one descriptor - 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors - 3) Greater than 2048, use two descriptors and the ISR - */ - - if (dataSize <= 1024) - { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - /*Setup descriptor 0 to point to nothing and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (dataSize <=2048) - { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ - - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - - /*Setup descriptor 0 to point to descriptor 1*/ - readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to nothing and disable */ - readDesr1.nextPtr = 0; - - /*Don't disable after first descriptor*/ - readDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ - readDesr1.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else /*dataSize must be greater than 2048*/ - { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ - yCounts = (dataSize / 1024); - - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); - - /*Setup the Y Ctrl for both descriptors*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - - /*Setup descriptor 0 to point to descriptor 1*/ - readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ - readDesr1.nextPtr = (uint32_t)(&readDesr0); - - /*Don't disable the channel on completion of descriptor*/ - readDesr0.ctl &= ~0x01000000; - readDesr1.ctl &= ~0x01000000; - - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ - yCounts -= 2; - - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); - - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the read*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; - } - - /*Otherwise it is a write*/ - else - { - /*First disable the Read channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Clear any pending interrupts in the DMA*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - - /*setup the SRC addresses*/ - writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); - writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - - - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ - writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); - writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); - - if (dataSize <= 1024) - { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - /*Setup descriptor 0 to point to nothing and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else if (dataSize <=2048) - { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ - - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - - /*Setup descriptor 0 to point to descriptor 1*/ - writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to nothing and disable */ - writeDesr1.nextPtr = 0; - - /*Don't disable after first descriptor*/ - writeDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ - writeDesr1.ctl |= 0x01000000; - - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else /*dataSize must be greater than 2048*/ - { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ - yCounts = (dataSize / 1024); - - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); - - /*Setup the Y Ctrl for both descriptors*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - - /*Setup descriptor 0 to point to descriptor 1*/ - writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ - writeDesr1.nextPtr = (uint32_t)(&writeDesr0); - - /*Don't disable the channel on completion of descriptor*/ - writeDesr0.ctl &= ~0x01000000; - writeDesr1.ctl &= ~0x01000000; - - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ - yCounts -= 2; - - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); - } -} - - -/******************************************************************************* -* Function Name: SDIO_SendCommandAndWait -****************************************************************************//** -* -* This function sends a command on the command channel and waits for that -* command to finish before returning. If a Command 53 is issued this function -* will handle all of the data transfer and wait to return until it is done. -* -* \param pstcCmd -* Pointer command configuration structure see \ref stc_sdio_cmd_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) -{ - /* Store the command and data configurations*/ - stc_sdio_cmd_config_t stcCmdConfig; - stc_sdio_data_config_t stcDataConfig; - - uint32_t u32CmdTimeout = 0; - - /*Returns from various function calls*/ - en_sdio_result_t enRet = Error; - en_sdio_result_t enRetTmp = Ok; - - /* Hold value of if these checks are needed */ - uint8_t bCmdIndexCheck; - uint8_t bCmdCrcCheck; - static uint8_t u8responseBuf[6]; - - /* Clear statuses */ - gstcInternalData.stcEvents.u8CmdComplete = 0; - gstcInternalData.stcEvents.u8TransComplete = 0; - gstcInternalData.stcEvents.u8CRCError = 0; - - /* Setup the command configuration */ - stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; - stcCmdConfig.u32Argument = pstcCmd->u32Arg; - -#ifdef CY_RTOS_AWARE - - cy_rslt_t result; - - /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in - * interrupt thread. - */ - if(!sema_initialized) - { - cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 ); - sema_initialized = true; - } -#else - - /* Variable used for holding timeout value */ - uint32_t u32Timeout = 0; -#endif - - /*Determine the type of response and if we need to do any checks*/ - /*Command 0 and 8 have no response, so don't wait for one*/ - if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) - { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = false; - stcCmdConfig.pu8ResponseBuf = NULL; - } - - /*Command 5's response doesn't have a CRC or index, so don't check*/ - else if (pstcCmd->u32CmdIdx == 5) - { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; - } - /*Otherwise check everything*/ - else - { - bCmdIndexCheck = true; - bCmdCrcCheck = true; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; - } - - /*Check if the command is 53, if it is then setup the data transfer*/ - if (pstcCmd->u32CmdIdx == 53) - { - /*Set the number of blocks in the global struct*/ - stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; - /*Set the size of the data transfer*/ - stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; - /*Set the direction are we reading or writing*/ - stcDataConfig.bRead = pstcCmd->bRead; - /*Set the pointer for the data*/ - stcDataConfig.pu8Data = pstcCmd->pu8Data; - - /*Get the data Transfer Ready*/ - SDIO_InitDataTransfer(&stcDataConfig); - - /*Set bit saying this was a CMD_53*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; - } - - /*Send the command*/ - SDIO_SendCommand(&stcCmdConfig); - - /*Wait for the command to finish*/ - do - { - u32CmdTimeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); - - } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); - - - if (u32CmdTimeout == SDIO_CMD_TIMEOUT) - { - enRet |= CMDTimeout; - } - else /*CMD Passed*/ - { - /*If a response is expected check it*/ - if (stcCmdConfig.bResponseRequired == true) - { - enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); - if (enRetTmp != Ok) - { - enRet |= enRetTmp; - } - else /*Response good*/ - { - /*if it was command 53, check the response to ensure there was no error*/ - if ((pstcCmd->u32CmdIdx) == 53) - { - /*Make sure none of the error bits are set*/ - if (*(pstcCmd->pu32Response) & 0x0000cf00) - { - enRet |= ResponseFlagError; - } - else /*CMD53 Response good*/ - { - /*If it was command 53 and it was a write enable the write*/ - if (pstcCmd->bRead == false && enRet == Error) - { - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the write*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - /*Enable the channel*/ - Cy_SysLib_DelayCycles(35); - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; - } - - #ifdef CY_RTOS_AWARE - /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released - * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in - * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases - * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero - * and exit. Or timeout occurs - */ - result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); - - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - if (result != CY_RSLT_SUCCESS) - #else - /* Wait for the transfer to finish */ - do - { - u32Timeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); - - if (u32Timeout == SDIO_DAT_TIMEOUT) - #endif - { - enRet |= DataTimeout; - } - - /* if it was a read it is possible there is still extra data hanging out, trigger the - DMA again. This can result in extra data being transfered so the read buffer should be - 3 bytes bigger than needed*/ - if (pstcCmd->bRead == true) - { - Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); - } - - if (enRetTmp == DataCrcError) - { - enRet |= DataCrcError; - } - }/*CMD53 response good*/ - }/*Not a CMD53*/ - } /*Response Good*/ - } /*No Response Required, thus no CMD53*/ - } /*CMD Passed*/ - -#ifndef CY_RTOS_AWARE - u32Timeout = 0; -#endif - - /*If there were no errors then indicate transfer was okay*/ - if (enRet == Error) - { - enRet = Ok; - } - - /*reset CmdTimeout value*/ - u32CmdTimeout = 0; - - /*Always Reset on exit to clean up*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - /*No longer a CMD_53*/ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); - SDIO_Reset(); - - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_CheckForEvent -****************************************************************************//** -* -* Checks to see if a specific event has occurred such a command complete or -* transfer complete. -* -* \param enEventType -* The type of event to check for. See \ref en_sdio_event_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) -{ - en_sdio_result_t enRet = Error; - - /*Disable Interrupts while modifying the global*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - - /*Switch the event to check*/ - switch ( enEventType ) - { - /*If the command is done clear the flag*/ - case SdCmdEventCmdDone: - if (gstcInternalData.stcEvents.u8CmdComplete > 0) - { - gstcInternalData.stcEvents.u8CmdComplete = 0; - enRet = Ok; - } - break; - - /*If the transfer is done check for CRC Error and clear the flag*/ - case SdCmdEventTransferDone: - if (gstcInternalData.stcEvents.u8TransComplete > 0) - { - gstcInternalData.stcEvents.u8TransComplete = 0; - enRet = Ok; - } - /*Check for CRC error and set flags*/ - if (gstcInternalData.stcEvents.u8CRCError > 0) - { - enRet = DataCrcError; - gstcInternalData.stcEvents.u8CRCError = 0; - } - break; - } - - /*Re-enable Interrupts*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); - return enRet; -} - - -/******************************************************************************* -* Function Name: SDIO_CalculateCrc7 -****************************************************************************//** -* -* Calculate the 7 bit CRC for the command channel -* -* \param pu8Data -* Data to calculate CRC on -* -* \param u8Size -* Number of bytes to calculate CRC on -* -* \return -* CRC -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) -{ - uint8_t data; - uint8_t remainder = 0; - uint32_t byte; - - for(byte = 0; byte < u8Size; ++byte) - { - data = pu8Data[byte] ^ remainder; - remainder = crcTable[data] ^ (remainder << 8); - } - - return (remainder>>1); -} - - -/******************************************************************************* -* Function Name: SDIO_Crc7Init -****************************************************************************//** -* -* Initialize 7-bit CRC Table -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ -void SDIO_Crc7Init(void) -{ - uint8_t remainder; - uint8_t bit; - uint32_t dividend; - - for(dividend = 0; dividend < 256; ++dividend) - { - remainder = dividend; - - for(bit = 8; bit > 0; --bit) - { - if (remainder & SDIO_CRC_UPPER_BIT) - { - remainder = (remainder << 1) ^ SDIO_CRC7_POLY; - } - else - { - remainder = (remainder << 1); - } - } - - crcTable[dividend] = (remainder); - } -} - - -/******************************************************************************* -* Function Name: SDIO_SetBlockSize -****************************************************************************//** -* -* Sets the size of each block -* -* \param u8ByteCount -* Size of the block -* -*******************************************************************************/ -void SDIO_SetBlockSize(uint8_t u8ByteCount) -{ - SDIO_BYTE_COUNT_REG = u8ByteCount; -} - - -/******************************************************************************* -* Function Name: SDIO_SetNumBlocks -****************************************************************************//** -* -* Sets the number of blocks to send -* -* \param u8BlockCount -* Size of the block -* -*******************************************************************************/ -void SDIO_SetNumBlocks(uint8_t u8BlockCount) -{ - SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; - SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; - /*The one is used so that we can do 256 bytes*/ - SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; - SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; -} - - -/******************************************************************************* -* Function Name: SDIO_EnableIntClock -****************************************************************************//** -* -* Enable Internal clock for the block -* -*******************************************************************************/ -void SDIO_EnableIntClock(void) -{ - SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); -} - - -/******************************************************************************* -* Function Name: SDIO_DisableIntClock -****************************************************************************//** -* -* Enable Disable clock for the block -* -*******************************************************************************/ -void SDIO_DisableIntClock(void) -{ - SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); -} - - -/******************************************************************************* -* Function Name: SDIO_EnableSdClk -****************************************************************************//** -* -* Enable SD Clock out to pin -* -*******************************************************************************/ -void SDIO_EnableSdClk(void) -{ - SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; -} - - -/******************************************************************************* -* Function Name: SDIO_DisableSdClk -****************************************************************************//** -* -* Disable SD Clock out to the pin -* -*******************************************************************************/ -void SDIO_DisableSdClk(void) -{ - SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; -} - - -/******************************************************************************* -* Function Name: SDIO_SetSdClkFrequency -****************************************************************************//** -* -* Sets the frequency of the SD Clock -* -* \param u32SdClkFreqHz -* Frequency of SD Clock in Hz. -* -* \note -* Only an integer divider is used, so the desired frequency may not be meet -*******************************************************************************/ -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) -{ - uint16_t u16Div; - /* - * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB - * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required - * SDIO operating frequency. - */ - u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); - Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); -} - - -/******************************************************************************* -* Function Name: SDIO_SetupDMA -****************************************************************************//** -* -* Configures the DMA for the SDIO block -* -*******************************************************************************/ -void SDIO_SetupDMA(void) -{ - /*Set the number of bytes to send*/ - SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); - /*Set the destination address*/ - SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; - - /*Initialize descriptor for cmd channel*/ - Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); - - /*Set flag to disable descriptor when done*/ - cmdDesr.ctl |= 0x01000000; - - /*Configure channel*/ - /*CMD channel can be preempted, and has lower priority*/ - cmdChannelConfig.descriptor = &cmdDesr; - cmdChannelConfig.preemptable = 1; - cmdChannelConfig.priority = 1; - cmdChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); - - /*Set the number of bytes to receive*/ - SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; - /*Set the source address*/ - SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; - - /*Initialize descriptor for response channel*/ - Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); - - /*Set flag to disable descriptor when done*/ - respDesr.ctl |= 0x01000000; - - /*Configure channel*/ - /*response channel can be preempted, and has lower priority*/ - respChannelConfig.descriptor = &respDesr; - respChannelConfig.preemptable = 1; - respChannelConfig.priority = 1; - respChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); - - /*Set the destination address*/ - SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; - - /*Initialize descriptor for write channel*/ - Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - - /*Configure channel*/ - /*write channel cannot be preempted, and has highest priority*/ - writeChannelConfig.descriptor = &writeDesr0; - writeChannelConfig.preemptable = 0; - writeChannelConfig.priority = 0; - writeChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); - - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); - - /*Set the source address*/ - SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; - /*Initialize descriptor for read channel*/ - Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - - /*Configure channel*/ - /*read channel cannot be preempted, and has highest priority*/ - readChannelConfig.descriptor = &readDesr0; - readChannelConfig.preemptable = 0; - readChannelConfig.priority = 0; - readChannelConfig.enable = 0u; - - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); - - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); - - /*Enable DMA block*/ - Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); -} - - -/******************************************************************************* -* Function Name: SDIO_Reset -****************************************************************************//** -* -* Reset the SDIO interface -* -*******************************************************************************/ -void SDIO_Reset(void) -{ - /*Control register is in pulse mode, so this just pulses the reset*/ - SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); -} - - -/******************************************************************************* -* Function Name: SDIO_EnableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ -void SDIO_EnableChipInt(void) -{ - SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; -} - - -/******************************************************************************* -* Function Name: SDIO_DisableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ -void SDIO_DisableChipInt(void) -{ - SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; -} - - -/******************************************************************************* -* Function Name: SDIO_IRQ -****************************************************************************//** -* -* SDIO interrupt, checks for events, and calls callbacks -* -*******************************************************************************/ -void SDIO_IRQ(void) -{ - uint8_t u8Status; - - /* First read the status register */ - u8Status = SDIO_STATUS_REG; - - /* Check card interrupt */ - if (u8Status & SDIO_STS_CARD_INT ) - { - pfnCardInt_count++; - } - - /* Execute card interrupt callback if neccesary */ - if (0 != pfnCardInt_count) - { - if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) - { - gstcInternalData.pstcCallBacks.pfnCardIntCb(); - } - pfnCardInt_count--; - } - - /* If the command is complete set the flag */ - if (u8Status & SDIO_STS_CMD_DONE) - { - gstcInternalData.stcEvents.u8CmdComplete++; - } - - /* Check if a write is complete */ - if (u8Status & SDIO_STS_WRITE_DONE ) - { - - /* Clear the Write flag and CMD53 flag */ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); - - /* Check if the CRC status return was bad */ - if (u8Status & SDIO_STS_CRC_ERR) - { - /* CRC was bad, set the flag */ - gstcInternalData.stcEvents.u8CRCError++; - } - - /* Set the done flag */ - - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else - gstcInternalData.stcEvents.u8TransComplete++; - #endif - } - - /* Check if a read is complete */ - if (u8Status & SDIO_STS_READ_DONE) - { - /* Clear the read flag */ - SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); - - /* Check the CRC */ - if (u8Status & SDIO_STS_CRC_ERR) - { - /* CRC was bad, set the flag */ - gstcInternalData.stcEvents.u8CRCError++; - } - /* Okay we're done so set the done flag */ - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else - gstcInternalData.stcEvents.u8TransComplete++; - #endif - } - - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); -} - - -/******************************************************************************* -* Function Name: SDIO_READ_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Read interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ -void SDIO_READ_DMA_IRQ(void) -{ - /*Shouldn't have to change anything unless it is the last descriptor*/ - - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) - { - /*We need to increment the destination address every time*/ - readDesr1.dst += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ - readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - } - - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) - { - /*We need to increment the destination address everytime*/ - readDesr0.dst += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ - readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); - } - } - - /*Clear the interrupt*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - /*decrement y counts*/ - yCounts--; -} - -/******************************************************************************* -* Function Name: SDIO_WRITE_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Write interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ -void SDIO_WRITE_DMA_IRQ(void) -{ - /*We shouldn't have to change anything unless it is the last descriptor*/ - - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) - { - /*We also need to increment the destination address every-time*/ - writeDesr1.src += 2048; - - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ - writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - } - - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) - { - /*We also need to increment the destination address*/ - writeDesr0.src += 2048; - /*If this is the last descriptor*/ - if ((yCounts == 1) && (yCountRemainder == 0)) - { - /* In this case all we need to change is the next descriptor and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - else if (yCounts == 0 && (yCountRemainder > 0)) - { - /*change next descriptor, and disable*/ - writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ - writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - } - } - - /*Clear the interrupt*/ - Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - yCounts--; -} - -/******************************************************************************* -* Function Name: SDIO_Free -****************************************************************************//** -* -* Frees any system resources that were allocated by the SDIO driver. -* -*******************************************************************************/ -void SDIO_Free(void) -{ -#ifdef CY_RTOS_AWARE - cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); -#endif -} - -/******************************************************************************* -* Function Name: SDIO_SaveConfig -******************************************************************************** -* -* Saves the user configuration of the SDIO UDB non-retention registers. Call the -* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function. -* -*******************************************************************************/ -static void SDIO_SaveConfig(void) -{ - regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0]; - regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1]; - regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2]; - regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3]; -} - - -/******************************************************************************* -* Function Name: SDIO_RestoreConfig -******************************************************************************** -* -* Restores the user configuration of the SDIO UDB non-retention registers. Call -* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function. -* -*******************************************************************************/ -static void SDIO_RestoreConfig(void) -{ - UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0; - UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1; - UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2; - UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3; -} - -#if defined(__cplusplus) -} -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h deleted file mode 100644 index 06edc747bc..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h +++ /dev/null @@ -1,396 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST.h -* -* \brief -* This file provides types definition, constants and function definition for -* the SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \defgroup group_bsp_pin_state Pin States -* \defgroup group_bsp_pins Pin Mappings -* \defgroup group_bsp_macros Macros -* \defgroup group_bsp_functions Functions -* -* \defgroup group_udb_sdio UDB_SDIO -* \{ -* SDIO - Secure Digital Input Output is a standard for communicating with various - external devices such as Wifi and bluetooth devices. -*

-* The driver is currently designed to only support communication with certain -* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general -* SDIO card, or even and SD card. It is only intended to be used by the WiFi -* driver for communication. -*

-* This is not intended to be used as a general purpose API. -* -* \section group_udb_sdio_section_configuration_considerations Configuration Considerations -* Features: -* * Always Four Wire Mode -* * Supports Card Interrupt -* * Uses DMA for command and data transfer -* -* \defgroup group_udb_sdio_macros Macros -* \defgroup group_udb_sdio_functions Functions -* \defgroup group_udb_sdio_data_structures Data Structures -*/ - -#if !defined(CY_SDIO_H) -#define CY_SDIO_H - -#include "SDIO_HOST_cfg.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - -/*************************************** -* API Constants -***************************************/ - -/** -* \addtogroup group_udb_sdio_macros -* \{ -*/ - -#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ -#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ -#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ -#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ - -/*! -\defgroup group_sdio_cmd_constants Constants for the command channel -*/ -/* @{*/ -#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ -#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ -#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/ -#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/ -/*@} group_sdio_cmd_constants */ - -/*! -\defgroup group_sdio_ctrl_reg SDIO control register bits -*/ -/* @{*/ -#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ -#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ -#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ -#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ -#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ -#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ -#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ -#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ -/*@} group_sdio_ctrl_reg */ - -/*! -\defgroup group_sdio_status_reg SDIO status register bits -*/ -/* @{*/ -#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ -#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ -#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ -#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ -#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ -#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ -#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ -/*@} group_sdio_status_reg */ - -/*! -\defgroup group_sdio_crc Constants for 7bit CRC for command -*/ -/* @{*/ -#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ -#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ -/*@} group_sdio_crc */ - -/** \} group_udb_sdio_macros */ - - -/*************************************** -* Type Definitions -***************************************/ - -/** -* \addtogroup group_udb_sdio_data_structures -* \{ -*/ - -/** -* Create a type for the card interrupt call back -*/ -typedef void (* sdio_card_int_cb_t)(void); - -/** -* \brief This enum is used when checking for specific events -*/ -typedef enum en_sdio_event -{ - SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ - SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ - -}en_sdio_event_t; - -/** -* \brief Used to indicate the result of a function -*/ -typedef enum en_sdio_result -{ - Ok = 0x00, /**< No error*/ - Error = 0x01, /**< Non-specific error code*/ - CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ - CommandIdxError = 0x04, /**< The index for the command didn't match*/ - CommandEndError = 0x08, /**< There was an end bit error on the command*/ - DataCrcError = 0x10, /**< There was a data CRC Error*/ - CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ - DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ - ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ - -} en_sdio_result_t; - -/** -* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function -*/ -typedef struct stc_sdcmd_event_flag -{ - uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ - uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ - uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ - -}stc_sdio_event_flag_t; - -/** -* \brief Holds pointers to callback functions -*/ -typedef struct stc_sdio_irq_cb -{ - sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ -}stc_sdio_irq_cb_t; - -/** -* \brief Global structure used to hold data from interrupt and other functions -*/ -typedef struct stc_sdio_gInternalData -{ - stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ - stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ -}stc_sdio_gInternalData_t; - -/** -* \brief structure used for configuring command -*/ -typedef struct stc_sdio_cmd_config -{ - uint8_t u8CmdIndex; /**< Command index*/ - uint32_t u32Argument; /**< The argument of command */ - uint8_t bResponseRequired; /**< TRUE: A Response is required*/ - uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ - -}stc_sdio_cmd_config_t; - -/** -* \brief structure used for the data channel -*/ -typedef struct stc_sdio_data_config -{ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockSize; /**< Block size*/ - uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - -}stc_sdio_data_config_t; - -/** -* \brief structure used for configuring command and data -*/ -typedef struct stc_sdio_cmd -{ - uint32_t u32CmdIdx; /**< Command index*/ - uint32_t u32Arg; /**< The argument of command*/ - uint32_t *pu32Response; /**< Pointer to location to store response*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockCnt; /**< Number of blocks to send*/ - uint16_t u16BlockSize; /**< Block size*/ -}stc_sdio_cmd_t; - -/** \} group_udb_sdio_data_structures */ - -/*************************************** -* Function Prototypes -***************************************/ - -/** -* \addtogroup group_udb_sdio_functions -* \{ -*/ - -/* Main functions*/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); -void SDIO_EnableIntClock(void); -void SDIO_DisableIntClock(void); -void SDIO_EnableSdClk(void); -void SDIO_DisableSdClk(void); -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); -void SDIO_Reset(void); -void SDIO_EnableChipInt(void); -void SDIO_DisableChipInt(void); -void SDIO_Free(void); - -/*Low Level Functions*/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); -void SDIO_SetBlockSize(uint8_t u8ByteCount); -void SDIO_SetNumBlocks(uint8_t u8BlockCount); - -/*DMA setup function*/ -void SDIO_SetupDMA(void); - -/*Interrupt Function*/ -void SDIO_IRQ(void); -void SDIO_READ_DMA_IRQ(void); -void SDIO_WRITE_DMA_IRQ(void); - -void SDIO_Crc7Init(void); - -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); - -/** \endcond */ - -/** \} group_udb_sdio_functions */ - - -/*************************************** -* Hardware Registers -***************************************/ - -/** \cond INTERNAL */ - -#define SDIO_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) - -#define SDIO_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) - -#define SDIO_STATUS_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_REG) - -#define SDIO_STATUS_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_REG) - -#define SDIO_STATUS_INT_MSK (* (reg8*) \ -SDIO_HOST_bSDIO_StatusReg__MASK_REG) - -#define SDIO_STATUS_AUX_CTL (* (reg8 *) \ -SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG) - -#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) - -#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) - -#define SDIO_CMD_COMMAND_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F0_REG) - -#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__A0_REG) - -#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F0_REG) - -#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F1_REG) - -#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \ -SDIO_HOST_bSDIO_CMD__F1_REG) - -#define SDIO_DAT_WRITE_REG (* (reg16 *) \ -SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) - -#define SDIO_DAT_WRITE_PTR ( (reg16 *) \ -SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) - -#define SDIO_DAT_READ_REG (* (reg16 *) \ -SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) - -#define SDIO_DAT_READ_PTR ( (reg16 *) \ -SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) - -#define SDIO_BYTE_COUNT_REG (* (reg8 *) \ -SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) - -/** \endcond */ - -#if defined(__cplusplus) -} -#endif - -#endif /* (CY_SDIO_H) */ - -/** \} group_udb_sdio */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c deleted file mode 100644 index a2808d37c0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ /dev/null @@ -1,1056 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.c -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "SDIO_HOST_cfg.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/***************************CMD DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_16CYC, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1L, - .dstXincrement = 0L, - .xCount = 5UL, - .srcYincrement = 0L, - .dstYincrement = 0L, - .yCount = 1UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Read DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0L, - .dstXincrement = 2L, - .xCount = 10UL, - .srcYincrement = 0L, - .dstYincrement = 10L, - .yCount = 2UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Resp DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0L, - .dstXincrement = 1L, - .xCount = 6UL, - .srcYincrement = 0L, - .dstYincrement = 0L, - .yCount = 1UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - -/***************************Write DMA Config Struct****************************/ -cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = -{ - .retrigger = CY_DMA_RETRIG_4CYC, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 2L, - .dstXincrement = 0L, - .xCount = 10UL, - .srcYincrement = 10L, - .dstYincrement = 0L, - .yCount = 2UL, - .nextDescriptor = NULL -}; - -cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL -}; - - - -/***************UDB Config code *****************/ - -#define CY_CFG_BASE_ADDR_COUNT 12u - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) - #define CYPACKED - #define CYPACKED_ATTR __attribute__ ((packed)) - #define CY_CFG_UNUSED __attribute__ ((unused)) - - -#elif defined(__ICCARM__) - #include - - #define CYPACKED __packed - #define CYPACKED_ATTR - #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") - - -#else - #error Unsupported toolchain -#endif - - -#ifndef CYCODE - #define CYCODE -#endif -#ifndef CYFAR - #define CYFAR -#endif - - -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) -{ - (void)memset(s, 0, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} - -CYPACKED typedef struct -{ - uint8 offset; - uint8 value; -} CYPACKED_ATTR cy_cfg_addrvalue_t; - - -/******************************************************************************* -* Function Name: cfg_write_bytes32 -******************************************************************************** -* Summary: -* This function is used for setting up the chip configuration areas that -* contain relatively sparse data. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ - -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) -{ - /* For 32-bit little-endian architectures */ - uint32 i, j = 0u; - for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) - { - uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; - baseAddr &= 0xFFFFFF00u; - while (count != 0u) - { - CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); - j++; - count--; - } - } -} - -static const uint32 CYCODE cy_cfg_addr_table[] = -{ - 0x40340002u, /* Base address: 0x40340000 Count: 2 */ - 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ - 0x40340301u, /* Base address: 0x40340300 Count: 1 */ - 0x40340405u, /* Base address: 0x40340400 Count: 5 */ - 0x40342466u, /* Base address: 0x40342400 Count: 102 */ - 0x40342632u, /* Base address: 0x40342600 Count: 50 */ - 0x4034282Bu, /* Base address: 0x40342800 Count: 43 */ - 0x40342A5Eu, /* Base address: 0x40342A00 Count: 94 */ - 0x40347005u, /* Base address: 0x40347000 Count: 5 */ - 0x40347102u, /* Base address: 0x40347100 Count: 2 */ - 0x40347202u, /* Base address: 0x40347200 Count: 2 */ - 0x40347804u, /* Base address: 0x40347800 Count: 4 */ -}; - -static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = -{ - {0x18u, 0xFFu}, - {0x1Du, 0x01u}, - {0x00u, 0x10u}, - {0x04u, 0x88u}, - {0x09u, 0x02u}, - {0x10u, 0x10u}, - {0x14u, 0x88u}, - {0x1Du, 0x01u}, - {0x20u, 0x10u}, - {0x24u, 0x88u}, - {0x28u, 0x10u}, - {0x2Cu, 0x88u}, - {0x15u, 0x40u}, - {0x04u, 0x07u}, - {0x14u, 0x47u}, - {0x1Cu, 0x2Fu}, - {0x20u, 0x03u}, - {0x28u, 0x0Fu}, - {0x01u, 0x8Eu}, - {0x03u, 0x70u}, - {0x05u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Du, 0x04u}, - {0x11u, 0x60u}, - {0x13u, 0x80u}, - {0x15u, 0x04u}, - {0x18u, 0x02u}, - {0x19u, 0xD0u}, - {0x1Bu, 0x23u}, - {0x21u, 0x01u}, - {0x23u, 0x20u}, - {0x25u, 0xD0u}, - {0x27u, 0x2Fu}, - {0x2Du, 0x10u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x48u}, - {0x30u, 0x01u}, - {0x31u, 0xE0u}, - {0x34u, 0x02u}, - {0x35u, 0x1Fu}, - {0x3Bu, 0x02u}, - {0x3Du, 0x22u}, - {0x3Eu, 0x11u}, - {0x40u, 0x52u}, - {0x41u, 0x01u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x5Cu, 0x04u}, - {0x5Du, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x86u, 0x20u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x20u}, - {0x90u, 0xBAu}, - {0x92u, 0x04u}, - {0x94u, 0x08u}, - {0x96u, 0x11u}, - {0x98u, 0x78u}, - {0x9Au, 0x02u}, - {0x9Cu, 0x18u}, - {0x9Eu, 0xC4u}, - {0xA3u, 0x01u}, - {0xA4u, 0x08u}, - {0xA6u, 0x10u}, - {0xA8u, 0xFEu}, - {0xABu, 0x01u}, - {0xADu, 0x02u}, - {0xAEu, 0x20u}, - {0xB0u, 0x01u}, - {0xB2u, 0x18u}, - {0xB3u, 0x01u}, - {0xB4u, 0x06u}, - {0xB5u, 0x02u}, - {0xB6u, 0xE0u}, - {0xBAu, 0x08u}, - {0xBFu, 0x14u}, - {0xC0u, 0x52u}, - {0xC1u, 0x01u}, - {0xC4u, 0x06u}, - {0xC5u, 0xB0u}, - {0xC7u, 0x40u}, - {0xC8u, 0x22u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xD4u, 0xDEu}, - {0xD5u, 0x40u}, - {0xD6u, 0x4Bu}, - {0xD7u, 0x04u}, - {0xDCu, 0x0Cu}, - {0xDDu, 0x04u}, - {0xDEu, 0x0Cu}, - {0xDFu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x00u, 0x08u}, - {0x04u, 0x01u}, - {0x05u, 0x07u}, - {0x08u, 0x01u}, - {0x0Au, 0x08u}, - {0x0Fu, 0x05u}, - {0x12u, 0x01u}, - {0x14u, 0x10u}, - {0x16u, 0x01u}, - {0x18u, 0x01u}, - {0x1Au, 0x04u}, - {0x1Eu, 0x0Eu}, - {0x1Fu, 0x06u}, - {0x20u, 0x01u}, - {0x22u, 0x02u}, - {0x25u, 0x03u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x01u}, - {0x32u, 0x10u}, - {0x36u, 0x0Fu}, - {0x37u, 0x07u}, - {0x3Cu, 0x80u}, - {0x40u, 0x36u}, - {0x41u, 0x01u}, - {0x42u, 0x20u}, - {0x44u, 0x05u}, - {0x45u, 0xFBu}, - {0x46u, 0xC0u}, - {0x47u, 0xE0u}, - {0x48u, 0x2Bu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x02u}, - {0x4Fu, 0x0Cu}, - {0x50u, 0x08u}, - {0x51u, 0x10u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x65u, 0x08u}, - {0x68u, 0xC0u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x71u, 0x10u}, - {0x72u, 0x50u}, - {0x73u, 0xA8u}, - {0x82u, 0x08u}, - {0x84u, 0x07u}, - {0x86u, 0xF8u}, - {0x8Cu, 0x0Eu}, - {0x8Eu, 0xD1u}, - {0x92u, 0x21u}, - {0x96u, 0x01u}, - {0x98u, 0x04u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x04u}, - {0xA4u, 0xB9u}, - {0xA6u, 0x06u}, - {0xA8u, 0x89u}, - {0xAAu, 0x72u}, - {0xAEu, 0x60u}, - {0xB0u, 0x80u}, - {0xB2u, 0x7Fu}, - {0xBAu, 0x08u}, - {0xBCu, 0x08u}, - {0xBEu, 0x01u}, - {0xC0u, 0x42u}, - {0xC1u, 0x05u}, - {0xC4u, 0x06u}, - {0xC6u, 0x40u}, - {0xC7u, 0xB0u}, - {0xC8u, 0x28u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x03u, 0x40u}, - {0x09u, 0x10u}, - {0x0Cu, 0x2Au}, - {0x0Du, 0x30u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x0Au}, - {0x15u, 0x30u}, - {0x17u, 0x0Au}, - {0x1Du, 0x0Cu}, - {0x1Eu, 0x14u}, - {0x20u, 0x02u}, - {0x22u, 0x29u}, - {0x23u, 0x35u}, - {0x24u, 0x30u}, - {0x25u, 0x03u}, - {0x28u, 0x03u}, - {0x29u, 0x20u}, - {0x2Au, 0x28u}, - {0x2Cu, 0x0Cu}, - {0x2Du, 0x0Au}, - {0x2Fu, 0x30u}, - {0x30u, 0x01u}, - {0x31u, 0x70u}, - {0x32u, 0x30u}, - {0x33u, 0x0Cu}, - {0x34u, 0x0Cu}, - {0x35u, 0x03u}, - {0x36u, 0x02u}, - {0x38u, 0x28u}, - {0x39u, 0x28u}, - {0x3Eu, 0x55u}, - {0x3Fu, 0x15u}, - {0x40u, 0x42u}, - {0x41u, 0x05u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x7Fu}, - {0x5Cu, 0x04u}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x82u, 0x01u}, - {0x86u, 0x01u}, - {0x8Au, 0x02u}, - {0x8Cu, 0x01u}, - {0x98u, 0x01u}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x01u}, - {0xA8u, 0x01u}, - {0xACu, 0x03u}, - {0xAEu, 0x04u}, - {0xB4u, 0x07u}, - {0xB6u, 0x07u}, - {0xBCu, 0xA0u}, - {0xC0u, 0x42u}, - {0xC1u, 0x05u}, - {0xC4u, 0x06u}, - {0xC7u, 0xB4u}, - {0xC8u, 0x30u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Fu}, - {0xDEu, 0x0Fu}, - {0xDFu, 0x04u}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x28u, 0x10u}, - {0xA8u, 0xE1u}, - {0xACu, 0x52u}, - {0xB0u, 0xAAu}, - {0xB4u, 0x01u}, - {0xA8u, 0xA1u}, - {0xE8u, 0x02u}, - {0xA8u, 0x87u}, - {0xACu, 0x53u}, - {0x00u, 0x01u}, - {0x10u, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x01u}, -}; - - - -CYPACKED typedef struct -{ -void *address; -uint16 size; -} CYPACKED_ATTR cfg_memset_t; - - -CYPACKED typedef struct -{ - void *dest; - const void *src; - size_t size; -} CYPACKED_ATTR cfg_memcpy_t; - -static const cfg_memset_t CYCODE cfg_memset_list[] = -{ - /* address, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), 116u}, -}; - -/* UDB_UDBPAIR4_UDBSNG0 Address: CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG0_VAL[] = -{ - 0x42u, 0x00u, 0x25u, 0x0Au, 0x50u, 0x00u, 0x08u, 0x00u, 0x48u, 0x00u, 0x10u, 0x05u, 0x04u, 0x00u, 0x00u, 0x00u, - 0x61u, 0x00u, 0x06u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x00u, 0x41u, 0x0Cu, 0x26u, 0x03u, 0x00u, 0x00u, 0x04u, 0x0Au, - 0x48u, 0x05u, 0x10u, 0x00u, 0x40u, 0x00u, 0x18u, 0x05u, 0x04u, 0x00u, 0x00u, 0x05u, 0x02u, 0x00u, 0x00u, 0x00u, - 0x07u, 0x0Cu, 0x40u, 0x03u, 0x07u, 0x00u, 0x38u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x22u, 0x00u, 0x44u, 0x05u, - 0x42u, 0x05u, 0x00u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x71u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR3_UDBSNG1 Address: CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG1_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x88u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x02u, 0x88u, 0x01u, 0x00u, - 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x88u, 0x03u, 0x00u, 0x01u, 0xBCu, 0x00u, 0x40u, 0x39u, 0x22u, 0x46u, 0xC5u, - 0x00u, 0x00u, 0x04u, 0x01u, 0x28u, 0xA2u, 0x56u, 0x4Du, 0x51u, 0x00u, 0x2Eu, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, - 0x00u, 0x60u, 0x00u, 0x80u, 0x1Fu, 0x00u, 0x60u, 0x1Fu, 0x00u, 0x80u, 0x20u, 0x00u, 0x20u, 0x80u, 0x40u, 0x05u, - 0x64u, 0x03u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x06u, 0x11u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0xA0u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x73u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x00u, 0x00u, 0x40u, 0x40u, 0x10u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = -{ - 0x04u, 0x20u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x79u, 0x00u, 0x82u, 0x11u, 0x48u, 0x2Eu, 0x95u, - 0x09u, 0x08u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x8Du, 0x00u, 0x72u, 0x20u, 0x08u, 0x00u, 0x00u, - 0x2Eu, 0x00u, 0x11u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, - 0x38u, 0xE0u, 0x02u, 0x07u, 0x04u, 0x18u, 0x01u, 0x07u, 0x00u, 0x00u, 0x82u, 0x22u, 0x82u, 0xAAu, 0x14u, 0x00u, - 0x41u, 0x05u, 0x63u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0xF0u, 0x21u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x08u, 0x03u, 0x08u, 0x00u, 0x18u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x58u, 0xECu, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR0_UDBSNG0 Address: CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG0_VAL[] = -{ - 0x95u, 0x08u, 0x6Au, 0x00u, 0x26u, 0x62u, 0xD9u, 0x9Du, 0x82u, 0x00u, 0x40u, 0x42u, 0x00u, 0x00u, 0x80u, 0x00u, - 0x00u, 0x00u, 0x90u, 0x32u, 0x4Eu, 0x00u, 0xB1u, 0x01u, 0x92u, 0x00u, 0x6Du, 0x00u, 0x00u, 0xB5u, 0x04u, 0x4Au, - 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0xF2u, 0x00u, 0x09u, 0x00u, 0x66u, 0x01u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x3Fu, 0xE0u, 0xC0u, 0x1Fu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x2Au, 0x0Au, 0x2Au, 0x0Au, 0x00u, 0x00u, - 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR1_UDBSNG0 Address: CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG0_VAL[] = -{ - 0x00u, 0x01u, 0x00u, 0x00u, 0xABu, 0x00u, 0x00u, 0x03u, 0x2Bu, 0xC9u, 0x54u, 0x12u, 0x02u, 0x00u, 0x00u, 0x40u, - 0xAAu, 0x00u, 0x01u, 0x01u, 0x81u, 0x05u, 0x2Au, 0xBAu, 0xAAu, 0x00u, 0x00u, 0x40u, 0x08u, 0xB3u, 0x00u, 0x4Cu, - 0x04u, 0x20u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x01u, 0x10u, 0x01u, 0x00u, 0x80u, 0x20u, 0xB1u, 0x00u, 0x04u, - 0x19u, 0x00u, 0x07u, 0x80u, 0x61u, 0x00u, 0x80u, 0x7Fu, 0x2Au, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x55u, 0x04u, - 0x24u, 0x06u, 0x00u, 0x00u, 0x01u, 0x0Eu, 0x00u, 0xC4u, 0x31u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, - 0x40u, 0x03u, 0x00u, 0x10u -}; - -/* UDB_UDBPAIR0_UDBSNG1 Address: CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG1_VAL[] = -{ - 0x00u, 0x00u, 0x80u, 0x03u, 0x7Bu, 0x04u, 0x80u, 0x00u, 0x33u, 0x1Cu, 0xCCu, 0x00u, 0x04u, 0x03u, 0x00u, 0x00u, - 0x8Au, 0x00u, 0x71u, 0x04u, 0xB9u, 0x00u, 0x42u, 0x0Cu, 0x00u, 0x03u, 0x20u, 0x00u, 0x00u, 0x14u, 0x00u, 0x00u, - 0x00u, 0x00u, 0xA0u, 0x03u, 0x0Au, 0x1Cu, 0xD0u, 0x00u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, - 0x00u, 0x07u, 0x00u, 0x18u, 0xF8u, 0x00u, 0x07u, 0x00u, 0x80u, 0x08u, 0x20u, 0x00u, 0x20u, 0x00u, 0x40u, 0x05u, - 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x0Bu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u -}; - -/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x25u, 0x40u, 0x13u, 0x30u, - 0x54u, 0xF1u, 0x1Fu, 0xF6u, 0xF5u, 0x33u, 0x05u, 0x12u, 0x33u, 0x51u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x21u, 0x32u, 0x75u, 0x37u, 0x23u, 0xF5u, 0x51u, 0x14u, 0x54u, 0x32u, 0x11u, 0x41u, - 0x33u, 0x51u, 0xFFu, 0x0Fu, 0x5Fu, 0xFFu, 0x2Fu, 0x22u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x14u, 0x01u, 0x01u, 0x11u, 0x10u, 0x44u, 0x53u, 0x33u, 0x14u, 0x11u, 0x40u, 0x01u, 0x01u, 0x33u, 0x4Cu, 0x04u, - 0x11u, 0x01u, 0x3Bu, 0x01u, 0x01u, 0x10u, 0x11u, 0x00u, 0x62u, 0x10u, 0x11u, 0x13u, 0x11u, 0x19u, 0x11u, 0x16u, - 0x09u, 0x73u, 0x10u, 0x66u, 0x11u, 0x11u, 0x11u, 0x11u, 0x12u, 0x11u, 0x11u, 0x14u, 0x11u, 0x14u, 0x11u, 0x11u -}; - -/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0xF5u, 0x5Fu, - 0x22u, 0xFFu, 0x04u, 0xF1u, 0x56u, 0x63u, 0x61u, 0x12u, 0xF7u, 0x04u, 0x37u, 0x16u, 0x63u, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, 0x52u, 0x75u, 0x60u, 0x45u, 0x04u, 0x14u, 0x31u, 0x44u, 0x12u, 0x76u, 0x13u, - 0x51u, 0x73u, 0x70u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x25u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x00u, 0xF5u, - 0x4Fu, 0x06u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x03u, 0x06u, 0x00u, 0xA1u, 0x06u, 0x0Cu, 0x36u, 0xF5u, 0x0Du, 0x10u, 0xF3u, 0x01u, 0x00u, 0xFFu, 0x3Fu, 0x0Fu, - 0x15u, 0x00u, 0xFBu, 0x01u, 0x03u, 0x10u, 0x11u, 0x4Cu, 0x11u, 0x52u, 0x90u, 0xC1u, 0xD2u, 0x15u, 0xC3u, 0x5Fu, - 0x36u, 0x0Fu, 0x23u, 0x3Cu, 0x00u, 0x11u, 0x15u, 0x11u, 0x11u, 0x31u, 0x14u, 0x1Fu, 0x11u, 0x8Fu, 0x11u, 0xC1u -}; - -/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x11u, 0xFFu, 0x45u, - 0xFFu, 0x5Fu, 0xF5u, 0x44u, 0x4Fu, 0x36u, 0x43u, 0x73u, 0x13u, 0xFFu, 0x23u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x6Fu, 0x24u, 0x45u, 0x44u, 0x1Fu, 0x63u, 0x17u, 0x1Fu, 0xFFu, 0xFFu, 0x4Fu, 0xFFu, - 0x13u, 0x14u, 0x63u, 0x07u, 0x55u, 0xF7u, 0xF7u, 0x72u, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x05u, 0x2Fu, 0x10u, - 0xF0u, 0xF3u, 0xF0u, 0x10u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x01u, 0x00u, 0x8Du, 0x16u, 0x21u, 0x0Fu, 0x1Fu, 0x1Fu, 0xAFu, 0xB0u, 0x0Fu, 0xADu, 0x00u, 0xFFu, 0x4Fu, 0x00u, - 0x05u, 0x0Du, 0x0Au, 0x41u, 0x00u, 0xAAu, 0x01u, 0xF1u, 0xC4u, 0x10u, 0xF0u, 0x04u, 0xF3u, 0x1Fu, 0xC4u, 0x3Fu, - 0x1Fu, 0x03u, 0xF0u, 0xF0u, 0x88u, 0x01u, 0x3Fu, 0x01u, 0x11u, 0xB1u, 0x57u, 0x81u, 0x11u, 0xC1u, 0x1Du, 0x14u -}; - -/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x36u, 0x34u, 0x32u, - 0x06u, 0x14u, 0xF5u, 0x46u, 0x43u, 0xF6u, 0xF3u, 0x43u, 0xFFu, 0x37u, 0x5Fu, 0xFFu, 0x5Fu, 0xF2u, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x45u, 0xF4u, 0x37u, 0x40u, 0xF0u, 0xF2u, 0x7Fu, 0xF4u, 0xF4u, 0xFFu, 0xF3u, 0x03u, - 0x73u, 0xF0u, 0x77u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF2u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x00u, 0x06u, 0xBFu, 0x17u, 0x11u, 0x7Fu, 0x71u, 0x11u, 0x5Fu, 0x70u, 0x5Fu, 0xFFu, 0x06u, 0xFFu, 0x0Fu, 0x07u, - 0x7Fu, 0x3Fu, 0x0Fu, 0xF6u, 0x00u, 0x2Fu, 0x7Fu, 0x48u, 0xF4u, 0x30u, 0xB0u, 0x5Fu, 0x11u, 0x0Fu, 0x91u, 0xFFu, - 0x1Fu, 0x0Au, 0xF3u, 0xFBu, 0x15u, 0x11u, 0x1Fu, 0xA1u, 0x11u, 0x81u, 0x11u, 0x12u, 0x14u, 0x11u, 0x1Fu, 0x31u -}; - -/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x17u, 0xF5u, 0x65u, - 0x77u, 0x77u, 0x7Fu, 0x05u, 0x14u, 0xF4u, 0x5Fu, 0x0Fu, 0x1Fu, 0x5Fu, 0x43u, 0x5Fu, 0xFFu, 0xF2u, 0xFFu, 0x05u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x23u, 0x7Fu, 0x52u, 0x64u, 0x55u, 0x75u, 0xFFu, 0xFFu, 0xF5u, 0xFFu, 0x11u, 0xFFu, - 0x1Fu, 0x52u, 0x13u, 0x40u, 0xFFu, 0xF3u, 0xFFu, 0xF5u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x25u, 0x00u, 0x30u, - 0x00u, 0x00u, 0x00u, 0x13u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x00u, 0x81u, 0x1Fu, 0x11u, 0x11u, 0x5Fu, 0x91u, 0x10u, 0xFFu, 0x33u, 0x0Fu, 0xFFu, 0x30u, 0xFFu, 0x4Fu, 0x31u, - 0x1Fu, 0xFFu, 0x06u, 0x06u, 0x0Au, 0x28u, 0x08u, 0x66u, 0x11u, 0x10u, 0xF9u, 0x17u, 0x20u, 0x3Fu, 0x10u, 0x2Fu, - 0x1Fu, 0x00u, 0xF1u, 0xF6u, 0x1Bu, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x33u, 0x31u, 0x11u, 0x17u, 0x11u, 0x11u, 0x1Bu -}; - -/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, 0x43u, 0xFFu, 0x30u, - 0xF0u, 0x22u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Fu, 0x5Fu, 0x53u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x42u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0xF3u, 0x1Fu, 0x15u, 0x11u, 0x13u, 0x13u, 0x41u, 0xF1u, 0x31u, 0x3Fu, - 0x1Fu, 0x53u, 0x03u, 0xF0u, 0x4Fu, 0xFFu, 0x2Fu, 0x13u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x01u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x23u, 0x11u, 0x1Fu, 0x11u, 0x31u, 0x7Fu, 0x61u, 0x17u, 0xBFu, 0x8Cu, 0x8Fu, 0xFFu, 0x39u, 0x1Fu, 0x95u, 0x1Cu, - 0x1Fu, 0xFFu, 0x6Cu, 0x7Fu, 0x33u, 0x1Fu, 0x7Fu, 0xFFu, 0x44u, 0x13u, 0x11u, 0x11u, 0x13u, 0x81u, 0x7Cu, 0x12u, - 0x11u, 0xCCu, 0x16u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI0_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI1_VAL[] = -{ - 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x20u, 0xF1u, 0x0Fu, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x10u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI2_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x0Au, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Au, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x13u, 0x0Au, 0x00u, 0x0Du, 0x16u, 0x1Fu, 0x11u, 0x1Fu, - 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0xF4u, 0xF0u, 0x10u, 0x10u, 0x50u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x01u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x12u, 0x11u, 0xBFu, 0x11u, 0x11u, 0x1Du, 0x01u, 0x11u, 0x12u, 0x11u, 0x11u, 0x01u, 0xF1u, 0x10u, - 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, - 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI3_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x03u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI4_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI5_VAL[] = -{ - 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI6_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, 0x03u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI7_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x0Au, 0x1Fu, 0x08u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x02u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, 0x10u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u -}; - -/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI8_VAL[] = -{ - 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0xF0u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x1Du, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI9_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI10_VAL[] = -{ - 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x0Cu, 0x1Fu, 0x03u, 0x06u, 0x1Fu, 0x1Fu, 0x05u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, 0x00u, 0xF0u, 0x00u, 0x00u, 0x00u, 0xFFu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI11_VAL[] = -{ - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u -}; - -static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), BS_UDB_UDBPAIR4_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), BS_UDB_UDBPAIR3_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), BS_UDB_UDBPAIR0_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), BS_UDB_UDBPAIR1_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), BS_UDB_UDBPAIR0_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, -}; - -void SDIO_Host_Config_TriggerMuxes(void) -{ - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); - - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); -} - -void SDIO_Host_Config_UDBs(void) -{ - size_t i; - - /* Power on the UDB array */ - CY_SET_REG32(0x402101F0u, 0x05FA0003u); - - /* Zero out critical memory blocks before beginning configuration */ - for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - { - const cfg_memset_t *ms = &cfg_memset_list[i]; - CYMEMZERO(ms->address, ms->size); - } - - /* Copy device configuration data into registers */ - for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) - { - const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; - CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); - } - - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - - /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ - CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); - - /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C4C4Cu); - - /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x4C4C444Cu); - - /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x044C4C44u); - - /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C4Cu); - - /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x004C4C44u); - - /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x0C4C040Cu); - - /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x008C8C8Cu); - - /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - - /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x4C4C444Cu); - - /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x008C808Cu); - - /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x8C8C0404u); - - /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x048F808Fu); - - /* Enable UDB array and digital routing */ - CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); -} - -#if defined(__cplusplus) -} -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h deleted file mode 100644 index 39febda573..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ /dev/null @@ -1,931 +0,0 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.h -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#if !defined(CY_SDIO_CFG_H) -#define CY_SDIO_CFG_H - -#include - -#include "cy_dma.h" -#include "cy_sysclk.h" -#include "cy_trigmux.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u -#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u -#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u -#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu -#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u - -#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u -#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u - -#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu -#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu - -#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu -#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu - -#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu -#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu -#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu -#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu -#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu -#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu -#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu -#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu - -#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u -#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u -#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u -#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u - -#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u -#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u -#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u -#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u -#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u -#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u - - -#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u -#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u -#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u -#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u -#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u -#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u - - -#define CYDEV_UDB_DSI0_BASE 0x40346000u -#define CYDEV_UDB_DSI1_BASE 0x40346080u -#define CYDEV_UDB_DSI2_BASE 0x40346100u -#define CYDEV_UDB_DSI3_BASE 0x40346180u -#define CYDEV_UDB_DSI4_BASE 0x40346200u -#define CYDEV_UDB_DSI5_BASE 0x40346280u -#define CYDEV_UDB_DSI6_BASE 0x40346300u -#define CYDEV_UDB_DSI7_BASE 0x40346380u -#define CYDEV_UDB_DSI8_BASE 0x40346400u -#define CYDEV_UDB_DSI9_BASE 0x40346480u -#define CYDEV_UDB_DSI10_BASE 0x40346500u -#define CYDEV_UDB_DSI11_BASE 0x40346580u - -#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u - -/*************Defines for UDBs from Creator*****************************/ -/***********These come for cyfitter.h**********************************/ - -/* TFT_DMA */ -#define TFT_DMA_DW__BLOCK_HW DW0 -#define TFT_DMA_DW__BLOCK_NUMBER 0u -#define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2 -#define TFT_DMA_DW__CHANNEL_NUMBER 2u -#define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2 -#define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2 - -/* TFT_CTRL */ -#define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u -#define TFT_CTRL_Sync_ctrl_reg__0__POS 0 -#define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u -#define TFT_CTRL_Sync_ctrl_reg__1__POS 1 -#define TFT_CTRL_Sync_ctrl_reg__2__MASK 0x04u -#define TFT_CTRL_Sync_ctrl_reg__2__POS 2 -#define TFT_CTRL_Sync_ctrl_reg__3__MASK 0x08u -#define TFT_CTRL_Sync_ctrl_reg__3__POS 3 -#define TFT_CTRL_Sync_ctrl_reg__4__MASK 0x10u -#define TFT_CTRL_Sync_ctrl_reg__4__POS 4 -#define TFT_CTRL_Sync_ctrl_reg__5__MASK 0x20u -#define TFT_CTRL_Sync_ctrl_reg__5__POS 5 -#define TFT_CTRL_Sync_ctrl_reg__6__MASK 0x40u -#define TFT_CTRL_Sync_ctrl_reg__6__POS 6 -#define TFT_CTRL_Sync_ctrl_reg__7__MASK 0x80u -#define TFT_CTRL_Sync_ctrl_reg__7__POS 7 -#define TFT_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG 0x4034192Cu -#define TFT_CTRL_Sync_ctrl_reg__CONTROL_REG 0x4034172Cu -#define TFT_CTRL_Sync_ctrl_reg__CONTROL_ST_REG 0x4034032Cu -#define TFT_CTRL_Sync_ctrl_reg__COUNT_REG 0x4034172Cu -#define TFT_CTRL_Sync_ctrl_reg__COUNT_ST_REG 0x4034032Cu -#define TFT_CTRL_Sync_ctrl_reg__MASK 0xFFu -#define TFT_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG 0x4034042Cu -#define TFT_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG 0x4034042Cu -#define TFT_CTRL_Sync_ctrl_reg__PERIOD_REG 0x4034182Cu -#define TFT_CTRL_Sync_ctrl_reg__RC_CFG0 0x40342ADCu -#define TFT_CTRL_Sync_ctrl_reg__RC_CFG1 0x40342AE0u -#define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u -#define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u - -/* SDIO_HOST */ -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x4034001Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x4034101Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x4034111Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x4034011Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x4034121Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x4034131Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x403426C0u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x403426C4u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x403426C8u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x403426CCu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x403426D0u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x403426E4u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x403426E8u -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x403426ECu -#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x403426F0u -#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x4034021Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x4034141Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x4034151Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__MSK_DP_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__PER_DP_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__32BIT_PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341720u -#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x40342854u -#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x40342858u -#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341620u -#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_REG 0x40341620u -#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341820u -#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x40342854u -#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x40342858u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340320u -#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341620u -#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340018u -#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341018u -#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341118u -#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340118u -#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341218u -#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341318u -#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341918u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342640u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342644u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342648u -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034264Cu -#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342650u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342664u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342668u -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034266Cu -#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342670u -#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340218u -#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341418u -#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341518u -#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034265Cu -#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342660u -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034171Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x403426D4u -#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x403426D8u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_REG 0x4034161Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_REG 0x4034161Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034181Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034041Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x403426DCu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x403426E0u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x403426D4u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x403426D8u -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034191Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034031Cu -#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034161Cu -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u -#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u -#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u -#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u -#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u -#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0 -#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u -#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1 -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u -#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2 -#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u -#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3 -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u -#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4 -#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u -#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6 -#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u -#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7 -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340314u -#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341714u -#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340314u -#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu -#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341814u -#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x403424D4u -#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x403424D8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341000u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340100u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341300u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341900u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342040u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342044u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342048u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034204Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342050u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342064u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342068u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034206Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342070u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340200u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341400u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341500u -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034205Cu -#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342060u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341004u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340104u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341304u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403420C0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403420C4u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403420C8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403420CCu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403420D0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403420E4u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403420E8u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403420ECu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403420F0u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340204u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341504u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__MSK_DP_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__PER_DP_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341010u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340110u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341310u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341910u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342440u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342444u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342448u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x4034244Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342450u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342464u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342468u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x4034246Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342470u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340210u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341410u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341510u -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x4034245Cu -#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342460u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x40340014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x40341014u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x40341114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x40340114u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x40341214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x40341314u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x403424C0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x403424C4u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x403424C8u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x403424CCu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x403424D0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x403424E4u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x403424E8u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x403424ECu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x403424F0u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x40340214u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x40341414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x40341514u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341028u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341128u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341228u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341328u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341528u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340028u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341028u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341128u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340128u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341228u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341328u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341928u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342A40u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342A44u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342A48u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x40342A4Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342A50u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342A64u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342A68u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x40342A6Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342A70u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340228u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341528u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__MSK_DP_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__PER_DP_AUX_CTL_REG 0x40340428u -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x40342A5Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342A60u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x4034002Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x4034102Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x4034112Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x4034012Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x4034122Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x4034132Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x4034192Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x40342AC0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x40342AC4u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x40342AC8u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x40342ACCu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x40342AD0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x40342AE4u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x40342AE8u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x40342AECu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x40342AF0u -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x4034022Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x4034142Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x4034152Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x4034042Cu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x40342ADCu -#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x40342AE0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341020u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340120u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341320u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341920u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342840u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342844u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342848u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034284Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342850u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342864u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342868u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034286Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342870u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340220u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341520u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340420u -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034285Cu -#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342860u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x40341024u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x40341124u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x40341224u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x40341324u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x40341424u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x40341524u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x40340024u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x40341024u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x40341124u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x40340124u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x40341224u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x40341324u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x40341924u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403428C0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403428C4u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403428C8u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403428CCu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403428D0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403428E4u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403428E8u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403428ECu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403428F0u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x40340224u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x40341424u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x40341524u -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403428DCu -#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403428E0u -#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x4034000Cu -#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x4034100Cu -#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x4034110Cu -#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x4034010Cu -#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x4034120Cu -#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x4034130Cu -#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403422C0u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403422C4u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403422C8u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403422CCu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403422D0u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403422E4u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403422E8u -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403422ECu -#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403422F0u -#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x4034020Cu -#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x4034140Cu -#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x4034150Cu -#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403422DCu -#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403422E0u -#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x4034160Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x4034160Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x4034180Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403422DCu -#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403422E0u -#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403422D4u -#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403422D8u -#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x4034190Cu -#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x4034160Cu -#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u -#define SDIO_HOST_bSDIO_StatusReg__0__POS 0 -#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u -#define SDIO_HOST_bSDIO_StatusReg__1__POS 1 -#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341614u -#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u -#define SDIO_HOST_bSDIO_StatusReg__2__POS 2 -#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u -#define SDIO_HOST_bSDIO_StatusReg__3__POS 3 -#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341614u -#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u -#define SDIO_HOST_bSDIO_StatusReg__6__POS 6 -#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu -#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341814u -#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340414u -#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x403424DCu -#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x403424E0u -#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x403424D4u -#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x403424D8u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341914u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340314u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340314u -#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341614u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x40340008u -#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x40341008u -#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x40341108u -#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x40340108u -#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x40341208u -#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x40341308u -#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x40342240u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x40342244u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x40342248u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x4034224Cu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x40342250u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x40342264u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x40342268u -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x4034226Cu -#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x40342270u -#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x40340208u -#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x40341408u -#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x40341508u -#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x4034225Cu -#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x40342260u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x40341908u -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x40340308u -#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x40341708u -#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x40340308u -#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x40340408u -#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x40341808u -#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x4034225Cu -#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x40342260u -#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x40342254u -#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x40342258u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341704u -#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x403420D4u -#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x403420D8u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341604u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341804u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340404u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x403420DCu -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x403420E0u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x403420D4u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x403420D8u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341904u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340304u -#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341604u -#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0 -#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u -#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1 -#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u -#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1 -#define SDIO_HOST_Internal_Clock__DIV_IDX 0 -#define SDIO_HOST_Internal_Clock__DIV_NUM 0 -#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT -#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1 -#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u -#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3 -#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u -#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3 -#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0 -#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u -#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0 -#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u -#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0 -#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1 -#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u -#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1 -#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u -#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 - - -/***************************CMD DMA***************************************/ -#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) -#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) -#define SDIO_HOST_CMD_DMA_HW (DW0) -#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_CMD_DMA_PRIORITY (1u) -#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; - -/***************************Read DMA***************************************/ -#define SDIO_HOST_Read_DMA_DW_BLOCK (1u) -#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) -#define SDIO_HOST_Read_DMA_HW (DW1) -#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Read_DMA_PRIORITY (0u) -#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Read_DMA_PREEMPTABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; - -/***************************Resp DMA***************************************/ -#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) -#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) -#define SDIO_HOST_Resp_DMA_HW (DW0) -#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Resp_DMA_PRIORITY (1u) -#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; - -/***************************Write DMA***************************************/ -#define SDIO_HOST_Write_DMA_DW_BLOCK (1u) -#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) -#define SDIO_HOST_Write_DMA_HW (DW1) -#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) - -/* Channel settings */ -#define SDIO_HOST_Write_DMA_PRIORITY (0u) -#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) -#define SDIO_HOST_Write_DMA_PREEMPTABLE (false) - -extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; - -/***************************SDIO Clock**************************************/ -/* The peripheral clock divider number */ -#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0) -/* The peripheral clock divider type */ -#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) - -/*Function for configuring TriggerMuxes*/ -void SDIO_Host_Config_TriggerMuxes(void); - -/*Function for configuring UDBs*/ -void SDIO_Host_Config_UDBs(void); - -/* SDIO_HOST_Read_Int */ -#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Read_Int__INTC_NUMBER 69u -#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Read_Int_INTC_NUMBER 69u - -/* SDIO_HOST_sdio_int */ -#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_sdio_int__INTC_NUMBER 122u -#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_sdio_int_INTC_NUMBER 122u - -/* SDIO_HOST_Write_Int */ -#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Write_Int__INTC_NUMBER 67u -#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1 -#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u -#define SDIO_HOST_Write_Int_INTC_NUMBER 67u - -#if defined(__cplusplus) -} -#endif - -#endif /* !defined(CY_SDIO_CFG_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.c index 851e751b7a..acd73e3ebd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.c @@ -2,12 +2,12 @@ * \file cybsp.c * * Description: -* Provides initialization code for starting up the hardware contained on the +* Provides initialization code for starting up the hardware contained on the * Cypress board. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif #if defined(__cplusplus) @@ -36,7 +37,7 @@ extern "C" { #endif /* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon +* is executed before entry into deep sleep mode and the first one upon * exit the deep sleep mode. * Doing so minimizes the time spent on low power mode entry and exit. */ @@ -81,6 +82,11 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif @@ -97,8 +103,8 @@ cy_rslt_t cybsp_init(void) #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. */ if (CY_RSLT_SUCCESS == result) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.h index bb83a6b9a8..1ec5ff5a60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -62,7 +59,7 @@ cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) /** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp_types.h index f3b4128582..d32a5f7356 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp_types.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,28 +101,50 @@ extern "C" { */ /** LED 8; User LED1 (orange) */ +#ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) +#endif /** LED 9; User LED2 (red) */ +#ifndef CYBSP_LED9 #define CYBSP_LED9 (P11_1) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_LED_RGB_RED #define CYBSP_LED_RGB_RED (P1_1) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_LED_RGB_GREEN #define CYBSP_LED_RGB_GREEN (P0_5) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_LED_RGB_BLUE #define CYBSP_LED_RGB_BLUE (P7_3) +#endif /** LED 8; User LED1 (orange) */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) +#endif /** LED 9; User LED2 (red) */ +#ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) +#endif /** LED 5: RGB LED - Red; User LED3 */ +#ifndef CYBSP_USER_LED3 #define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +#endif /** LED 5: RGB LED - Green; User LED4 */ +#ifndef CYBSP_USER_LED4 #define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +#endif /** LED 5: RGB LED - Blue; User LED5 */ +#ifndef CYBSP_USER_LED5 #define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +#endif /** LED 8; User LED1 */ +#ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) +#endif /** \} group_bsp_pins_led */ @@ -121,16 +154,26 @@ extern "C" { */ /** Switch 2; User Button 1 */ +#ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) +#endif /** Switch 4; User Button 2 */ +#ifndef CYBSP_SW4 #define CYBSP_SW4 (P1_4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) +#endif /** Switch 4; User Button 2 */ +#ifndef CYBSP_USER_BTN2 #define CYBSP_USER_BTN2 (CYBSP_SW4) +#endif /** Switch 2; User Button 1 */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) +#endif /** \} group_bsp_pins_btn */ @@ -141,76 +184,140 @@ extern "C" { */ /** Pin: WIFI SDIO D0 */ +#ifndef CYBSP_WIFI_SDIO_D0 #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif /** Pin: WIFI SDIO D1 */ +#ifndef CYBSP_WIFI_SDIO_D1 #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif /** Pin: WIFI SDIO D2 */ +#ifndef CYBSP_WIFI_SDIO_D2 #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif /** Pin: WIFI SDIO D3 */ +#ifndef CYBSP_WIFI_SDIO_D3 #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif /** Pin: WIFI SDIO CMD */ +#ifndef CYBSP_WIFI_SDIO_CMD #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif /** Pin: WIFI SDIO CLK */ +#ifndef CYBSP_WIFI_SDIO_CLK #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif /** Pin: WIFI ON */ +#ifndef CYBSP_WIFI_WL_REG_ON #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif /** Pin: WIFI Host Wakeup */ +#ifndef CYBSP_WIFI_HOST_WAKE #define CYBSP_WIFI_HOST_WAKE (P4_1) +#endif /** Pin: BT UART RX */ +#ifndef CYBSP_BT_UART_RX #define CYBSP_BT_UART_RX (P3_0) +#endif /** Pin: BT UART TX */ +#ifndef CYBSP_BT_UART_TX #define CYBSP_BT_UART_TX (P3_1) +#endif /** Pin: BT UART RTS */ +#ifndef CYBSP_BT_UART_RTS #define CYBSP_BT_UART_RTS (P3_2) +#endif /** Pin: BT UART CTS */ +#ifndef CYBSP_BT_UART_CTS #define CYBSP_BT_UART_CTS (P3_3) +#endif /** Pin: BT Power */ +#ifndef CYBSP_BT_POWER #define CYBSP_BT_POWER (P3_4) +#endif /** Pin: BT Host Wakeup */ +#ifndef CYBSP_BT_HOST_WAKE #define CYBSP_BT_HOST_WAKE (P4_0) +#endif /** Pin: BT Device Wakeup */ +#ifndef CYBSP_BT_DEVICE_WAKE #define CYBSP_BT_DEVICE_WAKE (P3_5) +#endif /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_0) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SWO */ +#ifndef CYBSP_SWO #define CYBSP_SWO (P6_4) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P12_0) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P12_1) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P12_2) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P12_4) +#endif /** Host-wake GPIO drive mode */ #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) @@ -226,49 +333,93 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#ifndef CYBSP_A0 +#define CYBSP_A0 (P10_0) +#endif /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#ifndef CYBSP_A1 +#define CYBSP_A1 (P10_1) +#endif /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#ifndef CYBSP_A2 +#define CYBSP_A2 (P10_2) +#endif /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#ifndef CYBSP_A3 +#define CYBSP_A3 (P10_3) +#endif /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#ifndef CYBSP_A4 +#define CYBSP_A4 (P10_4) +#endif /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#ifndef CYBSP_A5 +#define CYBSP_A5 (P10_5) +#endif /** Arduino D0 */ +#ifndef CYBSP_D0 #define CYBSP_D0 (P5_0) +#endif /** Arduino D1 */ +#ifndef CYBSP_D1 #define CYBSP_D1 (P5_1) +#endif /** Arduino D2 */ +#ifndef CYBSP_D2 #define CYBSP_D2 (P5_2) +#endif /** Arduino D3 */ +#ifndef CYBSP_D3 #define CYBSP_D3 (P5_3) +#endif /** Arduino D4 */ +#ifndef CYBSP_D4 #define CYBSP_D4 (P5_4) +#endif /** Arduino D5 */ +#ifndef CYBSP_D5 #define CYBSP_D5 (P5_5) +#endif /** Arduino D6 */ +#ifndef CYBSP_D6 #define CYBSP_D6 (P5_6) +#endif /** Arduino D7 */ +#ifndef CYBSP_D7 #define CYBSP_D7 (P5_7) +#endif /** Arduino D8 */ +#ifndef CYBSP_D8 #define CYBSP_D8 (P7_5) +#endif /** Arduino D9 */ +#ifndef CYBSP_D9 #define CYBSP_D9 (P7_4) +#endif /** Arduino D10 */ +#ifndef CYBSP_D10 #define CYBSP_D10 (P12_3) +#endif /** Arduino D11 */ +#ifndef CYBSP_D11 #define CYBSP_D11 (P12_0) +#endif /** Arduino D12 */ +#ifndef CYBSP_D12 #define CYBSP_D12 (P12_1) +#endif /** Arduino D13 */ +#ifndef CYBSP_D13 #define CYBSP_D13 (P12_2) +#endif /** Arduino D14 */ +#ifndef CYBSP_D14 #define CYBSP_D14 (P6_1) +#endif /** Arduino D15 */ +#ifndef CYBSP_D15 #define CYBSP_D15 (P6_0) +#endif /** \} group_bsp_pins_arduino */ @@ -279,37 +430,69 @@ extern "C" { */ /** Cypress J2 Header pin 1 */ +#ifndef CYBSP_J2_1 #define CYBSP_J2_1 (CYBSP_A0) +#endif /** Cypress J2 Header pin 2 */ +#ifndef CYBSP_J2_2 #define CYBSP_J2_2 (P9_0) +#endif /** Cypress J2 Header pin 3 */ +#ifndef CYBSP_J2_3 #define CYBSP_J2_3 (CYBSP_A1) +#endif /** Cypress J2 Header pin 4 */ +#ifndef CYBSP_J2_4 #define CYBSP_J2_4 (P9_1) +#endif /** Cypress J2 Header pin 5 */ +#ifndef CYBSP_J2_5 #define CYBSP_J2_5 (CYBSP_A2) +#endif /** Cypress J2 Header pin 6 */ +#ifndef CYBSP_J2_6 #define CYBSP_J2_6 (P9_2) +#endif /** Cypress J2 Header pin 7 */ +#ifndef CYBSP_J2_7 #define CYBSP_J2_7 (CYBSP_A3) +#endif /** Cypress J2 Header pin 8 */ +#ifndef CYBSP_J2_8 #define CYBSP_J2_8 (P9_3) +#endif /** Cypress J2 Header pin 9 */ +#ifndef CYBSP_J2_9 #define CYBSP_J2_9 (CYBSP_A4) +#endif /** Cypress J2 Header pin 10 */ +#ifndef CYBSP_J2_10 #define CYBSP_J2_10 (P9_4) +#endif /** Cypress J2 Header pin 11 */ +#ifndef CYBSP_J2_11 #define CYBSP_J2_11 (CYBSP_A5) +#endif /** Cypress J2 Header pin 12 */ +#ifndef CYBSP_J2_12 #define CYBSP_J2_12 (P9_5) +#endif /** Cypress J2 Header pin 13 */ +#ifndef CYBSP_J2_13 #define CYBSP_J2_13 (P10_6) +#endif /** Cypress J2 Header pin 14 */ +#ifndef CYBSP_J2_14 #define CYBSP_J2_14 (P9_6) +#endif /** Cypress J2 Header pin 15 */ +#ifndef CYBSP_J2_15 #define CYBSP_J2_15 (NC) +#endif /** Cypress J2 Header pin 16 */ +#ifndef CYBSP_J2_16 #define CYBSP_J2_16 (NC) +#endif /** \} group_bsp_pins_j2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 4ff5ccb454..7a99d7b707 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index a9d28573c6..b78effb0c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3a0414efa3..61d4a4b17b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197563..2e2b15209a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 0f7f5fe0df..e9a6874e34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 9be3c4aa3b..f0a3d746f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index b405a8b603..51808a1db4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b2ef..7e634e2f31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h index 8dd97ffb7a..0ad244b658 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *

Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/targets.json b/targets/targets.json index 664430e608..704d169b39 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8531,7 +8531,8 @@ "components_add": [ "WHD", "4343W", - "CYW43XXX" + "CYW43XXX", + "UDB_SDIO_P2" ], "supported_form_factors": [ "ARDUINO" @@ -8669,7 +8670,8 @@ "components_add": [ "WHD", "43438", - "CYW43XXX" + "CYW43XXX", + "UDB_SDIO_P2" ], "extra_labels_add": [ "PSOC6_01", @@ -8744,7 +8746,8 @@ "components_add": [ "WHD", "43012", - "CYW43XXX" + "CYW43XXX", + "UDB_SDIO_P12" ], "components_remove": [ "QSPIF"
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.