ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

remove empty lines and redundant variables

pull/6862/head
Qinghao Shi 2018-05-21 18:43:37 +01:00
parent bc03c20408
commit f35ba494ca
7 changed files with 1168 additions and 1171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c
View File

@ -188,7 +188,7 @@ unsigned int smsc9220_read_id(void)
return SMSC9220->ID_REV; return SMSC9220->ID_REV;
} }
// Initiates a soft reset, returns failure or success. // Initiates a soft reset, returns 0 on success, or 1 on failure.
unsigned int smsc9220_soft_reset(void) unsigned int smsc9220_soft_reset(void)
{ {
int timedout; int timedout;
@ -260,18 +260,14 @@ unsigned int smsc9220_check_phy(void)
unsigned int smsc9220_reset_phy(void) unsigned int smsc9220_reset_phy(void)
{ {
unsigned short read; unsigned short read;
int error;
error = 0;
if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
error = 1; return 1;
return error;
} }
read |= (1 << 15); read |= (1 << 15);
if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
error = 1; return 1;
return error;
} }
return 0; return 0;
} }

8
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c
View File

@ -60,14 +60,11 @@ int smsc9220_check_id(void)
int smsc9220_check_macaddress(void) int smsc9220_check_macaddress(void)
{ {
int error;
const unsigned int mac_valid_high = 0xC00A; const unsigned int mac_valid_high = 0xC00A;
const unsigned int mac_valid_low = 0x00F70200; const unsigned int mac_valid_low = 0x00F70200;
unsigned int mac_low; unsigned int mac_low;
unsigned int mac_high; unsigned int mac_high;
error = 0;
// Read current mac address. // Read current mac address.
smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
@ -82,11 +79,10 @@ int smsc9220_check_macaddress(void)
if (mac_high != mac_valid_high || mac_low != mac_valid_low) { if (mac_high != mac_valid_high || mac_low != mac_valid_low) {
error = TRUE; return 1;
return error;
} }
return error; return 0;
} }
void smsc9220_print_mac_registers() void smsc9220_print_mac_registers()

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h
View File

@ -46,7 +46,8 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -106,7 +107,8 @@ typedef struct {
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -164,7 +166,8 @@ typedef struct { //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -311,7 +314,8 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -327,7 +331,8 @@ typedef struct {
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -481,7 +486,8 @@ typedef struct {
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct { // SMSC LAN9220 typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h
View File

@ -46,7 +46,8 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -106,7 +107,8 @@ typedef struct {
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -164,7 +166,8 @@ typedef struct { //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -311,7 +314,8 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -327,7 +331,8 @@ typedef struct {
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -481,7 +486,8 @@ typedef struct {
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct { // SMSC LAN9220 typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h
View File

@ -46,7 +46,8 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -106,7 +107,8 @@ typedef struct {
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -164,7 +166,8 @@ typedef struct { //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -311,7 +314,8 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -327,7 +331,8 @@ typedef struct {
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -481,7 +486,8 @@ typedef struct {
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct { // SMSC LAN9220 typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

18
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h
View File

@ -46,7 +46,8 @@
/* FPGA System Register declaration */ /* FPGA System Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved // [31:2] : Reserved
// [1:0] : LEDs // [1:0] : LEDs
@ -106,7 +107,8 @@ typedef struct {
/* SCC Register declaration */ /* SCC Register declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved // [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT // [0] 1 : REMAP BlockRam to ZBT
@ -164,7 +166,8 @@ typedef struct { //
/* SSP Peripheral declaration */ /* SSP Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved // [31:16] : Reserved
// [15:8] : Serial clock rate // [15:8] : Serial clock rate
@ -311,7 +314,8 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
/* Audio and Touch Screen (I2C) Peripheral declaration */ /* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
union { union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
@ -327,7 +331,8 @@ typedef struct {
/* Audio I2S Peripheral declaration */ /* Audio I2S Peripheral declaration */
/******************************************************************************/ /******************************************************************************/
typedef struct { typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */ /*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h> __IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable // <o.0> TX Enable
@ -481,7 +486,8 @@ typedef struct {
/* SMSC9220 Register Definitions */ /* SMSC9220 Register Definitions */
/******************************************************************************/ /******************************************************************************/
typedef struct { // SMSC LAN9220 typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7]; uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h
View File

@ -20,24 +20,5 @@
#ifndef MBED_DEVICE_H #ifndef MBED_DEVICE_H
#define MBED_DEVICE_H #define MBED_DEVICE_H
#include "objects.h" #include "objects.h"
#endif #endif