diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c index 0e1c17d2f1..d0ded31e75 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c @@ -188,7 +188,7 @@ unsigned int smsc9220_read_id(void) return SMSC9220->ID_REV; } -// Initiates a soft reset, returns failure or success. +// Initiates a soft reset, returns 0 on success, or 1 on failure. unsigned int smsc9220_soft_reset(void) { int timedout; @@ -260,18 +260,14 @@ unsigned int smsc9220_check_phy(void) unsigned int smsc9220_reset_phy(void) { unsigned short read; - int error; - error = 0; if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { - error = 1; - return error; + return 1; } read |= (1 << 15); if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { - error = 1; - return error; + return 1; } return 0; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c index 0b8b928e7d..f5032d241b 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c @@ -60,14 +60,11 @@ int smsc9220_check_id(void) int smsc9220_check_macaddress(void) { - int error; const unsigned int mac_valid_high = 0xC00A; const unsigned int mac_valid_low = 0x00F70200; unsigned int mac_low; unsigned int mac_high; - error = 0; - // Read current mac address. smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); @@ -82,11 +79,10 @@ int smsc9220_check_macaddress(void) if (mac_high != mac_valid_high || mac_low != mac_valid_low) { - error = TRUE; - return error; + return 1; } - return error; + return 0; } void smsc9220_print_mac_registers() diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h index 1e11483c3a..af11e0b478 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -590,9 +596,9 @@ typedef struct { // SMSC LAN9220 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h index 1e11483c3a..3b78c8b44f 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -590,9 +596,9 @@ typedef struct { // SMSC LAN9220 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h index 1e11483c3a..6b2a5ac3d7 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h index 2e44ab2207..e438d840f6 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h * Release: Version 1.1 @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -586,9 +592,9 @@ typedef struct { // SMSC LAN9220 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h index f7db3c293d..97ace26e8b 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h @@ -20,24 +20,5 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - - - - - - - - - - - - - - - - #include "objects.h" - #endif