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Merge pull request #7706 from jamesbeyond/fm_mem 

Refactoring memory regions definitions for Fast Models MPS2 targets
pull/7826/head
Cruz Monrreal 2018-08-17 11:10:36 -05:00 committed by GitHub
parent 8e25d2d905 f2aae22f92
commit f15dbf2c3d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
34 changed files with 599 additions and 526 deletions
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33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,3 +1,4 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2018 ARM Limited
@ -33,15 +34,31 @@
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if (defined(__stack_size__))
#define STACK_SIZE __stack_size__
#else
#define STACK_SIZE 0x0400
#endif
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

103
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
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@ -34,38 +34,14 @@
; CMSDK_CM0 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
#include "../memory_zones.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
__initial_sp EQU ZBT_SRAM2_START + ZBT_SRAM2_SIZE
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
@ -115,14 +91,14 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -217,22 +193,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP
@ -240,31 +216,4 @@ PORT0_7_Handler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld
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@ -27,11 +27,15 @@
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
@ -62,11 +66,10 @@ MEMORY
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
M_VECTOR_RAM_SIZE = 0x100;
SECTIONS
{
@ -188,13 +191,13 @@ SECTIONS
bss_size = __bss_end__ - __bss_start__;
.heap :
.heap (COPY):
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
*(.heap*)
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM

40
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf
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@ -19,25 +19,37 @@
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
/*
* WARNING: these symbols are the same as the defines in ../memory_zones.h but
* can not be included here. Please make sure that the two definitions match.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/* Code memory zones */
define symbol MAPPABLE_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SRAM1_START + ZBT_SRAM1_SIZE - 1;
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SRAM2_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SRAM2_START + ZBT_SRAM2_SIZE - 1;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x200000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

56
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c
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@ -1,56 +0,0 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
// int i;
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
// Set the vector
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
// We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];
}

23
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.h
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@ -28,27 +28,20 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#include "memory_zones.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS ZBT_SRAM2_START // Location of vectors in RAM
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
/*
* Size of the whole vector table in bytes. Each vector is on 32 bits.
*/
#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4)
#endif

14
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/memory_zones.h → targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/memory_zones.h
View File

@ -32,19 +32,19 @@
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not simulate persistent flash memory.
* The FLASH memory zone is a 256 KiB SRAM block and named FLASH
* Please note that MPS2 on Fast Models do not implemented persistent flash memory.
* The FLASH memory can be simulated via 4MB ZBT_SRAM1 block
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#define FLASH_START 0x00000000
#define FLASH_SIZE 0x00040000 /* 256 KiB */
#define ZBT_SRAM1_START 0x00400000
#define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
#define MAPPABLE_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */
#define ZBT_SRAM2_START 0x20000000
#define ZBT_SRAM2_SIZE 0x00800000 /* 8 MiB */
#define ZBT_SRAM2_SIZE 0x00400000 /* 4 MiB */
#endif /* MEMORY_ZONES_H */

33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,3 +1,4 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2018 ARM Limited
@ -33,15 +34,31 @@
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if (defined(__stack_size__))
#define STACK_SIZE __stack_size__
#else
#define STACK_SIZE 0x0400
#endif
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

55
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
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@ -34,38 +34,14 @@
; CMSDK_CM0P Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
#include "../memory_zones.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
__initial_sp EQU ZBT_SRAM2_START + ZBT_SRAM2_SIZE
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
@ -240,31 +216,4 @@ PORT0_7_Handler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld
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@ -27,11 +27,15 @@
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
@ -62,11 +66,10 @@ MEMORY
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;
SECTIONS
{
@ -188,13 +191,13 @@ SECTIONS
bss_size = __bss_end__ - __bss_start__;
.heap :
.heap (COPY):
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
*(.heap*)
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM

40
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf
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@ -19,25 +19,37 @@
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
/*
* WARNING: these symbols are the same as the defines in ../memory_zones.h but
* can not be included here. Please make sure that the two definitions match.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/* Code memory zones */
define symbol MAPPABLE_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SRAM1_START + ZBT_SRAM1_SIZE - 1;
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SRAM2_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SRAM2_START + ZBT_SRAM2_SIZE - 1;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x200000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis_nvic.h
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@ -33,7 +33,14 @@
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "memory_zones.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#define NVIC_RAM_VECTOR_ADDRESS ZBT_SRAM2_START // Location of vectors in RAM
/*
* Size of the whole vector table in bytes. Each vector is on 32 bits.
*/
#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4)
#endif

50
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/memory_zones.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file contains the information of memory zones for code and data on
* ARM Versatile Express Cortex-M Prototyping Systems (V2M-MPS2) TRM.
* It is used in startup code and linker scripts of supported compilers (ARM and
* GCC_ARM).
*
* WARNING: IAR does not include this file and re-define these values in
* MPS2.icf file. Please make sure that the two files share the same values.
*
* These memory zones are defined in section 4.2 of ARM V2M-MPS2 RTL and
* Fast Model Reference Guide.
*/
#ifndef MEMORY_ZONES_H
#define MEMORY_ZONES_H
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not implemented persistent flash memory.
* The FLASH memory can be simulated via 4MB ZBT_SRAM1 block
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#define MAPPABLE_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */
#define ZBT_SRAM2_START 0x20000000
#define ZBT_SRAM2_SIZE 0x00400000 /* 4 MiB */
#endif /* MEMORY_ZONES_H */

33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,3 +1,4 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2018 ARM Limited
@ -33,15 +34,31 @@
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if (defined(__stack_size__))
#define STACK_SIZE __stack_size__
#else
#define STACK_SIZE 0x0400
#endif
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

55
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
View File

@ -34,38 +34,14 @@
; CMSDK_CM3 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
#include "../memory_zones.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
__initial_sp EQU ZBT_SRAM2_START + ZBT_SRAM2_SIZE
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
@ -260,31 +236,4 @@ PORT0_7_Handler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld
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@ -27,11 +27,15 @@
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
@ -62,11 +66,10 @@ MEMORY
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;
SECTIONS
{
@ -188,13 +191,13 @@ SECTIONS
bss_size = __bss_end__ - __bss_start__;
.heap :
.heap (COPY):
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
*(.heap*)
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM

40
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf
View File

@ -19,25 +19,37 @@
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
/*
* WARNING: these symbols are the same as the defines in ../memory_zones.h but
* can not be included here. Please make sure that the two definitions match.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/* Code memory zones */
define symbol MAPPABLE_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SRAM1_START + ZBT_SRAM1_SIZE - 1;
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SRAM2_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SRAM2_START + ZBT_SRAM2_SIZE - 1;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x200000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

10
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis_nvic.h
View File

@ -30,10 +30,18 @@
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "memory_zones.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#define NVIC_RAM_VECTOR_ADDRESS ZBT_SRAM2_START // Location of vectors in RAM
/*
* Size of the whole vector table in bytes. Each vector is on 32 bits.
*/
#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4)
#endif

50
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/memory_zones.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file contains the information of memory zones for code and data on
* ARM Versatile Express Cortex-M Prototyping Systems (V2M-MPS2) TRM.
* It is used in startup code and linker scripts of supported compilers (ARM and
* GCC_ARM).
*
* WARNING: IAR does not include this file and re-define these values in
* MPS2.icf file. Please make sure that the two files share the same values.
*
* These memory zones are defined in section 4.2 of ARM V2M-MPS2 RTL and
* Fast Model Reference Guide.
*/
#ifndef MEMORY_ZONES_H
#define MEMORY_ZONES_H
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not implemented persistent flash memory.
* The FLASH memory can be simulated via 4MB ZBT_SRAM1 block
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#define MAPPABLE_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */
#define ZBT_SRAM2_START 0x20000000
#define ZBT_SRAM2_SIZE 0x00400000 /* 4 MiB */
#endif /* MEMORY_ZONES_H */

33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,3 +1,4 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2018 ARM Limited
@ -33,15 +34,31 @@
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if (defined(__stack_size__))
#define STACK_SIZE __stack_size__
#else
#define STACK_SIZE 0x0400
#endif
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

55
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
View File

@ -34,38 +34,14 @@
; CMSDK_CM4 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
#include "../memory_zones.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
__initial_sp EQU ZBT_SRAM2_START + ZBT_SRAM2_SIZE
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
@ -260,31 +236,4 @@ PORT0_7_Handler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld
View File

@ -27,11 +27,15 @@
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
@ -62,11 +66,10 @@ MEMORY
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;
SECTIONS
{
@ -188,13 +191,13 @@ SECTIONS
bss_size = __bss_end__ - __bss_start__;
.heap :
.heap (COPY):
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
*(.heap*)
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM

40
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf
View File

@ -19,25 +19,37 @@
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
/*
* WARNING: these symbols are the same as the defines in ../memory_zones.h but
* can not be included here. Please make sure that the two definitions match.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/* Code memory zones */
define symbol MAPPABLE_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SRAM1_START + ZBT_SRAM1_SIZE - 1;
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SRAM2_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SRAM2_START + ZBT_SRAM2_SIZE - 1;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x200000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis_nvic.h
View File

@ -33,7 +33,14 @@
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "memory_zones.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#define NVIC_RAM_VECTOR_ADDRESS ZBT_SRAM2_START // Location of vectors in RAM
/*
* Size of the whole vector table in bytes. Each vector is on 32 bits.
*/
#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4)
#endif

50
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/memory_zones.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file contains the information of memory zones for code and data on
* ARM Versatile Express Cortex-M Prototyping Systems (V2M-MPS2) TRM.
* It is used in startup code and linker scripts of supported compilers (ARM and
* GCC_ARM).
*
* WARNING: IAR does not include this file and re-define these values in
* MPS2.icf file. Please make sure that the two files share the same values.
*
* These memory zones are defined in section 4.2 of ARM V2M-MPS2 RTL and
* Fast Model Reference Guide.
*/
#ifndef MEMORY_ZONES_H
#define MEMORY_ZONES_H
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not implemented persistent flash memory.
* The FLASH memory can be simulated via 4MB ZBT_SRAM1 block
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#define MAPPABLE_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */
#define ZBT_SRAM2_START 0x20000000
#define ZBT_SRAM2_SIZE 0x00400000 /* 4 MiB */
#endif /* MEMORY_ZONES_H */

33
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,3 +1,4 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2018 ARM Limited
@ -33,15 +34,31 @@
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if (defined(__stack_size__))
#define STACK_SIZE __stack_size__
#else
#define STACK_SIZE 0x0400
#endif
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

55
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S
View File

@ -34,38 +34,14 @@
; CMSDK_CM7 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
#include "../memory_zones.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
__initial_sp EQU ZBT_SRAM2_START + ZBT_SRAM2_SIZE
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
@ -260,31 +236,4 @@ PORT0_7_Handler
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

19
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld
View File

@ -27,11 +27,15 @@
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
@ -62,11 +66,10 @@ MEMORY
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;
SECTIONS
{
@ -188,13 +191,13 @@ SECTIONS
bss_size = __bss_end__ - __bss_start__;
.heap :
.heap (COPY):
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
*(.heap*)
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM

40
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf
View File

@ -19,25 +19,37 @@
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
/*
* WARNING: these symbols are the same as the defines in ../memory_zones.h but
* can not be included here. Please make sure that the two definitions match.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/* Code memory zones */
define symbol MAPPABLE_START = 0x00000000;
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
/* Data memory zones */
define symbol ZBT_SRAM2_START = 0x20000000;
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = (16 + 48);
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SRAM1_START + ZBT_SRAM1_SIZE - 1;
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SRAM2_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SRAM2_START + ZBT_SRAM2_SIZE - 1;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x200000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

9
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h
View File

@ -33,7 +33,14 @@
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "memory_zones.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#define NVIC_RAM_VECTOR_ADDRESS ZBT_SRAM2_START // Location of vectors in RAM
/*
* Size of the whole vector table in bytes. Each vector is on 32 bits.
*/
#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4)
#endif

50
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/memory_zones.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file contains the information of memory zones for code and data on
* ARM Versatile Express Cortex-M Prototyping Systems (V2M-MPS2) TRM.
* It is used in startup code and linker scripts of supported compilers (ARM and
* GCC_ARM).
*
* WARNING: IAR does not include this file and re-define these values in
* MPS2.icf file. Please make sure that the two files share the same values.
*
* These memory zones are defined in section 4.2 of ARM V2M-MPS2 RTL and
* Fast Model Reference Guide.
*/
#ifndef MEMORY_ZONES_H
#define MEMORY_ZONES_H
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not implemented persistent flash memory.
* The FLASH memory can be simulated via 4MB ZBT_SRAM1 block
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#define MAPPABLE_START 0x00000000
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
/* Data memory zones */
#define ZBT_SRAM2_START 0x20000000
#define ZBT_SRAM2_SIZE 0x00400000 /* 4 MiB */
#endif /* MEMORY_ZONES_H */

6
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c
View File

@ -23,9 +23,9 @@
*/
#define FLASH_PAGE_SIZE 256
#define FLASH_OFS_START FLASH_START
#define FLASH_OFS_START ZBT_SRAM1_START
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_OFS_END (FLASH_OFS_START + FLASH_SIZE)
#define FLASH_OFS_END (ZBT_SRAM1_START + ZBT_SRAM1_SIZE)
int32_t flash_init(flash_t *obj)
{
@ -99,5 +99,5 @@ uint32_t flash_get_size(const flash_t *obj)
{
(void)obj;
return FLASH_SIZE;
return ZBT_SRAM1_SIZE;
}

4
targets/TARGET_ARM_FM/mbed_rtx.h
View File

@ -16,13 +16,15 @@
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
#include "memory_zones.h"
#if defined(TARGET_FVP_MPS2)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20020000UL)
#define INITIAL_SP (ZBT_SRAM2_START + ZBT_SRAM2_SIZE)
#endif
#endif /* defined(TARGET_...) */
#endif /* MBED_MBED_RTX_H */

2
targets/targets.json
View File

@ -4272,7 +4272,7 @@
"FVP_MPS2_M0": {
"inherits": ["FVP_MPS2"],
"core": "Cortex-M0",
"macros": ["CMSDK_CM0","CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""]
"macros": ["CMSDK_CM0"]
},
"FVP_MPS2_M0P": {
"inherits": ["FVP_MPS2"],