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Merge pull request #7669 from SigmaDeltaTechnologiesInc/master 

SDT64, 8195, 32620, 32625, 51822, 52832B added to targets
pull/7826/head
Cruz Monrreal 2018-08-17 11:10:12 -05:00 committed by GitHub
parent 871ee09c7a 515e35efe9
commit 8e25d2d905
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GPG Key ID: 4AEE18F83AFDEB23
24 changed files with 4031 additions and 1 deletions
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137
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
typedef enum {
UART_0 = 0,
UART_1 = 1,
UART_2 = 2,
UART_3 = 3,
UART_4 = 4,
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
typedef enum {
I2C_0 = 0,
I2C_1 = 1,
I2C_2 = 2,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21,
ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4,
ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5,
ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6,
ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7,
ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23,
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1 = 1,
SPI_2 = 2,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralPins.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTA17, ADC1_SE17, 0},
{PTB0 , ADC0_SE8 , 0},
{PTB1 , ADC0_SE9 , 0},
{PTB2 , ADC0_SE12, 0},
{PTB3 , ADC0_SE13, 0},
{PTB6 , ADC1_SE12, 0},
{PTB7 , ADC1_SE13, 0},
{PTB10, ADC1_SE14, 0},
{PTB11, ADC1_SE15, 0},
{PTC0 , ADC0_SE14, 0},
{PTC1 , ADC0_SE15, 0},
{PTC2, ADC0_SE4b, 0},
{PTC8, ADC1_SE4b, 0},
{PTC9, ADC1_SE5b, 0},
{PTC10, ADC1_SE6b, 0},
{PTC11, ADC1_SE7b, 0},
{PTD1, ADC0_SE5b, 0},
{PTD5, ADC0_SE6b, 0},
{PTD6, ADC0_SE7b, 0},
{PTE0, ADC1_SE4a, 0},
{PTE1, ADC1_SE5a, 0},
{PTE2, ADC1_SE6a, 0},
{PTE3, ADC1_SE7a, 0},
//{PTE24, ADC0_SE17, 0}, //I2C pull up
//{PTE25, ADC0_SE18, 0}, //I2C pull up
{NC , NC , 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTE25, I2C_0, 5},
{PTB1 , I2C_0, 2},
{PTB3 , I2C_0, 2},
{PTC11, I2C_1, 2},
{PTA13, I2C_2, 5},
{PTD3 , I2C_0, 7},
{PTE0 , I2C_1, 6},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTE24, I2C_0, 5},
{PTB0 , I2C_0, 2},
{PTB2 , I2C_0, 2},
{PTC10, I2C_1, 2},
{PTA12, I2C_2, 5},
{PTA14, I2C_2, 5},
{PTD2 , I2C_0, 7},
{PTE1 , I2C_1, 6},
{NC , NC , 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTB17, UART_0, 3},
{PTC17, UART_3, 3},
{PTD7 , UART_0, 3},
{PTD3 , UART_2, 3},
{PTC4 , UART_1, 3},
{PTC15, UART_4, 3},
{PTB11, UART_3, 3},
{PTA14, UART_0, 3},
{PTE24, UART_4, 3},
{PTE4 , UART_3, 3},
{PTE0, UART_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTB16, UART_0, 3},
{PTE1 , UART_1, 3},
{PTE5 , UART_3, 3},
{PTE25, UART_4, 3},
{PTA15, UART_0, 3},
{PTC16, UART_3, 3},
{PTB10, UART_3, 3},
{PTC3 , UART_1, 3},
{PTC14, UART_4, 3},
{PTD2 , UART_2, 3},
{PTD6 , UART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_CTS[] = {
{PTB13, UART_3, 2},
{PTE2 , UART_1, 3},
{PTE6 , UART_3, 3},
{PTE26, UART_4, 3},
{PTA0 , UART_0, 2},
{PTA16, UART_0, 3},
{PTB3 , UART_0, 3},
{PTB9 , UART_3, 3},
{PTC2 , UART_1, 3},
{PTC13, UART_4, 3},
{PTC19, UART_3, 3},
{PTD1 , UART_2, 3},
{PTD5 , UART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RTS[] = {
{PTB12, UART_3, 2},
{PTE3 , UART_1, 3},
{PTE7 , UART_3, 3},
{PTE27, UART_4, 3},
{PTA17, UART_0, 3},
{PTB8 , UART_3, 3},
{PTC1 , UART_1, 3},
{PTC12, UART_4, 3},
{PTC18, UART_3, 3},
{PTD0 , UART_2, 3},
{PTD4 , UART_0, 3},
{PTA3 , UART_0, 2},
{PTB2 , UART_0, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTD1 , SPI_0, 2},
{PTE2 , SPI_1, 2},
{PTA15, SPI_0, 2},
{PTB11, SPI_1, 2},
{PTB21, SPI_2, 2},
{PTC5 , SPI_0, 2},
{PTD5 , SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTD2 , SPI_0, 2},
{PTE1 , SPI_1, 2},
{PTE3 , SPI_1, 7},
{PTA16, SPI_0, 2},
{PTB16, SPI_1, 2},
{PTB22, SPI_2, 2},
{PTC6 , SPI_0, 2},
{PTD6 , SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTD3 , SPI_0, 2},
{PTE1 , SPI_1, 7},
{PTE3 , SPI_1, 2},
{PTA17, SPI_0, 2},
{PTB17, SPI_1, 2},
{PTB23, SPI_2, 2},
{PTC7 , SPI_0, 2},
{PTD7 , SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTD0 , SPI_0, 2},
{PTE4 , SPI_1, 2},
{PTA14, SPI_0, 2},
{PTB10, SPI_1, 2},
{PTB20, SPI_2, 2},
{PTC4 , SPI_0, 2},
{PTD4 , SPI_1, 7},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PTA0 , PWM_6 , 3},
{PTA1 , PWM_7 , 3},
{PTA2 , PWM_8 , 3},
{PTA3 , PWM_1 , 3},
{PTA4 , PWM_2 , 3},
{PTA5 , PWM_3 , 3},
{PTA6 , PWM_4 , 3},
{PTA7 , PWM_5 , 3},
{PTA8 , PWM_9 , 3},
{PTA9 , PWM_10, 3},
{PTA10, PWM_17, 3},
{PTA11, PWM_18, 3},
{PTA12, PWM_9 , 3},
{PTA13, PWM_10, 3},
{PTB0 , PWM_9 , 3},
{PTB1 , PWM_10, 3},
{PTB18, PWM_17, 3},
{PTB19, PWM_18, 3},
{PTC1 , PWM_1 , 4},
{PTC2 , PWM_2 , 4},
{PTC3 , PWM_3 , 4},
{PTC4 , PWM_4 , 4},
{PTC5 , PWM_3 , 7},
{PTC8 , PWM_29, 3},
{PTC9 , PWM_30, 3},
{PTC10, PWM_31, 3},
{PTC11, PWM_32, 3},
{PTD0 , PWM_25, 4},
{PTD1 , PWM_26, 4},
{PTD2 , PWM_27, 4},
{PTD3 , PWM_28, 4},
{PTD4 , PWM_5 , 4},
{PTD5 , PWM_6 , 4},
{PTD6 , PWM_7 , 4},
{PTD4 , PWM_5 , 4},
{PTD7 , PWM_8 , 4},
{PTE5 , PWM_25, 6},
{PTE6 , PWM_26, 6},
{NC , NC , 0}
};

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define DAC0_OUT 0xFEFE /* DAC does not have Pin Name in RM */
#define NOT_CONNECTED (int)0xFFFFFFFF
#define GPIO_PORT_SHIFT 12
typedef enum {
PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
PTA22 = (0 << GPIO_PORT_SHIFT | 22),
PTA23 = (0 << GPIO_PORT_SHIFT | 23),
PTA24 = (0 << GPIO_PORT_SHIFT | 24),
PTA25 = (0 << GPIO_PORT_SHIFT | 25),
PTA26 = (0 << GPIO_PORT_SHIFT | 26),
PTA27 = (0 << GPIO_PORT_SHIFT | 27),
PTA28 = (0 << GPIO_PORT_SHIFT | 28),
PTA29 = (0 << GPIO_PORT_SHIFT | 29),
PTA30 = (0 << GPIO_PORT_SHIFT | 30),
PTA31 = (0 << GPIO_PORT_SHIFT | 31),
PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
PTB12 = (1 << GPIO_PORT_SHIFT | 12),
PTB13 = (1 << GPIO_PORT_SHIFT | 13),
PTB14 = (1 << GPIO_PORT_SHIFT | 14),
PTB15 = (1 << GPIO_PORT_SHIFT | 15),
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
PTB24 = (1 << GPIO_PORT_SHIFT | 24),
PTB25 = (1 << GPIO_PORT_SHIFT | 25),
PTB26 = (1 << GPIO_PORT_SHIFT | 26),
PTB27 = (1 << GPIO_PORT_SHIFT | 27),
PTB28 = (1 << GPIO_PORT_SHIFT | 28),
PTB29 = (1 << GPIO_PORT_SHIFT | 29),
PTB30 = (1 << GPIO_PORT_SHIFT | 30),
PTB31 = (1 << GPIO_PORT_SHIFT | 31),
PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
PTC20 = (2 << GPIO_PORT_SHIFT | 20),
PTC21 = (2 << GPIO_PORT_SHIFT | 21),
PTC22 = (2 << GPIO_PORT_SHIFT | 22),
PTC23 = (2 << GPIO_PORT_SHIFT | 23),
PTC24 = (2 << GPIO_PORT_SHIFT | 24),
PTC25 = (2 << GPIO_PORT_SHIFT | 25),
PTC26 = (2 << GPIO_PORT_SHIFT | 26),
PTC27 = (2 << GPIO_PORT_SHIFT | 27),
PTC28 = (2 << GPIO_PORT_SHIFT | 28),
PTC29 = (2 << GPIO_PORT_SHIFT | 29),
PTC30 = (2 << GPIO_PORT_SHIFT | 30),
PTC31 = (2 << GPIO_PORT_SHIFT | 31),
PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
PTD10 = (3 << GPIO_PORT_SHIFT | 10),
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
PTD15 = (3 << GPIO_PORT_SHIFT | 15),
PTD16 = (3 << GPIO_PORT_SHIFT | 16),
PTD17 = (3 << GPIO_PORT_SHIFT | 17),
PTD18 = (3 << GPIO_PORT_SHIFT | 18),
PTD19 = (3 << GPIO_PORT_SHIFT | 19),
PTD20 = (3 << GPIO_PORT_SHIFT | 20),
PTD21 = (3 << GPIO_PORT_SHIFT | 21),
PTD22 = (3 << GPIO_PORT_SHIFT | 22),
PTD23 = (3 << GPIO_PORT_SHIFT | 23),
PTD24 = (3 << GPIO_PORT_SHIFT | 24),
PTD25 = (3 << GPIO_PORT_SHIFT | 25),
PTD26 = (3 << GPIO_PORT_SHIFT | 26),
PTD27 = (3 << GPIO_PORT_SHIFT | 27),
PTD28 = (3 << GPIO_PORT_SHIFT | 28),
PTD29 = (3 << GPIO_PORT_SHIFT | 29),
PTD30 = (3 << GPIO_PORT_SHIFT | 30),
PTD31 = (3 << GPIO_PORT_SHIFT | 31),
PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
PTE14 = (4 << GPIO_PORT_SHIFT | 14),
PTE15 = (4 << GPIO_PORT_SHIFT | 15),
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
PTE20 = (4 << GPIO_PORT_SHIFT | 20),
PTE21 = (4 << GPIO_PORT_SHIFT | 21),
PTE22 = (4 << GPIO_PORT_SHIFT | 22),
PTE23 = (4 << GPIO_PORT_SHIFT | 23),
PTE24 = (4 << GPIO_PORT_SHIFT | 24),
PTE25 = (4 << GPIO_PORT_SHIFT | 25),
PTE26 = (4 << GPIO_PORT_SHIFT | 26),
PTE27 = (4 << GPIO_PORT_SHIFT | 27),
PTE28 = (4 << GPIO_PORT_SHIFT | 28),
PTE29 = (4 << GPIO_PORT_SHIFT | 29),
PTE30 = (4 << GPIO_PORT_SHIFT | 30),
PTE31 = (4 << GPIO_PORT_SHIFT | 31),
// Analog
A0 = PTB6,
A1 = PTB7,
A2 = DAC0_OUT,
//A3 = DAC1_OUT,
// General Pin Input Output (GPIO)
GPIO0 = PTC1,
GPIO1 = PTC5,
GPIO2 = PTD6,
GPIO3 = PTC9,
GPIO4 = PTC3,
GPIO5 = PTC6,
GPIO6 = NOT_CONNECTED,
// Pulse Width Modulation (PWM)
PWM0 = GPIO2,
PWM1 = GPIO3,
PWM2 = GPIO0,
PWM3 = GPIO1,
// LEDs
LED0 = GPIO0,
LED1 = GPIO1,
LED2 = GPIO2,
LED_RED = LED0,
LED_GREEN = LED1,
LED_BLUE = LED2,
// USB bridge and SWD UART connected UART pins
USBTX = PTC15,
USBRX = PTC14,
// UART pins
UART0_RX = PTD8,
UART0_TX = PTD9,
UART0_CTS = PTD11,
UART0_RTS = PTD10,
UART1_RX = USBRX,
UART1_TX = USBTX,
UART1_CTS = PTC13,
UART1_RTS = PTC12,
UART2_RX = PTC16,
UART2_TX = PTC17,
UART2_CTS = PTC19,
UART2_RTS = PTC18,
// I2C pins
I2C0_SCL = PTC10,
I2C0_SDA = PTC11,
I2C1_SCL = PTB2,
I2C1_SDA = PTB3,
I2C2_SCL = NOT_CONNECTED,
I2C2_SDA = NOT_CONNECTED,
// SPI pins
SPI0_SCK = PTB11,
SPI0_MOSI = PTB16,
SPI0_MISO = PTB17,
SPI0_SS0 = PTB10,
SPI0_SS1 = PTB9,
SPI0_SS2 = PTB8,
SPI1_SCK = PTB21,
SPI1_MOSI = PTB22,
SPI1_MISO = PTB23,
SPI1_SS0 = PTB20,
SPI1_SS1 = PTB19,
SPI1_SS2 = PTB18,
SPI2_SCK = PTD1,
SPI2_MOSI = PTD2,
SPI2_MISO = PTD3,
SPI2_SS0 = PTD0,
SPI2_SS1 = PTD4,
SPI2_SS2 = PTD5,
SPI3_SCK = NOT_CONNECTED,
SPI3_MOSI = NOT_CONNECTED,
SPI3_MISO = NOT_CONNECTED,
SPI3_SS0 = NOT_CONNECTED,
SPI3_SS1 = NOT_CONNECTED,
SPI3_SS2 = NOT_CONNECTED,
// SWD UART
SWD_TGT_TX = UART1_TX,
SWD_TGT_RX = UART1_RX,
SWD_TGT_CTS = UART1_CTS,
SWD_TGT_RTS = UART1_RTS,
// Generics
SERIAL_TX = UART0_TX,
SERIAL_RX = UART0_RX,
I2C_SCL = I2C0_SCL,
I2C_SDA = I2C0_SDA,
SPI_MOSI = SPI0_MOSI,
SPI_MISO = SPI0_MISO,
SPI_SCK = SPI0_SCK,
SPI_CS = SPI0_SS0,
PWM_OUT = PWM0,
// Not connected
NC = NOT_CONNECTED
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/**********************************************************************
*
* Filename: crc.c
*
* Description: Slow and fast implementations of the CRC standards.
*
* Notes: The parameters for each supported CRC standard are
* defined in the header file crc.h. The implementations
* here should stand up to further additions to that list.
*
*
* Copyright (c) 2000 by Michael Barr. This software is placed into
* the public domain and may be used for any purpose. However, this
* notice must not be changed or removed and no warranty is either
* expressed or implied by its publication or distribution.
**********************************************************************/
#include "crc.h"
/*
* Derive parameters from the standard-specific parameters in crc.h.
*/
#define WIDTH (8 * sizeof(crc))
#define TOPBIT (1 << (WIDTH - 1))
#if (REFLECT_DATA == TRUE)
#undef REFLECT_DATA
#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
#else
#undef REFLECT_DATA
#define REFLECT_DATA(X) (X)
#endif
#if (REFLECT_REMAINDER == TRUE)
#undef REFLECT_REMAINDER
#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
#else
#undef REFLECT_REMAINDER
#define REFLECT_REMAINDER(X) (X)
#endif
/*********************************************************************
*
* Function: reflect()
*
* Description: Reorder the bits of a binary sequence, by reflecting
* them about the middle position.
*
* Notes: No checking is done that nBits <= 32.
*
* Returns: The reflection of the original data.
*
*********************************************************************/
static unsigned long
reflect(unsigned long data, unsigned char nBits)
{
unsigned long reflection = 0x00000000;
unsigned char bit;
/*
* Reflect the data about the center bit.
*/
for (bit = 0; bit < nBits; ++bit)
{
/*
* If the LSB bit is set, set the reflection of it.
*/
if (data & 0x01)
{
reflection |= (1 << ((nBits - 1) - bit));
}
data = (data >> 1);
}
return (reflection);
} /* reflect() */
/*********************************************************************
*
* Function: crcSlow()
*
* Description: Compute the CRC of a given message.
*
* Notes:
*
* Returns: The CRC of the message.
*
*********************************************************************/
crc
crcSlow(unsigned char const message[], int nBytes)
{
crc remainder = INITIAL_REMAINDER;
int byte;
unsigned char bit;
/*
* Perform modulo-2 division, a byte at a time.
*/
for (byte = 0; byte < nBytes; ++byte)
{
/*
* Bring the next byte into the remainder.
*/
remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
/*
* Perform modulo-2 division, a bit at a time.
*/
for (bit = 8; bit > 0; --bit)
{
/*
* Try to divide the current data bit.
*/
if (remainder & TOPBIT)
{
remainder = (remainder << 1) ^ POLYNOMIAL;
}
else
{
remainder = (remainder << 1);
}
}
}
/*
* The final remainder is the CRC result.
*/
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
} /* crcSlow() */
crc crcTable[256];
/*********************************************************************
*
* Function: crcInit()
*
* Description: Populate the partial CRC lookup table.
*
* Notes: This function must be rerun any time the CRC standard
* is changed. If desired, it can be run "offline" and
* the table results stored in an embedded system's ROM.
*
* Returns: None defined.
*
*********************************************************************/
void
crcInit(void)
{
crc remainder;
int dividend;
unsigned char bit;
/*
* Compute the remainder of each possible dividend.
*/
for (dividend = 0; dividend < 256; ++dividend)
{
/*
* Start with the dividend followed by zeros.
*/
remainder = dividend << (WIDTH - 8);
/*
* Perform modulo-2 division, a bit at a time.
*/
for (bit = 8; bit > 0; --bit)
{
/*
* Try to divide the current data bit.
*/
if (remainder & TOPBIT)
{
remainder = (remainder << 1) ^ POLYNOMIAL;
}
else
{
remainder = (remainder << 1);
}
}
/*
* Store the result into the table.
*/
crcTable[dividend] = remainder;
}
} /* crcInit() */
/*********************************************************************
*
* Function: crcFast()
*
* Description: Compute the CRC of a given message.
*
* Notes: crcInit() must be called first.
*
* Returns: The CRC of the message.
*
*********************************************************************/
crc
crcFast(unsigned char const message[], int nBytes)
{
crc remainder = INITIAL_REMAINDER;
unsigned char data;
int byte;
/*
* Divide the message by the polynomial, a byte at a time.
*/
for (byte = 0; byte < nBytes; ++byte)
{
data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
remainder = crcTable[data] ^ (remainder << 8);
}
/*
* The final remainder is the CRC.
*/
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
} /* crcFast() */

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/**********************************************************************
*
* Filename: crc.h
*
* Description: A header file describing the various CRC standards.
*
* Notes:
*
*
* Copyright (c) 2000 by Michael Barr. This software is placed into
* the public domain and may be used for any purpose. However, this
* notice must not be changed or removed and no warranty is either
* expressed or implied by its publication or distribution.
**********************************************************************/
#ifndef _crc_h
#define _crc_h
#define FALSE 0
#define TRUE !FALSE
/*
* Select the CRC standard from the list that follows.
*/
#define CRC16
#if defined(CRC_CCITT)
typedef unsigned short crc;
#define CRC_NAME "CRC-CCITT"
#define POLYNOMIAL 0x1021
#define INITIAL_REMAINDER 0xFFFF
#define FINAL_XOR_VALUE 0x0000
#define REFLECT_DATA FALSE
#define REFLECT_REMAINDER FALSE
#define CHECK_VALUE 0x29B1
#elif defined(CRC16)
typedef unsigned short crc;
#define CRC_NAME "CRC-16"
#define POLYNOMIAL 0x8005
#define INITIAL_REMAINDER 0x0000
#define FINAL_XOR_VALUE 0x0000
#define REFLECT_DATA TRUE
#define REFLECT_REMAINDER TRUE
#define CHECK_VALUE 0xBB3D
#elif defined(CRC32)
typedef unsigned long crc;
#define CRC_NAME "CRC-32"
#define POLYNOMIAL 0x04C11DB7
#define INITIAL_REMAINDER 0xFFFFFFFF
#define FINAL_XOR_VALUE 0xFFFFFFFF
#define REFLECT_DATA TRUE
#define REFLECT_REMAINDER TRUE
#define CHECK_VALUE 0xCBF43926
#else
#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd."
#endif
void crcInit(void);
crc crcSlow(unsigned char const message[], int nBytes);
crc crcFast(unsigned char const message[], int nBytes);
#endif /* _crc_h */

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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_common.h"
#include "fsl_smc.h"
#include "fsl_clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/* Configuration for enter VLPR mode. Core clock = 4MHz. */
const clock_config_t g_defaultClockConfigVlpr = {
.mcgConfig =
{
.mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcFast, /* Select IRC4M. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 0U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, /* Don't eanble PLL. */
.prdiv = 0U,
.vdiv = 0U,
},
},
.simConfig =
{
.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeExt,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
.coreClock = 4000000U, /* Core clock frequency */
};
/* Configuration for enter RUN mode. Core clock = 120MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 7U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeExt,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
.coreClock = 120000000U, /* Core clock frequency */
};
/*******************************************************************************
* Code
******************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
* and flash clock are in allowed range during clock mode switch.
*
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
*
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
* internal reference clock(MCGIRCLK). Follow the steps to setup:
*
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
*
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
* explicitly to setup MCGIRCLK.
*
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
* if the target mode is not FLL mode, the FLL is disabled.
*
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
*
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
*/
void BOARD_BootClockVLPR(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC, false);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClock = g_defaultClockConfigRun.coreClock;
}

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
/*******************************************************************************
* DEFINITION
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 50000000U
#define BOARD_XTAL32K_CLK_HZ 32768U
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
void BOARD_BootClockVLPR(void);
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_phy.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0xFFFFFU
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern uint32_t ENET_GetInstance(ENET_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{
uint32_t counter = PHY_TIMEOUT_COUNT;
uint32_t idReg = 0;
status_t result = kStatus_Success;
uint32_t instance = ENET_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI(base, srcClock_Hz, false);
/* Initialization after PHY stars to work. */
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
}
if (!counter)
{
return kStatus_Fail;
}
/* Reset PHY. */
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
return result;
}
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
{
status_t result = kStatus_Success;
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT;
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success)
{
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
if (result == kStatus_Success)
{
/* Check auto negotiation complete. */
while (counter --)
{
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
if ( result == kStatus_Success)
{
if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
{
break;
}
}
if (!counter)
{
return kStatus_PHY_AutoNegotiateFail;
}
}
}
}
return result;
}
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
{
uint32_t counter;
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI write command. */
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
/* Wait for SMI complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
{
assert(dataPtr);
uint32_t counter;
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI read command operation. */
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
/* Wait for MII complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Get data from MII register. */
*dataPtr = ENET_ReadSMIData(base);
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable)
{
status_t result;
uint32_t data = 0;
/* Set the loop mode. */
if (enable)
{
if (mode == kPHY_LocalLoop)
{
/* First read the current status in control register. */
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK));
}
}
else
{
/* First read the current status in control register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
}
}
}
else
{
/* Disable the loop mode. */
if (mode == kPHY_LocalLoop)
{
/* First read the current status in the basic control register. */
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK));
}
}
else
{
/* First read the current status in control one register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
}
}
}
return result;
}
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
{
assert(status);
status_t result = kStatus_Success;
uint32_t data;
/* Read the basic status register. */
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
if (result == kStatus_Success)
{
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
{
/* link down. */
*status = false;
}
else
{
/* link up. */
*status = true;
}
}
return result;
}
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
{
assert(duplex);
status_t result = kStatus_Success;
uint32_t data, ctlReg;
/* Read the control two register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (result == kStatus_Success)
{
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* Full duplex. */
*duplex = kPHY_FullDuplex;
}
else
{
/* Half duplex. */
*duplex = kPHY_HalfDuplex;
}
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* 100M speed. */
*speed = kPHY_Speed100M;
}
else
{ /* 10M speed. */
*speed = kPHY_Speed10M;
}
}
return result;
}

225
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.h Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_enet.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
/*! @brief Defines the PHY status. */
enum _phy_status
{
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
};
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
typedef enum _phy_speed
{
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
kPHY_Speed100M /*!< ENET PHY 100M speed. */
} phy_speed_t;
/*! @brief Defines the PHY link duplex. */
typedef enum _phy_duplex
{
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
kPHY_FullDuplex /*!< ENET PHY full duplex. */
} phy_duplex_t;
/*! @brief Defines the PHY loopback mode. */
typedef enum _phy_loop
{
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
} phy_loop_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
/*!
* @brief Initiates auto negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @retval kStatus_Success PHY auto negotiation success
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr);
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
/*!
* @brief Enables/disables PHY loopback.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* the two loopback mode should not be both set. when one loopback mode is set
* the other one should be disabled.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY loopback success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable);
/*!
* @brief Gets the PHY link status.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PHY_H_ */

80
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#define CRC16
#include "crc.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
BOARD_BootClockRUN();
}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void)
{
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}
// Enable the RTC oscillator if available on the board
void rtc_setup_oscillator(RTC_Type *base)
{
/* Enable the RTC oscillator */
RTC->CR |= RTC_CR_OSCE_MASK;
}
// Provide ethernet devices with a semi-unique MAC address from the UUID
void mbed_mac_address(char *mac)
{
uint16_t MAC[3]; // 3 16 bits words for the MAC
// get UID via SIM_UID macros defined in the K64F MCU CMSIS header file
uint32_t UID[4];
UID[0] = SIM->UIDH;
UID[1] = SIM->UIDMH;
UID[2] = SIM->UIDML;
UID[3] = SIM->UIDL;
// generate three CRC16's using different slices of the UUID
MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
MAC[1] = crcSlow((const uint8_t *)UID, 12);
MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
// The network stack expects an array of 6 bytes
// so we copy, and shift and copy from the half-word array to the byte array
mac[0] = MAC[0] >> 8;
mac[1] = MAC[0];
mac[2] = MAC[1] >> 8;
mac[3] = MAC[1];
mac[4] = MAC[2] >> 8;
mac[5] = MAC[2];
// We want to force bits [1:0] of the most significant byte [0]
// to be "10"
// http://en.wikipedia.org/wiki/MAC_address
mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered"
mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast
}

6
targets/TARGET_Freescale/mbed_rtx.h
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#define INITIAL_SP (0x20030000UL)
#endif
#elif defined(TARGET_SDT64B)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20030000UL)
#endif
#elif defined(TARGET_KW24D)
#ifndef INITIAL_SP

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targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PeripheralNames.h Normal file
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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = MXC_BASE_UART0,
UART_1 = MXC_BASE_UART1,
UART_2 = MXC_BASE_UART2,
UART_3 = MXC_BASE_UART3,
STDIO_UART = UART_1
} UARTName;
typedef enum {
I2C_0 = MXC_BASE_I2CM0,
I2C_1 = MXC_BASE_I2CM1,
I2C_2 = MXC_BASE_I2CM2
} I2CName;
typedef enum {
SPI_0 = MXC_BASE_SPIM0,
SPI_1 = MXC_BASE_SPIM1,
SPI_2 = MXC_BASE_SPIM2
} SPIName;
typedef enum {
PWM_0 = MXC_BASE_PT0,
PWM_1 = MXC_BASE_PT1,
PWM_2 = MXC_BASE_PT2,
PWM_3 = MXC_BASE_PT3,
PWM_4 = MXC_BASE_PT4,
PWM_5 = MXC_BASE_PT5,
PWM_6 = MXC_BASE_PT6,
PWM_7 = MXC_BASE_PT7,
PWM_8 = MXC_BASE_PT8,
PWM_9 = MXC_BASE_PT9,
PWM_10 = MXC_BASE_PT10,
PWM_11 = MXC_BASE_PT11,
PWM_12 = MXC_BASE_PT12,
PWM_13 = MXC_BASE_PT13,
PWM_14 = MXC_BASE_PT14,
PWM_15 = MXC_BASE_PT15
} PWMName;
typedef enum {
ADC = MXC_BASE_ADC
} ADCName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PinNames.h Normal file
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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "gpio_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z,
PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL
} PinDirection;
#define PORT_SHIFT 12
#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
#define NOT_CONNECTED (int)0xFFFFFFFF
typedef enum {
P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
P5_0 = (5 << PORT_SHIFT), P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7,
P6_0 = (6 << PORT_SHIFT),
// Analog input pins
AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, AIN_10, AIN_11,
// Analog
A0 = AIN_0,
A1 = AIN_1,
A2 = AIN_2,
A3 = AIN_3,
// General Pin Input Output (GPIO)
GPIO0 = P1_4,
GPIO1 = P1_5,
GPIO2 = P4_0,
GPIO3 = P4_1,
GPIO4 = P4_2,
GPIO5 = P4_3,
GPIO6 = P5_6,
//Purse Width Modulation (PWM)
PWM0 = GPIO2,
PWM1 = GPIO3,
PWM2 = GPIO0,
PWM3 = GPIO1,
// LEDs
LED0 = GPIO0,
LED1 = GPIO1,
LED2 = GPIO2,
LED3 = NOT_CONNECTED,
LED4 = NOT_CONNECTED,
LED_RED = LED0,
LED_GREEN = LED1,
LED_BLUE = LED2,
// USB bridge and SWD UART connected UART pins
USBTX = P2_1,
USBRX = P2_0,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
// UART pins
UART0_RX = P0_0,
UART0_TX = P0_1,
UART0_CTS = P0_2,
UART0_RTS = P0_3,
UART1_RX = P2_0,
UART1_TX = P2_1,
UART1_CTS = P2_2,
UART1_RTS = P2_3,
UART2_RX = P3_0,
UART2_TX = P3_1,
UART2_CTS = P3_2,
UART2_RTS = P3_3,
// I2C pins
I2C0_SCL = P1_7,
I2C0_SDA = P1_6,
I2C1_SCL = P3_5,
I2C1_SDA = P3_4,
I2C2_SCL = P6_0,
I2C2_SDA = P5_7,
// SPI pins
SPI0_SCK = P0_4,
SPI0_MOSI = P0_5,
SPI0_MISO = P0_6,
SPI0_SS0 = P0_7,
SPI0_SS1 = P4_4,
SPI0_SS2 = P4_5,
SPI1_SCK = P1_0,
SPI1_MOSI = P1_1,
SPI1_MISO = P1_2,
SPI1_SS0 = P1_3,
SPI1_SS1 = P3_6,
SPI1_SS2 = P3_7,
SPI2_SCK = P2_4,
SPI2_MOSI = P2_5,
SPI2_MISO = P2_6,
SPI2_SS0 = P2_7,
SPI2_SS1 = P4_6,
SPI2_SS2 = P4_7,
SPI3_SCK = P5_0,
SPI3_MOSI = P5_1,
SPI3_MISO = P5_2,
SPI3_SS0 = P5_3,
SPI3_SS1 = P5_4,
SPI3_SS2 = P5_5,
// SWD UART
SWD_TGT_TX = UART1_TX,
SWD_TGT_RX = UART1_RX,
SWD_TGT_CTS = UART1_CTS,
SWD_TGT_RTS = UART1_RTS,
// Generics
SERIAL_TX = UART0_TX,
SERIAL_RX = UART0_RX,
I2C_SCL = I2C0_SCL,
I2C_SDA = I2C0_SDA,
SPI_MOSI = SPI0_MOSI,
SPI_MISO = SPI0_MISO,
SPI_SCK = SPI0_SCK,
SPI_CS = SPI0_SS0,
PWM_OUT = PWM0,
// Not connected
NC = NOT_CONNECTED
} PinName;
typedef enum {
PullUp,
PullDown,
OpenDrain,
PullNone,
PullDefault = PullUp
} PinMode;
typedef enum {
LED_ON = 0,
LED_OFF = 1
} LedStates;
#ifdef __cplusplus
}
#endif
#endif

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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = MXC_BASE_UART0,
UART_1 = MXC_BASE_UART1,
UART_2 = MXC_BASE_UART2,
STDIO_UART = UART_1
} UARTName;
typedef enum {
I2C_0 = MXC_BASE_I2CM0,
I2C_1 = MXC_BASE_I2CM1
} I2CName;
typedef enum {
SPI_0 = MXC_BASE_SPIM0,
SPI_1 = MXC_BASE_SPIM1,
SPI_2 = MXC_BASE_SPIM2
} SPIName;
typedef enum {
PWM_0 = MXC_BASE_PT0,
PWM_1 = MXC_BASE_PT1,
PWM_2 = MXC_BASE_PT2,
PWM_3 = MXC_BASE_PT3,
PWM_4 = MXC_BASE_PT4,
PWM_5 = MXC_BASE_PT5,
PWM_6 = MXC_BASE_PT6,
PWM_7 = MXC_BASE_PT7,
PWM_8 = MXC_BASE_PT8,
PWM_9 = MXC_BASE_PT9,
PWM_10 = MXC_BASE_PT10,
PWM_11 = MXC_BASE_PT11,
PWM_12 = MXC_BASE_PT12,
PWM_13 = MXC_BASE_PT13,
PWM_14 = MXC_BASE_PT14,
PWM_15 = MXC_BASE_PT15
} PWMName;
typedef enum {
ADC = MXC_BASE_ADC
} ADCName;
#ifdef __cplusplus
}
#endif
#endif

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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "gpio_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT = 0, /* MXC_V_GPIO_OUT_MODE_HIGH_Z,*/
PIN_OUTPUT = 1 /* MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE */
} PinDirection;
#define PORT_SHIFT 12
#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
#define NOT_CONNECTED (int)0xFFFFFFFF
typedef enum {
P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
// Analog input pins
AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
// Analog
A0 = AIN_0,
A1 = AIN_1,
A2 = AIN_2,
A3 = AIN_3,
// General Pin Input Output (GPIO)
GPIO0 = P1_4,
GPIO1 = P1_5,
GPIO2 = P4_0,
GPIO3 = P4_1,
GPIO4 = P4_2,
GPIO5 = P4_3,
GPIO6 = NOT_CONNECTED,
//Purse Width Modulation (PWM)
PWM0 = GPIO2,
PWM1 = GPIO3,
PWM2 = GPIO0,
PWM3 = GPIO1,
// LEDs
LED0 = GPIO0,
LED1 = GPIO1,
LED2 = GPIO2,
LED3 = NOT_CONNECTED,
LED4 = NOT_CONNECTED,
LED_RED = LED0,
LED_GREEN = LED1,
LED_BLUE = LED2,
// USB bridge and SWD UART connected UART pins
USBTX = P2_1,
USBRX = P2_0,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
// UART pins
UART0_RX = P0_0,
UART0_TX = P0_1,
UART0_CTS = P0_2,
UART0_RTS = P0_3,
UART1_RX = P2_0,
UART1_TX = P2_1,
UART1_CTS = P2_2,
UART1_RTS = P2_3,
UART2_RX = P3_0,
UART2_TX = P3_1,
UART2_CTS = P3_2,
UART2_RTS = P3_3,
// I2C pins
I2C0_SCL = P1_7,
I2C0_SDA = P1_6,
I2C1_SCL = P3_5,
I2C1_SDA = P3_4,
I2C2_SCL = NOT_CONNECTED,
I2C2_SDA = NOT_CONNECTED,
// SPI pins
SPI0_SCK = P0_4,
SPI0_MOSI = P0_5,
SPI0_MISO = P0_6,
SPI0_SS0 = P0_7,
SPI0_SS1 = P4_4,
SPI0_SS2 = P4_5,
SPI1_SCK = P1_0,
SPI1_MOSI = P1_1,
SPI1_MISO = P1_2,
SPI1_SS0 = P1_3,
SPI1_SS1 = P3_6,
SPI1_SS2 = P3_7,
SPI2_SCK = P2_4,
SPI2_MOSI = P2_5,
SPI2_MISO = P2_6,
SPI2_SS0 = P2_7,
SPI2_SS1 = P4_6,
SPI2_SS2 = P4_7,
SPI3_SCK = NOT_CONNECTED,
SPI3_MOSI = NOT_CONNECTED,
SPI3_MISO = NOT_CONNECTED,
SPI3_SS0 = NOT_CONNECTED,
SPI3_SS1 = NOT_CONNECTED,
SPI3_SS2 = NOT_CONNECTED,
// SWD UART
SWD_TGT_TX = UART1_TX,
SWD_TGT_RX = UART1_RX,
SWD_TGT_CTS = UART1_CTS,
SWD_TGT_RTS = UART1_RTS,
// Generics
SERIAL_TX = UART0_TX,
SERIAL_RX = UART0_RX,
I2C_SCL = I2C0_SCL,
I2C_SDA = I2C0_SDA,
SPI_MOSI = SPI0_MOSI,
SPI_MISO = SPI0_MISO,
SPI_SCK = SPI0_SCK,
SPI_CS = SPI0_SS0,
PWM_OUT = PWM0,
// Not connected
NC = NOT_CONNECTED
} PinName;
typedef enum {
PullUp,
PullDown,
OpenDrain,
PullNone,
PullDefault = PullUp
} PinMode;
typedef enum {
LED_ON = 0,
LED_OFF = 1
} LedStates;
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define NOT_CONNECTED (int)0xFFFFFFFF
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
// Analog
A0 = P0_1,
A1 = P0_2,
A2 = P0_3,
A3 = P0_4,
// General Pin Input Output (GPIO)
GPIO0 = P0_5,
GPIO1 = P0_7,
GPIO2 = P0_12,
GPIO3 = NOT_CONNECTED,
GPIO4 = NOT_CONNECTED,
GPIO5 = NOT_CONNECTED,
GPIO6 = NOT_CONNECTED,
//Purse Width Modulation (PWM)
PWM0 = GPIO2,
PWM1 = GPIO3,
PWM2 = GPIO0,
PWM3 = GPIO1,
// LEDs
LED0 = GPIO0,
LED1 = GPIO1,
LED2 = GPIO2,
LED_RED = LED0,
LED_GREEN = LED1,
LED_BLUE = LED2,
// USB bridge and SWD UART connected UART pins
USBTX = P0_9,
USBRX = P0_11,
// UART pins
UART0_RX = NOT_CONNECTED,
UART0_TX = NOT_CONNECTED,
UART0_CTS = NOT_CONNECTED,
UART0_RTS = NOT_CONNECTED,
UART1_RX = P0_11,
UART1_TX = P0_9,
UART1_CTS = P0_10,
UART1_RTS = P0_8,
RX_PIN_NUMBER = p11,
TX_PIN_NUMBER = p9,
CTS_PIN_NUMBER = p10,
RTS_PIN_NUMBER = p8,
UART2_RX = NOT_CONNECTED,
UART2_TX = NOT_CONNECTED,
UART2_CTS = NOT_CONNECTED,
UART2_RTS = NOT_CONNECTED,
// I2C pins
I2C0_SCL = P0_20,
I2C0_SDA = P0_19,
I2C1_SCL = P0_30,
I2C1_SDA = P0_29,
I2C2_SCL = NOT_CONNECTED,
I2C2_SDA = NOT_CONNECTED,
// SPI pins
SPI0_SCK = P0_18,
SPI0_MOSI = P0_15,
SPI0_MISO = P0_16,
SPI0_SS0 = P0_17,
SPI0_SS1 = P0_14,
SPI0_SS2 = P0_13,
SPI1_SCK = P0_25,
SPI1_MOSI = P0_23,
SPI1_MISO = P0_24,
SPI1_SS0 = P0_22,
SPI1_SS1 = P0_21,
SPI1_SS2 = P0_28,
SPI2_SCK = NOT_CONNECTED,
SPI2_MOSI = NOT_CONNECTED,
SPI2_MISO = NOT_CONNECTED,
SPI2_SS0 = NOT_CONNECTED,
SPI2_SS1 = NOT_CONNECTED,
SPI2_SS2 = NOT_CONNECTED,
SPI3_SCK = NOT_CONNECTED,
SPI3_MOSI = NOT_CONNECTED,
SPI3_MISO = NOT_CONNECTED,
SPI3_SS0 = NOT_CONNECTED,
SPI3_SS1 = NOT_CONNECTED,
SPI3_SS2 = NOT_CONNECTED,
// SWD UART
SWD_TGT_TX = UART1_TX,
SWD_TGT_RX = UART1_RX,
SWD_TGT_CTS = UART1_CTS,
SWD_TGT_RTS = UART1_RTS,
// Generics
SERIAL_TX = UART1_TX,
SERIAL_RX = UART1_RX,
I2C_SCL = I2C0_SCL,
I2C_SDA = I2C0_SDA,
SPI_MOSI = SPI0_MOSI,
SPI_MISO = SPI0_MISO,
SPI_SCK = SPI0_SCK,
SPI_CS = SPI0_SS0,
PWM_OUT = PWM0,
// Not connected
NC = NOT_CONNECTED
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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/*
* Copyright (c) 2016 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define NOT_CONNECTED (int)0xFFFFFFFF
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
RX_PIN_NUMBER = p8,
TX_PIN_NUMBER = p6,
CTS_PIN_NUMBER = p7,
RTS_PIN_NUMBER = p5,
// mBed interface Pins
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
// Analog
A0 = P0_2,
A1 = P0_3,
A2 = P0_4,
A3 = P0_28,
// General Pin Input Output (GPIO)
GPIO0 = P0_9,
GPIO1 = P0_10,
GPIO2 = P0_17,
GPIO3 = P0_29,
GPIO4 = NOT_CONNECTED,
GPIO5 = NOT_CONNECTED,
GPIO6 = NOT_CONNECTED,
//Purse Width Modulation (PWM)
PWM0 = GPIO2,
PWM1 = GPIO3,
PWM2 = GPIO0,
PWM3 = GPIO1,
// LEDs
LED0 = GPIO0,
LED1 = GPIO1,
LED2 = GPIO2,
LED_RED = LED0,
LED_GREEN = LED1,
LED_BLUE = LED2,
// USB bridge and SWD UART connected UART pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
// UART pins
UART0_RX = NOT_CONNECTED,
UART0_TX = NOT_CONNECTED,
UART0_CTS = NOT_CONNECTED,
UART0_RTS = NOT_CONNECTED,
UART1_RX = P0_8,
UART1_TX = P0_6,
UART1_CTS = P0_7,
UART1_RTS = P0_5,
UART2_RX = NOT_CONNECTED,
UART2_TX = NOT_CONNECTED,
UART2_CTS = NOT_CONNECTED,
UART2_RTS = NOT_CONNECTED,
// I2C pins
I2C0_SCL = P0_27,
I2C0_SDA = P0_26,
I2C1_SCL = P0_31,
I2C1_SDA = P0_30,
I2C2_SCL = NOT_CONNECTED,
I2C2_SDA = NOT_CONNECTED,
// SPI pins
SPI0_SCK = P0_14,
SPI0_MOSI = P0_12,
SPI0_MISO = P0_13,
SPI0_SS0 = P0_11,
SPI0_SS1 = P0_15,
SPI0_SS2 = P0_16,
SPI1_SCK = P0_25,
SPI1_MOSI = P0_23,
SPI1_MISO = P0_24,
SPI1_SS0 = P0_22,
SPI1_SS1 = P0_19,
SPI1_SS2 = P0_20,
SPI2_SCK = NOT_CONNECTED,
SPI2_MOSI = NOT_CONNECTED,
SPI2_MISO = NOT_CONNECTED,
SPI2_SS0 = NOT_CONNECTED,
SPI2_SS1 = NOT_CONNECTED,
SPI2_SS2 = NOT_CONNECTED,
SPI3_SCK = NOT_CONNECTED,
SPI3_MOSI = NOT_CONNECTED,
SPI3_MISO = NOT_CONNECTED,
SPI3_SS0 = NOT_CONNECTED,
SPI3_SS1 = NOT_CONNECTED,
SPI3_SS2 = NOT_CONNECTED,
// SWD UART
SWD_TGT_TX = UART1_TX,
SWD_TGT_RX = UART1_RX,
SWD_TGT_CTS = UART1_CTS,
SWD_TGT_RTS = UART1_RTS,
// Generics
SERIAL_TX = UART1_TX,
SERIAL_RX = UART1_RX,
I2C_SCL = I2C0_SCL,
I2C_SDA = I2C0_SDA,
SPI_MOSI = SPI0_MOSI,
SPI_MISO = SPI0_MISO,
SPI_SCK = SPI0_SCK,
SPI_CS = SPI0_SS0,
PWM_OUT = PWM0,
// Not connected
NC = NOT_CONNECTED
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

38
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/device.h Normal file
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

757
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.c Normal file
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/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "osdep_service.h"
#include "dhcps.h"
#include "tcpip.h"
//static struct dhcp_server_state dhcp_server_state_machine;
static uint8_t dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
/* recorded the client MAC addr(default sudo mac) */
//static uint8_t dhcps_record_first_client_mac[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
/* recorded transaction ID (default sudo id)*/
static uint8_t dhcp_recorded_xid[4] = {0xff, 0xff, 0xff, 0xff};
/* UDP Protocol Control Block(PCB) */
static struct udp_pcb *dhcps_pcb;
static ip_addr_t dhcps_send_broadcast_address;
static ip_addr_t dhcps_local_address;
static ip_addr_t dhcps_pool_start;
static ip_addr_t dhcps_pool_end;
static ip_addr_t dhcps_local_mask;
static ip_addr_t dhcps_local_gateway;
static ip_addr_t dhcps_network_id;
static ip_addr_t dhcps_subnet_broadcast;
static ip_addr_t dhcps_allocated_client_address;
static int dhcps_addr_pool_set = 0;
static ip_addr_t dhcps_addr_pool_start;
static ip_addr_t dhcps_addr_pool_end;
#if 1
static ip_addr_t dhcps_owned_first_ip;
static ip_addr_t dhcps_owned_last_ip;
static uint8_t dhcps_num_of_available_ips;
#endif
static struct dhcp_msg *dhcp_message_repository;
static int dhcp_message_total_options_lenth;
/* allocated IP range */
static struct table ip_table;
static ip_addr_t client_request_ip;
static uint8_t client_addr[6];
static _mutex dhcps_ip_table_semaphore;
static struct netif * dhcps_netif = NULL;
/**
* @brief latch the specific ip in the ip table.
* @param d the specific index
* @retval None.
*/
#if (!IS_USE_FIXED_IP)
static void mark_ip_in_table(uint8_t d)
{
#if (debug_dhcps)
printf("\r\nmark ip %d\r\n",d);
#endif
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
if (0 < d && d <= 32) {
ip_table.ip_range[0] = MARK_RANGE1_IP_BIT(ip_table, d);
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[0] = 0x%x\r\n",ip_table.ip_range[0]);
#endif
} else if (32 < d && d <= 64) {
ip_table.ip_range[1] = MARK_RANGE2_IP_BIT(ip_table, (d - 32));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[1] = 0x%x\r\n",ip_table.ip_range[1]);
#endif
} else if (64 < d && d <= 96) {
ip_table.ip_range[2] = MARK_RANGE3_IP_BIT(ip_table, (d - 64));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[2] = 0x%x\r\n",ip_table.ip_range[2]);
#endif
} else if (96 < d && d <= 128) {
ip_table.ip_range[3] = MARK_RANGE4_IP_BIT(ip_table, (d - 96));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[3] = 0x%x\r\n",ip_table.ip_range[3]);
#endif
} else if(128 < d && d <= 160) {
ip_table.ip_range[4] = MARK_RANGE5_IP_BIT(ip_table, d);
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[4] = 0x%x\r\n",ip_table.ip_range[4]);
#endif
} else if (160 < d && d <= 192) {
ip_table.ip_range[5] = MARK_RANGE6_IP_BIT(ip_table, (d - 160));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[5] = 0x%x\r\n",ip_table.ip_range[5]);
#endif
} else if (192 < d && d <= 224) {
ip_table.ip_range[6] = MARK_RANGE7_IP_BIT(ip_table, (d - 192));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[6] = 0x%x\r\n",ip_table.ip_range[6]);
#endif
} else if (224 < d) {
ip_table.ip_range[7] = MARK_RANGE8_IP_BIT(ip_table, (d - 224));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[7] = 0x%x\r\n",ip_table.ip_range[7]);
#endif
} else {
printf("\r\n Request ip over the range(1-128) \r\n");
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
}
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
static void save_client_addr(ip_addr_t *client_ip, uint8_t *hwaddr)
{
uint8_t d = (uint8_t)ip4_addr4(client_ip);
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
memcpy(ip_table.client_mac[d], hwaddr, 6);
#if (debug_dhcps)
printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
ip4_addr1(client_ip), ip4_addr2(client_ip), ip4_addr3(client_ip), ip4_addr4(client_ip),
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
#endif
rtw_mutex_put(&dhcps_ip_table_semaphore);
}
static uint8_t check_client_request_ip(ip_addr_t *client_req_ip, uint8_t *hwaddr)
{
int ip_addr4 = 0, i;
#if (debug_dhcps)
printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
ip4_addr1(client_req_ip), ip4_addr2(client_req_ip), ip4_addr3(client_req_ip), ip4_addr4(client_req_ip),
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
#endif
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
for(i=DHCP_POOL_START;i<=DHCP_POOL_END;i++)
{
//printf("client[%d] = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",i,ip_table.client_mac[i][0],ip_table.client_mac[i][0],ip_table.client_mac[i][1],ip_table.client_mac[i][2],ip_table.client_mac[i][3],ip_table.client_mac[i][4],ip_table.client_mac[i][5]);
if(memcmp(ip_table.client_mac[i], hwaddr, 6) == 0){
if((ip_table.ip_range[i/32]>>(i%32-1)) & 1){
ip_addr4 = i;
break;
}
}
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
if(i == DHCP_POOL_END+1)
ip_addr4 = 0;
return ip_addr4;
}
#if debug_dhcps
static void dump_client_table()
{
#if 0
int i;
uint8_t *p = NULL;
printf("\r\nip_range: %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x",
ip_table.ip_range[0], ip_table.ip_range[1], ip_table.ip_range[2], ip_table.ip_range[3],
ip_table.ip_range[4], ip_table.ip_range[5], ip_table.ip_range[6], ip_table.ip_range[7]);
for(i=1; i<=DHCPS_MAX_CLIENT_NUM; i++)
{
p = ip_table.client_mac[i];
printf("\r\nClient[%d]: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
i, p[0], p[1], p[2], p[3], p[4], p[5]);
}
printf("\r\n");
#endif
}
#endif
#endif //CONFIG_DHCPS_KEPT_CLIENT_INFO
#endif
/**
* @brief get one usable ip from the ip table of dhcp server.
* @param: None
* @retval the usable index which represent the ip4_addr(ip) of allocated ip addr.
*/
#if (!IS_USE_FIXED_IP)
static uint8_t search_next_ip(void)
{
uint8_t range_count, offset_count;
uint8_t start, end;
uint8_t max_count;
if(dhcps_addr_pool_set){
start = (uint8_t)ip4_addr4(&dhcps_addr_pool_start);
end = (uint8_t)ip4_addr4(&dhcps_addr_pool_end);
}else{
start = 0;
end = 255;
}
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
for (range_count = 0; range_count < (max_count = 8); range_count++) {
for (offset_count = 0;offset_count < 32; offset_count++) {
if ((((ip_table.ip_range[range_count] >> offset_count) & 0x01) == 0)
&&(((range_count * 32) + (offset_count + 1)) >= start)
&&(((range_count * 32) + (offset_count + 1)) <= end)) {
rtw_mutex_put(&dhcps_ip_table_semaphore);
return ((range_count * 32) + (offset_count + 1));
}
}
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
return 0;
}
#endif
/**
* @brief fill in the option field with message type of a dhcp message.
* @param msg_option_base_addr: the addr be filled start.
* message_type: the type code you want to fill in
* @retval the start addr of the next dhcp option.
*/
static uint8_t *add_msg_type(uint8_t *msg_option_base_addr, uint8_t message_type)
{
uint8_t *option_start;
msg_option_base_addr[0] = DHCP_OPTION_CODE_MSG_TYPE;
msg_option_base_addr[1] = DHCP_OPTION_LENGTH_ONE;
msg_option_base_addr[2] = message_type;
option_start = msg_option_base_addr + 3;
if (DHCP_MESSAGE_TYPE_NAK == message_type)
*option_start++ = DHCP_OPTION_CODE_END;
return option_start;
}
static uint8_t *fill_one_option_content(uint8_t *option_base_addr,
uint8_t option_code, uint8_t option_length, void *copy_info)
{
uint8_t *option_data_base_address;
uint8_t *next_option_start_address = NULL;
option_base_addr[0] = option_code;
option_base_addr[1] = option_length;
option_data_base_address = option_base_addr + 2;
switch (option_length) {
case DHCP_OPTION_LENGTH_FOUR:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_FOUR);
next_option_start_address = option_data_base_address + 4;
break;
case DHCP_OPTION_LENGTH_TWO:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_TWO);
next_option_start_address = option_data_base_address + 2;
break;
case DHCP_OPTION_LENGTH_ONE:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_ONE);
next_option_start_address = option_data_base_address + 1;
break;
}
return next_option_start_address;
}
/**
* @brief fill in the needed content of the dhcp offer message.
* @param optptr the addr which the tail of dhcp magic field.
* @retval the addr represent to add the end of option.
*/
static void add_offer_options(uint8_t *option_start_address)
{
uint8_t *temp_option_addr;
/* add DHCP options 1.
The subnet mask option specifies the client's subnet mask */
temp_option_addr = fill_one_option_content(option_start_address,
DHCP_OPTION_CODE_SUBNET_MASK, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_mask);
/* add DHCP options 3 (i.e router(gateway)). The time server option
specifies a list of RFC 868 [6] time servers available to the client. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_ROUTER, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_address);
/* add DHCP options 6 (i.e DNS).
The option specifies a list of DNS servers available to the client. */
//temp_option_addr = fill_one_option_content(temp_option_addr,
// DHCP_OPTION_CODE_DNS_SERVER, DHCP_OPTION_LENGTH_FOUR,
// (void *)&dhcps_local_address);
/* add DHCP options 51.
This option is used to request a lease time for the IP address. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_LEASE_TIME, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcp_option_lease_time);
/* add DHCP options 54.
The identifier is the IP address of the selected server. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_SERVER_ID, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_address);
/* add DHCP options 28.
This option specifies the broadcast address in use on client's subnet.*/
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_BROADCAST_ADDRESS, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_subnet_broadcast);
/* add DHCP options 26.
This option specifies the Maximum transmission unit to use */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_INTERFACE_MTU, DHCP_OPTION_LENGTH_TWO,
(void *) &dhcp_option_interface_mtu);//dhcp_option_interface_mtu_576);
/* add DHCP options 31.
This option specifies whether or not the client should solicit routers */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY, DHCP_OPTION_LENGTH_ONE,
NULL);
*temp_option_addr++ = DHCP_OPTION_CODE_END;
}
/**
* @brief fill in common content of a dhcp message.
* @param m the pointer which point to the dhcp message store in.
* @retval None.
*/
static void dhcps_initialize_message(struct dhcp_msg *dhcp_message_repository)
{
dhcp_message_repository->op = DHCP_MESSAGE_OP_REPLY;
dhcp_message_repository->htype = DHCP_MESSAGE_HTYPE;
dhcp_message_repository->hlen = DHCP_MESSAGE_HLEN;
dhcp_message_repository->hops = 0;
memcpy((char *)dhcp_recorded_xid, (char *) dhcp_message_repository->xid,
sizeof(dhcp_message_repository->xid));
dhcp_message_repository->secs = 0;
dhcp_message_repository->flags = htons(BOOTP_BROADCAST);
memcpy((char *)dhcp_message_repository->yiaddr,
(char *)&dhcps_allocated_client_address,
sizeof(dhcp_message_repository->yiaddr));
memset((char *)dhcp_message_repository->ciaddr, 0,
sizeof(dhcp_message_repository->ciaddr));
memset((char *)dhcp_message_repository->siaddr, 0,
sizeof(dhcp_message_repository->siaddr));
memset((char *)dhcp_message_repository->giaddr, 0,
sizeof(dhcp_message_repository->giaddr));
memset((char *)dhcp_message_repository->sname, 0,
sizeof(dhcp_message_repository->sname));
memset((char *)dhcp_message_repository->file, 0,
sizeof(dhcp_message_repository->file));
memset((char *)dhcp_message_repository->options, 0,
dhcp_message_total_options_lenth);
memcpy((char *)dhcp_message_repository->options, (char *)dhcp_magic_cookie,
sizeof(dhcp_magic_cookie));
}
/**
* @brief init and fill in the needed content of dhcp offer message.
* @param packet_buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_offer(struct pbuf *packet_buffer)
{
uint8_t temp_ip = 0;
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
#if (!IS_USE_FIXED_IP)
temp_ip = check_client_request_ip(&client_request_ip, client_addr);
/* create new client ip */
if(temp_ip == 0)
temp_ip = search_next_ip();
#if (debug_dhcps)
printf("\r\n temp_ip = %d",temp_ip);
#endif
if (temp_ip == 0) {
#if 0
memset(&ip_table, 0, sizeof(struct table));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
printf("\r\n reset ip table!!\r\n");
#endif
printf("\r\n No useable ip!!!!\r\n");
}
printf("\n\r[%d]DHCP assign ip = %d.%d.%d.%d\n", rtw_get_current_time(), ip4_addr1(&dhcps_network_id),ip4_addr2(&dhcps_network_id),ip4_addr3(&dhcps_network_id),temp_ip);
IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), temp_ip);
#endif
dhcps_initialize_message(dhcp_message_repository);
add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
DHCP_MESSAGE_TYPE_OFFER));
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief init and fill in the needed content of dhcp nak message.
* @param packet buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_nak(struct pbuf *packet_buffer)
{
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcps_initialize_message(dhcp_message_repository);
add_msg_type(&dhcp_message_repository->options[4], DHCP_MESSAGE_TYPE_NAK);
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief init and fill in the needed content of dhcp ack message.
* @param packet buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_ack(struct pbuf *packet_buffer)
{
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcps_initialize_message(dhcp_message_repository);
add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
DHCP_MESSAGE_TYPE_ACK));
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief according by the input message type to reflect the correspond state.
* @param option_message_type the input server state
* @retval the server state which already transfer to.
*/
uint8_t dhcps_handle_state_machine_change(uint8_t option_message_type)
{
switch (option_message_type) {
case DHCP_MESSAGE_TYPE_DECLINE:
#if (debug_dhcps)
printf("\r\nget message DHCP_MESSAGE_TYPE_DECLINE\n");
#endif
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_MESSAGE_TYPE_DISCOVER:
#if (debug_dhcps)
printf("\r\nget message DHCP_MESSAGE_TYPE_DISCOVER\n");
#endif
if (dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE) {
dhcp_server_state_machine = DHCP_SERVER_STATE_OFFER;
}
break;
case DHCP_MESSAGE_TYPE_REQUEST:
#if (debug_dhcps)
printf("\r\n[%d]get message DHCP_MESSAGE_TYPE_REQUEST\n", rtw_get_current_time());
#endif
#if (!IS_USE_FIXED_IP)
#if (debug_dhcps)
printf("\r\ndhcp_server_state_machine=%d", dhcp_server_state_machine);
printf("\r\ndhcps_allocated_client_address=%d.%d.%d.%d",
ip4_addr1(&dhcps_allocated_client_address),
ip4_addr2(&dhcps_allocated_client_address),
ip4_addr3(&dhcps_allocated_client_address),
ip4_addr4(&dhcps_allocated_client_address));
printf("\r\nclient_request_ip=%d.%d.%d.%d\n",
ip4_addr1(&client_request_ip),
ip4_addr2(&client_request_ip),
ip4_addr3(&client_request_ip),
ip4_addr4(&client_request_ip));
#endif
if (dhcp_server_state_machine == DHCP_SERVER_STATE_OFFER) {
if (ip4_addr4(&dhcps_allocated_client_address) != 0) {
if (memcmp((void *)&dhcps_allocated_client_address, (void *)&client_request_ip, 4) == 0) {
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else if(dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE){
uint8_t ip_addr4 = check_client_request_ip(&client_request_ip, client_addr);
if(ip_addr4 > 0){
IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), ip_addr4);
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
}else{
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
#else
if (!(dhcp_server_state_machine == DHCP_SERVER_STATE_ACK ||
dhcp_server_state_machine == DHCP_SERVER_STATE_NAK)) {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
#endif
break;
case DHCP_MESSAGE_TYPE_RELEASE:
printf("get message DHCP_MESSAGE_TYPE_RELEASE\n");
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
}
return dhcp_server_state_machine;
}
/**
* @brief parse the dhcp message option part.
* @param optptr: the addr of the first option field.
* len: the total length of all option fields.
* @retval dhcp server state.
*/
static uint8_t dhcps_handle_msg_options(uint8_t *option_start, int16_t total_option_length)
{
int16_t option_message_type = 0;
uint8_t *option_end = option_start + total_option_length;
//dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
/* begin process the dhcp option info */
while (option_start < option_end) {
switch ((uint8_t)*option_start) {
case DHCP_OPTION_CODE_MSG_TYPE:
option_message_type = *(option_start + 2); // 2 => code(1)+lenth(1)
break;
case DHCP_OPTION_CODE_REQUEST_IP_ADDRESS :
#if IS_USE_FIXED_IP
if (memcmp((char *)&dhcps_allocated_client_address,
(char *)option_start + 2, 4) == 0)
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
else
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
#else
memcpy((char *)&client_request_ip, (char *)option_start + 2, 4);
#endif
break;
}
// calculate the options offset to get next option's base addr
option_start += option_start[1] + 2; // optptr[1]: length value + (code(1)+ Len(1))
}
return dhcps_handle_state_machine_change(option_message_type);
}
/**
* @brief get message from buffer then check whether it is dhcp related or not.
* if yes , parse it more to undersatnd the client's request.
* @param same as recv callback function definition
* @retval if message is dhcp related then return dhcp server state,
* otherwise return 0
*/
static uint8_t dhcps_check_msg_and_handle_options(struct pbuf *packet_buffer)
{
int dhcp_message_option_offset;
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcp_message_option_offset = ((int)dhcp_message_repository->options
- (int)packet_buffer->payload);
dhcp_message_total_options_lenth = (packet_buffer->len
- dhcp_message_option_offset);
memcpy(client_addr, dhcp_message_repository->chaddr, 6);
/* check the magic number,if correct parse the content of options */
if (memcmp((char *)dhcp_message_repository->options,
(char *)dhcp_magic_cookie, sizeof(dhcp_magic_cookie)) == 0) {
return dhcps_handle_msg_options(&dhcp_message_repository->options[4],
(dhcp_message_total_options_lenth - 4));
}
return 0;
}
/**
* @brief handle imcoming dhcp message and response message to client
* @param same as recv callback function definition
* @retval None
*/
static void dhcps_receive_udp_packet_handler(void *arg, struct udp_pcb *udp_pcb,
struct pbuf *udp_packet_buffer, ip_addr_t *sender_addr, uint16_t sender_port)
{
int16_t total_length_of_packet_buffer;
struct pbuf *merged_packet_buffer = NULL;
dhcp_message_repository = (struct dhcp_msg *)udp_packet_buffer->payload;
if (udp_packet_buffer == NULL) {
printf("\n\r Error!!!! System doesn't allocate any buffer \n\r");
return;
}
if (sender_port == DHCP_CLIENT_PORT) {
total_length_of_packet_buffer = udp_packet_buffer->tot_len;
if (udp_packet_buffer->next != NULL) {
merged_packet_buffer = pbuf_coalesce(udp_packet_buffer,
PBUF_TRANSPORT);
if (merged_packet_buffer->tot_len !=
total_length_of_packet_buffer) {
pbuf_free(udp_packet_buffer);
return;
}
}
switch (dhcps_check_msg_and_handle_options(udp_packet_buffer)) {
case DHCP_SERVER_STATE_OFFER:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_OFFER\n",__func__);
#endif
dhcps_send_offer(udp_packet_buffer);
break;
case DHCP_SERVER_STATE_ACK:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_ACK\n",__func__);
#endif
dhcps_send_ack(udp_packet_buffer);
#if (!IS_USE_FIXED_IP)
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_allocated_client_address));
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
save_client_addr(&dhcps_allocated_client_address, client_addr);
memset(&client_request_ip, 0, sizeof(client_request_ip));
memset(&client_addr, 0, sizeof(client_addr));
memset(&dhcps_allocated_client_address, 0, sizeof(dhcps_allocated_client_address));
#if (debug_dhcps)
dump_client_table();
#endif
#endif
#endif
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_SERVER_STATE_NAK:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_NAK\n",__func__);
#endif
dhcps_send_nak(udp_packet_buffer);
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_OPTION_CODE_END:
#if (debug_dhcps)
printf("%s DHCP_OPTION_CODE_END\n",__func__);
#endif
break;
}
}
/* free the UDP connection, so we can accept new clients */
udp_disconnect(udp_pcb);
/* Free the packet buffer */
if (merged_packet_buffer != NULL)
pbuf_free(merged_packet_buffer);
else
pbuf_free(udp_packet_buffer);
}
void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end)
{
//uint8_t *ip;
if(addr_pool_set){
dhcps_addr_pool_set = 1;
memcpy(&dhcps_addr_pool_start, addr_pool_start,
sizeof(ip_addr_t));
//ip = &dhcps_addr_pool_start;
//ip[3] = 100;
memcpy(&dhcps_addr_pool_end, addr_pool_end,
sizeof(ip_addr_t));
//ip = &dhcps_addr_pool_end;
//ip[3] = 200;
}else{
dhcps_addr_pool_set = 0;
}
}
/**
* @brief Initialize dhcp server.
* @param None.
* @retval None.
* Note, for now,we assume the server latch ip 192.168.1.1 and support dynamic
* or fixed IP allocation.
*/
void dhcps_init(struct netif * pnetif)
{
uint8_t *ip;
// printf("dhcps_init,wlan:%c\n\r",pnetif->name[1]);
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
memset(&ip_table, 0, sizeof(struct table));
// int i = 0;
// for(i=0; i< DHCPS_MAX_CLIENT_NUM+2; i++)
// memset(ip_table.client_mac[i], 0, 6);
// dump_client_table();
#endif
dhcps_netif = pnetif;
if (dhcps_pcb != NULL) {
udp_remove(dhcps_pcb);
dhcps_pcb = NULL;
}
dhcps_pcb = udp_new();
if (dhcps_pcb == NULL) {
printf("\n\r Error!!!upd_new error \n\r");
return;
}
IP4_ADDR(&dhcps_send_broadcast_address, 255, 255, 255, 255);
/* get net info from net interface */
memcpy(&dhcps_local_address, &pnetif->ip_addr,
sizeof(ip_addr_t));
memcpy(&dhcps_local_mask, &pnetif->netmask,
sizeof(ip_addr_t));
memcpy(&dhcps_local_gateway, &pnetif->gw,
sizeof(ip_addr_t));
/* calculate the usable network ip range */
dhcps_network_id.addr = ((pnetif->ip_addr.addr) &
(pnetif->netmask.addr));
dhcps_subnet_broadcast.addr = ((dhcps_network_id.addr |
~(pnetif->netmask.addr)));
#if 1
dhcps_owned_first_ip.addr = htonl((ntohl(dhcps_network_id.addr) + 1));
dhcps_owned_last_ip.addr = htonl(ntohl(dhcps_subnet_broadcast.addr) - 1);
dhcps_num_of_available_ips = ((ntohl(dhcps_owned_last_ip.addr)
- ntohl(dhcps_owned_first_ip.addr)) + 1);
#endif
#if IS_USE_FIXED_IP
IP4_ADDR(&dhcps_allocated_client_address, ip4_addr1(&dhcps_local_address)
, ip4_addr2(&dhcps_local_address), ip4_addr3(&dhcps_local_address),
(ip4_addr4(&dhcps_local_address)) + 1 );
#else
if (dhcps_ip_table_semaphore != NULL) {
rtw_mutex_free(&dhcps_ip_table_semaphore);
dhcps_ip_table_semaphore = NULL;
}
rtw_mutex_init(&dhcps_ip_table_semaphore);
//dhcps_ip_table = (struct ip_table *)(pvPortMalloc(sizeof(struct ip_table)));
memset(&ip_table, 0, sizeof(struct table));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_gateway));
#if 0
for (i = 1; i < ip4_addr4(&dhcps_local_address); i++) {
mark_ip_in_table(i);
}
#endif
#endif
memcpy(&dhcps_pool_start,&dhcps_local_address,sizeof(ip_addr_t));
ip = (uint8_t *)&dhcps_pool_start;
ip[3] = DHCP_POOL_START;
memcpy(&dhcps_pool_end,&dhcps_local_address,sizeof(ip_addr_t));
ip = (uint8_t *)&dhcps_pool_end;
ip[3] = DHCP_POOL_END;
dhcps_set_addr_pool(1,&dhcps_pool_start,&dhcps_pool_end);
udp_bind(dhcps_pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
udp_recv(dhcps_pcb, (udp_recv_fn)dhcps_receive_udp_packet_handler, NULL);
}
void dhcps_deinit(void)
{
if (dhcps_pcb != NULL) {
udp_remove(dhcps_pcb);
dhcps_pcb = NULL;
}
if (dhcps_ip_table_semaphore != NULL) {
rtw_mutex_free(&dhcps_ip_table_semaphore);
dhcps_ip_table_semaphore = NULL;
}
}

159
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.h Normal file
View File

@ -0,0 +1,159 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef __DHCPS_H__
#define __DHCPS_H__
#include "lwip/arch.h"
#include "lwip/netif.h"
#include "lwip/udp.h"
#include "lwip/stats.h"
#include "lwip/sys.h"
#include "lwip/ip_addr.h"
#include <platform/platform_stdlib.h>
#define CONFIG_DHCPS_KEPT_CLIENT_INFO
#define DHCP_POOL_START 100
#define DHCP_POOL_END 200
#define DHCPS_MAX_CLIENT_NUM (DHCP_POOL_END-DHCP_POOL_START+1)
#define IS_USE_FIXED_IP 0
#define debug_dhcps 0
/* dhcp server states */
#define DHCP_SERVER_STATE_OFFER (1)
#define DHCP_SERVER_STATE_DECLINE (2)
#define DHCP_SERVER_STATE_ACK (3)
#define DHCP_SERVER_STATE_NAK (4)
#define DHCP_SERVER_STATE_IDLE (5)
#define BOOTP_BROADCAST (0x8000)
#define DHCP_MESSAGE_OP_REQUEST (1)
#define DHCP_MESSAGE_OP_REPLY (2)
#define DHCP_MESSAGE_HTYPE (1)
#define DHCP_MESSAGE_HLEN (6)
#define DHCP_SERVER_PORT (67)
#define DHCP_CLIENT_PORT (68)
#define DHCP_MESSAGE_TYPE_DISCOVER (1)
#define DHCP_MESSAGE_TYPE_OFFER (2)
#define DHCP_MESSAGE_TYPE_REQUEST (3)
#define DHCP_MESSAGE_TYPE_DECLINE (4)
#define DHCP_MESSAGE_TYPE_ACK (5)
#define DHCP_MESSAGE_TYPE_NAK (6)
#define DHCP_MESSAGE_TYPE_RELEASE (7)
#define DHCP_OPTION_LENGTH_ONE (1)
#define DHCP_OPTION_LENGTH_TWO (2)
#define DHCP_OPTION_LENGTH_THREE (3)
#define DHCP_OPTION_LENGTH_FOUR (4)
#define DHCP_OPTION_CODE_SUBNET_MASK (1)
#define DHCP_OPTION_CODE_ROUTER (3)
#define DHCP_OPTION_CODE_DNS_SERVER (6)
#define DHCP_OPTION_CODE_INTERFACE_MTU (26)
#define DHCP_OPTION_CODE_BROADCAST_ADDRESS (28)
#define DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY (31)
#define DHCP_OPTION_CODE_REQUEST_IP_ADDRESS (50)
#define DHCP_OPTION_CODE_LEASE_TIME (51)
#define DHCP_OPTION_CODE_MSG_TYPE (53)
#define DHCP_OPTION_CODE_SERVER_ID (54)
#define DHCP_OPTION_CODE_REQ_LIST (55)
#define DHCP_OPTION_CODE_END (255)
#define IP_FREE_TO_USE (1)
#define IP_ALREADY_IN_USE (0)
#define HW_ADDRESS_LENGTH (6)
/* Reference by RFC 2131 */
struct dhcp_msg {
uint8_t op; /* Message op code/message type. 1 = BOOTREQUEST, 2 = BOOTREPLY */
uint8_t htype; /* Hardware address type */
uint8_t hlen; /* Hardware address length */
uint8_t hops; /* Client sets to zero, optionally used by relay agents
when booting via a relay agent */
uint8_t xid[4]; /* Transaction ID, a random number chosen by the client,
used by the client and server to associate messages and
responses between a client and a server */
uint16_t secs; /* Filled in by client, seconds elapsed since client began address
acquisition or renewal process.*/
uint16_t flags; /* bit 0: Broadcast flag, bit 1~15:MBZ must 0*/
uint8_t ciaddr[4]; /* Client IP address; only filled in if client is in BOUND,
RENEW or REBINDING state and can respond to ARP requests. */
uint8_t yiaddr[4]; /* 'your' (client) IP address */
uint8_t siaddr[4]; /* IP address of next server to use in bootstrap;
returned in DHCPOFFER, DHCPACK by server. */
uint8_t giaddr[4]; /* Relay agent IP address, used in booting via a relay agent.*/
uint8_t chaddr[16]; /* Client hardware address */
uint8_t sname[64]; /* Optional server host name, null terminated string.*/
uint8_t file[128]; /* Boot file name, null terminated string; "generic" name or
null in DHCPDISCOVER, fully qualified directory-path name in DHCPOFFER.*/
uint8_t options[312]; /* Optional parameters field. reference the RFC 2132 */
};
/* use this to check whether the message is dhcp related or not */
static const uint8_t dhcp_magic_cookie[4] = {99, 130, 83, 99};
static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x1c, 0x20}; //1 day
//static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x0e, 0x10}; // one hour
//static const uint8_t dhcp_option_interface_mtu_576[] = {0x02, 0x40};
static const uint8_t dhcp_option_interface_mtu[] = {0x05, 0xDC};
struct table {
uint32_t ip_range[8];
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
uint8_t client_mac[256][6];
#endif
};
struct address_pool{
uint32_t start;
uint32_t end;
};
/* 01~32 */
#define MARK_RANGE1_IP_BIT(table, ip) ((table.ip_range[0]) | (1 << ((ip) - 1)))
/* 33~64 */
#define MARK_RANGE2_IP_BIT(table, ip) ((table.ip_range[1]) | (1 << ((ip) - 1)))
/* 65~96 */
#define MARK_RANGE3_IP_BIT(table, ip) ((table.ip_range[2]) | (1 << ((ip) - 1)))
/* 97~128 */
#define MARK_RANGE4_IP_BIT(table, ip) ((table.ip_range[3]) | (1 << ((ip) - 1)))
/* 129~160 */
#define MARK_RANGE5_IP_BIT(table, ip) ((table.ip_range[4]) | (1 << ((ip) - 1)))
/* 161~192 */
#define MARK_RANGE6_IP_BIT(table, ip) ((table.ip_range[5]) | (1 << ((ip) - 1)))
/* 193~224 */
#define MARK_RANGE7_IP_BIT(table, ip) ((table.ip_range[6]) | (1 << ((ip) - 1)))
/* 225~255 */
#define MARK_RANGE8_IP_BIT(table, ip) ((table.ip_range[7]) | (1 << ((ip) - 1)))
/* expose API */
void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end);
void dhcps_init(struct netif * pnetif);
void dhcps_deinit(void);
extern struct netif *netif_default;
#endif /*__DHCPS_H__*/

3
targets/TARGET_Realtek/mbed_rtx.h
View File

@ -1,3 +1,4 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
@ -40,4 +41,4 @@
#endif
#endif
#endif
#endif

34
targets/targets.json
View File

@ -635,6 +635,12 @@
"network-default-interface-type": "ETHERNET"
}
},
"SDT64B": {
"inherits": ["K64F"],
"extra_labels_add": ["K64F"],
"extra_labels_remove": ["FRDM"],
"detect_code": ["3105"]
},
"EV_COG_AD4050LZ": {
"inherits": ["Target"],
"core": "Cortex-M4F",
@ -2907,6 +2913,16 @@
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
"release_versions": ["2", "5"]
},
"SDT32620B": {
"inherits": ["Target"],
"core": "Cortex-M4F",
"macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32620","TARGET_REV=0x4332","OPEN_DRAIN_LEDS"],
"detect_code": ["3101"],
"extra_labels": ["Maxim", "MAX32620C"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
"release_versions": ["2", "5"]
},
"MAX32625_BASE": {
"inherits": ["Target"],
"core": "Cortex-M4F",
@ -2922,6 +2938,11 @@
"inherits": ["MAX32625_BASE"],
"extra_labels_add": ["MAX32625_NO_BOOT"]
},
"SDT32625B": {
"inherits": ["MAX32625_BASE"],
"extra_labels_add": ["MAX32625_NO_BOOT"],
"detect_code": ["3102"]
},
"MAX32625PICO": {
"inherits": ["MAX32625_BASE"],
"extra_labels_add": ["MAX32625_BOOT"],
@ -3681,6 +3702,13 @@
"release_versions": ["2", "5"],
"device_name": "nRF51822_xxAA"
},
"SDT51822B": {
"inherits": ["MCU_NRF51_32K_UNIFIED"],
"device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"detect_code": ["3103"],
"release_versions": ["2", "5"],
"device_name": "nRF51822_xxAA"
},
"NRF51_DONGLE": {
"inherits": ["MCU_NRF51_32K_UNIFIED"],
"progen": {"target": "nrf51-dongle"},
@ -3763,6 +3791,12 @@
"release_versions": ["5"],
"device_name": "nRF52832_xxAA"
},
"SDT52832B": {
"inherits": ["MCU_NRF52832"],
"release_versions": ["5"],
"detect_code": ["3104"],
"device_name": "nRF52832_xxAA"
},
"UBLOX_EVA_NINA": {
"inherits": ["MCU_NRF52832"],
"release_versions": ["5"],