mirror of https://github.com/ARMmbed/mbed-os.git
HAL: Serial: Update the header file doxy
Clarified defined/undefined behavior.pull/11032/head
parent
7aea44f0cf
commit
e98cc2077e
131
hal/serial_api.h
131
hal/serial_api.h
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@ -70,9 +70,11 @@ typedef enum {
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ParityForced0 = 4
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} SerialParity;
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/** Serial interrupt sources
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*/
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typedef enum {
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RxIrq,
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TxIrq
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RxIrq, /**< Receive Data Register Full */
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TxIrq /**< Transmit Data Register Empty */
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} SerialIrq;
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typedef enum {
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@ -109,61 +111,95 @@ extern "C" {
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/**
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* \defgroup hal_GeneralSerial Serial Configuration Functions
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*
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* # Defined behaviour
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* * ::serial_init initializes the serial peripheral
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* # Defined behavior
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* * ::serial_init initializes the serial peripheral.
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* * ::serial_init sets the default parameters for serial peripheral
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* * ::serial_init configures its specified pins
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* * ::serial_free releases the serial peripheral
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^^^ FIXME, are the defaults given, or platform specific?
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Set to 9600, 8N1? Use MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE?
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* * ::serial_init configures its specified pins.
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* * ::serial_free releases the serial peripheral.
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* * ::serial_baud configures the baud rate
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* ^^^ FIXME, are any baudrates mandatory?
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* * ::serial_format configures the transmission format (number of bits, parity and the number of stop bits)
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* * ::serial_irq_handler registers the interrupt handler which will be invoked when the interrupt fires
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* * ::serial_irq_set enables or disables serial irq (RX or TX)
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* * ::serial_getc returns the character from serial buffer
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* * ::serial_getc is a blocking call (waits for the character)
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* * ::serial_putc sends a character
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* * ::serial_putc is a blocking call (waits for a peripheral to be available)
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* * ::serial_readable returns non-zero value if a character can be read, 0 if nothing to read
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* * ::serial_writable returns non-zero value if a character can be written, 0 otherwise
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^^^ FIXME, which values are mandatory?
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Any other than 8N1?
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* * ::serial_irq_handler registers the interrupt handler which will be invoked when the interrupt fires.
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* * ::serial_irq_set enables or disables the serial RX or TX IRQ.
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* * If `RxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever
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* Receive Data Register Full IRQ is generated.
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* * If `TxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever
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* Transmit Data Register Empty IRQ is generated.
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* * If the interrupt condition holds true, when the interrupt is enabled with ::serial_irq_set,
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* the ::serial_irq_handler is called instantly.
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* * ::serial_getc returns the character from serial buffer.
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* * ::serial_getc is a blocking call (waits for the character).
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* * ::serial_putc sends a character.
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* * ::serial_putc is a blocking call (waits for a peripheral to be available).
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* * ::serial_readable returns non-zero value if a character can be read, 0 otherwise.
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* * ::serial_writable returns non-zero value if a character can be written, 0 otherwise.
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* * ::serial_clear clears the serial peripheral
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* * ::serial_break_set sets the break signal
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* * ::serial_pinout_tx configures the TX pin for UART function
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* * ::serial_set_flow_control configures serial flow control
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* * ::serial_set_flow_control sets flow control in the hardware if a serial peripheral supports it, otherwise software emulation is used
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* * ::serial_tx_asynch starts the serial asynchronous transfer
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* * ::serial_tx_asynch writes `tx_length` bytes from the `tx` to the bus
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* * The callback given to ::serial_tx_asynch is invoked when the transfer completes
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* * ::serial_tx_asynch specifies the logical OR of events to be registered
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* * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm
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* * ::serial_rx_asynch starts the serial asynchronous transfer
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* * ::serial_rx_asynch reads `rx_length` bytes to the `rx`buffer
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* * The callback given to ::serial_rx_asynch is invoked when the transfer completes
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* * ::serial_tx_asynch specifies the logical OR of events to be registered
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* * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm
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* * ::serial_tx_asynch specifies the character in range 0-254 to be matched
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* * ::serial_tx_active returns non-zero if the TX transaction is ongoing, 0 otherwise
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* * ::serial_rx_active returns non-zero if the RX transaction is ongoing, 0 otherwise
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* * ::serial_irq_handler_asynch returns event flags if an RX transfer termination condition was met, otherwise returns 0
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* * ::serial_tx_abort_asynch aborts the ongoing TX transaction
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* * ::serial_tx_abort_asynch disables the enabled interupt for TX
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* * ::serial_tx_abort_asynch flushes the TX hardware buffer if TX FIFO is used
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* * ::serial_rx_abort_asynch aborts the ongoing RX transaction
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* * ::serial_rx_abort_asynch disables the enabled interupt for RX
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* * ::serial_rx_abort_asynch flushes the TX hardware buffer if RX FIFO is used
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^^^ FIXME, what does that actually mean?
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Reset both RX and TX FIFOs (and shift registers)?
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* * ::serial_break_set sets the break signal.
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* * ::serial_break_clear clears the break signal.
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* * ::serial_pinout_tx configures the TX pin as an output (to be used in half-duplex mode).
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* * ::serial_set_flow_control configures serial flow control.
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* * ::serial_set_flow_control sets flow control in the hardware if a serial peripheral supports it,
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* otherwise software emulation is used.
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* * ::serial_tx_asynch starts the serial asynchronous transfer.
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* * ::serial_tx_asynch writes `tx_length` bytes from the `tx` to the bus.
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* * ::serial_tx_asynch ignores the `tx_width` argument
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^^^ FIXME, is this valid; does deprecated == ignored?
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* * The callback given to ::serial_tx_asynch is invoked when the transfer completes.
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* * ::serial_tx_asynch specifies the logical OR of events to be registered.
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* * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm.
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* * ::serial_rx_asynch starts the serial asynchronous transfer.
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* * ::serial_rx_asynch reads `rx_length` bytes to the `rx` buffer.
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* * ::serial_rx_asynch ignores the `rx_width` argument
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^^^ FIXME, is this valid; does deprecated == ignored?
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* * The callback given to ::serial_rx_asynch is invoked when the transfer completes.
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* * ::serial_rx_asynch specifies the logical OR of events to be registered.
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* * The ::serial_rx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm.
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* * ::serial_rx_asynch specifies a character in range 0-254 to be matched, 255 is a reserved value.
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* * If SERIAL_EVENT_RX_CHARACTER_MATCH event is not registered, the `char_match` is ignored.
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* * The SERIAL_EVENT_RX_CHARACTER_MATCH event is set in the callback when SERIAL_EVENT_RX_CHARACTER_MATCH event is
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* registered AND `char_match` is present in the received data.
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* * ::serial_tx_active returns non-zero if the TX transaction is ongoing, 0 otherwise.
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* * ::serial_rx_active returns non-zero if the RX transaction is ongoing, 0 otherwise.
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* * ::serial_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise returns 0.
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* * ::serial_irq_handler_asynch takes no longer than one packet transfer time (packet_bits / baudrate) to execute.
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* * ::serial_tx_abort_asynch aborts the ongoing TX transaction.
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* * ::serial_tx_abort_asynch disables the enabled interupt for TX.
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* * ::serial_tx_abort_asynch flushes the TX hardware buffer if TX FIFO is used.
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* * ::serial_rx_abort_asynch aborts the ongoing RX transaction.
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* * ::serial_rx_abort_asynch disables the enabled interupt for RX.
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* * ::serial_rx_abort_asynch flushes the TX hardware buffer if RX FIFO is used.
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* * Correct operation guaranteed when interrupt latency is shorter than one packet transfer time (packet_bits / baudrate)
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* if the flow control is not used.
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* * Correct operation guaranteed regardless of interrupt latency if the flow control is used.
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*
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* # Undefined behaviour
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*
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* * Calling ::serial_init multiple times on the same `serial_t` without ::serial_free
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* * Passing invalid pin to ::serial_init, ::serial_pinout_tx
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* * Calling any function other than ::serial_init on a non-initialized or freed `serial_t`
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* * Passing an invalid pointer as `obj` to any function
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* * Passing an invalid pointer as `handler` to ::serial_irq_handler, ::serial_tx_asynch, ::serial_rx_asynch
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* * Calling ::spi_abort while no async transfer is being processed (no transfer or a synchronous transfer)
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* # Undefined behavior
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* * Calling ::serial_init multiple times on the same `serial_t` without ::serial_free.
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* * Passing invalid pin to ::serial_init, ::serial_pinout_tx.
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* * Calling any function other than ::serial_init on am uninitialized or freed `serial_t`.
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* * Passing an invalid pointer as `obj` to any function.
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* * Passing an invalid pointer as `handler` to ::serial_irq_handler, ::serial_tx_asynch, ::serial_rx_asynch.
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* * Calling ::serial_tx_abort while no async TX transfer is being processed.
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* * Calling ::serial_rx_abort while no async RX transfer is being processed.
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* * Devices behavior is undefined when the interrupt latency is longer than one packet transfer time
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* (packet_bits / baudrate) if the flow control is not used.
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* @{
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*/
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/**
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* \defgroup hal_GeneralSerial_tests Serial hal tests
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* The Serial HAL tests ensure driver conformance to defined behaviour.
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* The Serial HAL tests ensure driver conformance to defined behavior.
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*
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* To run the Serial hal tests use the command:
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*
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@ -353,7 +389,6 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
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* @param rx_width Deprecated argument
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* @param handler The serial handler
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* @param event The logical OR of events to be registered
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* @param handler The serial handler
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* @param char_match A character in range 0-254 to be matched
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* @param hint A suggestion for how to use DMA with this transfer
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*/
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