mirror of https://github.com/ARMmbed/mbed-os.git
Add header files to fpga tests, update test names
Przemyslaw Stekiel
parent
1bbcc8fd56
commit
7aea44f0cf
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@ -0,0 +1,60 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/** \addtogroup hal_analogin_tests */
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/** @{*/
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#ifndef MBED_FPGA_ANALOG_IN_TEST_H
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#define MBED_FPGA_ANALOG_IN_TEST_H
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#if DEVICE_ANALOGIN
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Test that the alalogin can be initialized using all possible analogin pins.
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*
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* Given board provides analogin support.
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* When analogin is initialized using valid analogin pin.
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* Then the operation is successfull.
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*
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*/
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void fpga_analogin_init_test(PinName pin);
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/** Test that analogin correctly interprets given input voltage.
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*
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* Given board provides analogin support.
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* When 0.0/3.3 V is provided to analogin pin.
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* Then analogin_read returns 0.0/1.0,
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* analogin_read_u16 returns 0/65535.
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*
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*/
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void fpga_analogin_test(PinName pin);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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/**@}*/
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@ -26,11 +26,11 @@
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#include "utest/utest.h"
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#include "unity/unity.h"
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#include "greentea-client/test_env.h"
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#include "mbed.h"
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#include "pinmap.h"
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#include "test_utils.h"
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#include "MbedTester.h"
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#include "analogin_fpga_test.h"
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using namespace utest::v1;
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@ -44,14 +44,14 @@ const PinList *restricted = pinmap_restricted_pins();
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MbedTester tester(form_factor, restricted);
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void analogin_init(PinName pin)
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void fpga_analogin_init_test(PinName pin)
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{
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analogin_t analogin;
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analogin_init(&analogin, pin);
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}
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void analogin_test(PinName pin)
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void fpga_analogin_test(PinName pin)
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{
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tester.reset();
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tester.pin_map_set(pin, MbedTester::LogicalPinGPIO0);
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@ -76,9 +76,9 @@ void analogin_test(PinName pin)
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Case cases[] = {
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// This will be run for all pins
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Case("AnalogIn - init test", all_ports<AnaloginPort, DefaultFormFactor, analogin_init>),
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Case("AnalogIn - init test", all_ports<AnaloginPort, DefaultFormFactor, fpga_analogin_init_test>),
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// This will be run for single pin
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Case("AnalogIn - read test", all_ports<AnaloginPort, DefaultFormFactor, analogin_test>),
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Case("AnalogIn - read test", all_ports<AnaloginPort, DefaultFormFactor, fpga_analogin_test>),
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};
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utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
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@ -0,0 +1,61 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/** \addtogroup hal_gpio_tests */
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/** @{*/
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#ifndef MBED_FPGA_GPIO_TEST_H
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#define MBED_FPGA_GPIO_TEST_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Test basic input & output operations.
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*
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* Given a GPIO instance initialized with a generic gpio_init() function,
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* when basic input and output operations are performed,
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* then all operations succeed.
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*/
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void fpga_test_basic_input_output(PinName pin);
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/* Test explicit input initialization.
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*
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* Given a GPIO instance,
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* when additional parameters are passed to the input init function,
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* then the GPIO is correctly initialized as an input.
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*/
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void fpga_test_explicit_input(PinName pin);
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/* Test explicit output initialization.
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*
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* Given a GPIO instance,
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* when additional parameters are passed to the output init function,
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* then the GPIO is correctly initialized as an output.
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*/
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void fpga_test_explicit_output(PinName pin);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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/**@}*/
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@ -25,12 +25,12 @@
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#include "unity/unity.h"
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#include "greentea-client/test_env.h"
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#include "mbed.h"
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using namespace utest::v1;
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#include "MbedTester.h"
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#include "pinmap.h"
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#include "test_utils.h"
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#include "gpio_fpga_test.h"
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using namespace utest::v1;
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// This delay is used when reading a floating input that has an internal pull-up
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// or pull-down resistor. The voltage response is much slower when the input
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@ -45,7 +45,7 @@ MbedTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins(
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* when basic input and output operations are performed,
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* then all operations succeed.
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*/
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void test_basic_input_output(PinName pin)
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void fpga_test_basic_input_output(PinName pin)
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{
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// Reset everything and set all tester pins to hi-Z.
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tester.reset();
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@ -128,7 +128,7 @@ void test_basic_input_output(PinName pin)
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* when additional parameters are passed to the input init function,
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* then the GPIO is correctly initialized as an input.
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*/
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void test_explicit_input(PinName pin)
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void fpga_test_explicit_input(PinName pin)
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{
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// Reset everything and set all tester pins to hi-Z.
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tester.reset();
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@ -180,7 +180,7 @@ void test_explicit_input(PinName pin)
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* when additional parameters are passed to the output init function,
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* then the GPIO is correctly initialized as an output.
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*/
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void test_explicit_output(PinName pin)
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void fpga_test_explicit_output(PinName pin)
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{
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// Reset everything and set all tester pins to hi-Z.
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tester.reset();
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@ -0,0 +1,58 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/** \addtogroup hal_gpioirq_tests */
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/** @{*/
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#ifndef MBED_FPGA_GPIO_IRQ_TEST_H
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#define MBED_FPGA_GPIO_IRQ_TEST_H
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#if DEVICE_INTERRUPTIN
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Test that the GPIO IRQ can be initialized/de-initialized using all possible
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* GPIO IRQ pins.
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*
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* Given board provides GPIO IRQ support.
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* When GPIO IRQ is initialized (and then de-initialized) using valid GPIO IRQ pin.
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* Then the operation is successfull.
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*
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*/
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void fpga_gpio_irq_test(PinName pin);
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/** Test that the gpio interrupt is generated correctly.
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*
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* Given board provides interrupt-in feature.
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* When gpio interrupt is configured to fire on rasing/falling/both edge(s).
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* Then on rasing/falling/any edge registered interrupt handler is called.
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*
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*/
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void fpga_gpio_irq_init_free_test(PinName pin);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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/**@}*/
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@ -27,6 +27,9 @@
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#include "unity/unity.h"
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#include "greentea-client/test_env.h"
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#include "mbed.h"
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#include "MbedTester.h"
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#include "pinmap.h"
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#include "gpio_irq_fpga_test.h"
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using namespace utest::v1;
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@ -44,7 +47,7 @@ void test_gpio_irq_handler(uint32_t id, gpio_irq_event event)
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#define WAIT() wait_us(10)
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void gpio_irq_test(PinName pin)
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void fpga_gpio_irq_test(PinName pin)
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{
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// Reset everything and set all tester pins to hi-Z.
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tester.reset();
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@ -250,7 +253,7 @@ void gpio_irq_test(PinName pin)
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gpio_irq_free(&gpio_irq);
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}
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void init_free_test(PinName pin)
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void fpga_gpio_irq_init_free_test(PinName pin)
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{
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gpio_t gpio;
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gpio_irq_t gpio_irq;
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@ -260,8 +263,8 @@ void init_free_test(PinName pin)
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}
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Case cases[] = {
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Case("init/free", all_ports<GPIOIRQPort, DefaultFormFactor, init_free_test>),
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Case("rising & falling edge", all_ports<GPIOIRQPort, DefaultFormFactor, gpio_irq_test>),
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Case("init/free", all_ports<GPIOIRQPort, DefaultFormFactor, fpga_gpio_irq_init_free_test>),
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Case("rising & falling edge", all_ports<GPIOIRQPort, DefaultFormFactor, fpga_gpio_irq_test>),
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};
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utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
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@ -0,0 +1,86 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/** \addtogroup hal_GeneralI2C_tests */
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/** @{*/
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#ifndef MBED_FPGA_I2C_TEST_H
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#define MBED_FPGA_I2C_TEST_H
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#if DEVICE_I2C
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Test that the i2c-master can be initialized/de-initialized using all possible
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* i2c pins.
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*
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* Given board provides i2c-master support.
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* When i2c-master is initialized (and then de-initialized) using valid set of i2c pins.
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* Then the operation is successfull.
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*
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*/
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void fpga_test_i2c_init_free(PinName sda, PinName scl);
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/** Test that I2C master is able to read data from I2C bus using i2c_byte_read.
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*
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* Given board provides I2C master support.
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* When I2C master reads data from I2C bus using i2c_byte_read.
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* Then data is successfully read.
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*
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*/
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void fpga_i2c_test_byte_read(PinName sda, PinName scl);
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/** Test that I2C master is able to write data to I2C bus using i2c_byte_write.
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*
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* Given board provides I2C master support.
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* When I2C master writes data to the I2C bus using i2c_byte_write.
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* Then data is successfully transmitted.
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*
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*/
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void fpga_i2c_test_byte_write(PinName sda, PinName scl);
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/** Test that I2C master is able to read data from I2C bus using i2c_read.
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*
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* Given board provides I2C master support.
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* When I2C master reads data from I2C bus using i2c_read.
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* Then data is successfully read.
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*
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*/
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void fpga_i2c_test_read(PinName sda, PinName scl);
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/** Test that I2C master is able to write data to I2C bus using i2c_write.
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*
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* Given board provides I2C master support.
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* When I2C master writes data to the I2C bus using i2c_write.
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* Then data is successfully transmitted.
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*
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*/
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void fpga_i2c_test_write(PinName sda, PinName scl);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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/**@}*/
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@ -26,14 +26,12 @@
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#include "utest/utest.h"
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#include "unity/unity.h"
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#include "greentea-client/test_env.h"
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#include "mbed.h"
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#include "mbed.h"
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#include "i2c_api.h"
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#include "pinmap.h"
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#include "test_utils.h"
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#include "I2CTester.h"
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#include "i2c_fpga_test.h"
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using namespace utest::v1;
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@ -45,7 +43,7 @@ const int TRANSFER_COUNT = 300;
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I2CTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
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void test_i2c_init_free(PinName sda, PinName scl)
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void fpga_test_i2c_init_free(PinName sda, PinName scl)
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{
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i2c_t obj = {};
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memset(&obj, 0, sizeof(obj));
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@ -66,7 +64,7 @@ void test_i2c_init_free(PinName sda, PinName scl)
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gpio_set(scl);
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}
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void i2c_test_write(PinName sda, PinName scl)
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void fpga_i2c_test_write(PinName sda, PinName scl)
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{
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// Remap pins for test
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tester.reset();
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@ -153,7 +151,7 @@ void i2c_test_write(PinName sda, PinName scl)
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tester.pin_set_pull(scl, MbedTester::PullNone);
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}
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void i2c_test_read(PinName sda, PinName scl)
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void fpga_i2c_test_read(PinName sda, PinName scl)
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{
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// Remap pins for test
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tester.reset();
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@ -239,7 +237,7 @@ void i2c_test_read(PinName sda, PinName scl)
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tester.pin_set_pull(scl, MbedTester::PullNone);
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}
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void i2c_test_byte_write(PinName sda, PinName scl)
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void fpga_i2c_test_byte_write(PinName sda, PinName scl)
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{
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// Remap pins for test
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tester.reset();
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@ -336,7 +334,7 @@ void i2c_test_byte_write(PinName sda, PinName scl)
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tester.pin_set_pull(scl, MbedTester::PullNone);
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}
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void i2c_test_byte_read(PinName sda, PinName scl)
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void fpga_i2c_test_byte_read(PinName sda, PinName scl)
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{
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// Remap pins for test
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tester.reset();
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@ -437,11 +435,11 @@ void i2c_test_byte_read(PinName sda, PinName scl)
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}
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Case cases[] = {
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Case("i2c - init/free test all pins", one_peripheral<I2CPort, DefaultFormFactor, test_i2c_init_free>),
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Case("i2c - test write i2c API", one_peripheral<I2CPort, DefaultFormFactor, i2c_test_write>),
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Case("i2c - test read i2c API", one_peripheral<I2CPort, DefaultFormFactor, i2c_test_read>),
|
||||
Case("i2c - test single byte write i2c API", one_peripheral<I2CPort, DefaultFormFactor, i2c_test_byte_write>),
|
||||
Case("i2c - test single byte read i2c API", one_peripheral<I2CPort, DefaultFormFactor, i2c_test_byte_read>)
|
||||
Case("i2c - init/free test all pins", one_peripheral<I2CPort, DefaultFormFactor, fpga_test_i2c_init_free>),
|
||||
Case("i2c - test write i2c API", one_peripheral<I2CPort, DefaultFormFactor, fpga_i2c_test_write>),
|
||||
Case("i2c - test read i2c API", one_peripheral<I2CPort, DefaultFormFactor, fpga_i2c_test_read>),
|
||||
Case("i2c - test single byte write i2c API", one_peripheral<I2CPort, DefaultFormFactor, fpga_i2c_test_byte_write>),
|
||||
Case("i2c - test single byte read i2c API", one_peripheral<I2CPort, DefaultFormFactor, fpga_i2c_test_byte_read>)
|
||||
};
|
||||
|
||||
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
|
||||
|
|
|
|||
|
|
@ -27,12 +27,12 @@
|
|||
#include "unity/unity.h"
|
||||
#include "greentea-client/test_env.h"
|
||||
#include "mbed.h"
|
||||
|
||||
using namespace utest::v1;
|
||||
|
||||
#include "MbedTester.h"
|
||||
#include "pinmap.h"
|
||||
#include "test_utils.h"
|
||||
#include "pwm_fpga_test.h"
|
||||
|
||||
using namespace utest::v1;
|
||||
|
||||
|
||||
#define pwm_debug_printf(...)
|
||||
|
|
@ -63,7 +63,7 @@ typedef enum {
|
|||
MbedTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
|
||||
|
||||
|
||||
void pwm_init_free(PinName pin)
|
||||
void fpga_pwm_init_free(PinName pin)
|
||||
{
|
||||
pwmout_t pwm_out;
|
||||
|
||||
|
|
@ -74,7 +74,7 @@ void pwm_init_free(PinName pin)
|
|||
}
|
||||
|
||||
|
||||
void pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pwm_api_test_t api_test)
|
||||
void fpga_pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pwm_api_test_t api_test)
|
||||
{
|
||||
pwm_debug_printf("PWM test on pin = %s (%i)\r\n", pinmap_ff_default_pin_to_string(pin), pin);
|
||||
pwm_debug_printf("Testing period = %lu ms, duty-cycle = %lu %%\r\n", period_ms, fill_prc);
|
||||
|
|
@ -157,59 +157,59 @@ void pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pw
|
|||
}
|
||||
|
||||
template<uint32_t period_ms, uint32_t fill_prc, pwm_api_test_t api_test>
|
||||
void pwm_period_fill_test(PinName pin)
|
||||
void fpga_pwm_period_fill_test(PinName pin)
|
||||
{
|
||||
pwm_period_fill_test(pin, period_ms, fill_prc, api_test);
|
||||
fpga_pwm_period_fill_test(pin, period_ms, fill_prc, api_test);
|
||||
}
|
||||
|
||||
|
||||
Case cases[] = {
|
||||
// This will be run for all pins
|
||||
Case("PWM - init/free test", all_ports<PWMPort, DefaultFormFactor, pwm_init_free>),
|
||||
Case("PWM - init/free test", all_ports<PWMPort, DefaultFormFactor, fpga_pwm_init_free>),
|
||||
|
||||
// This will be run for single pin
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 10, PERIOD_WRITE> >),
|
||||
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_PULSEWIDTH_US> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 10, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 10, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 10, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 10, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 10, PERIOD_PULSEWIDTH_US> >),
|
||||
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 50, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 50, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 50, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 50, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 50, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 50, PERIOD_PULSEWIDTH_US> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 50, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 50, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 50, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 50, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 50, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 50, PERIOD_PULSEWIDTH_US> >),
|
||||
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 90, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 90, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 90, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH_US> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH_US> >),
|
||||
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 10, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 10, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 10, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH_US> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH_US> >),
|
||||
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 50, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 50, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 50, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH_US> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH_US> >),
|
||||
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 90, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 90, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 90, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH_US> >)
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_MS_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_US_WRITE> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH_MS> >),
|
||||
Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH_US> >)
|
||||
};
|
||||
|
||||
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,61 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2019 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/** \addtogroup hal_pwmout_tests */
|
||||
/** @{*/
|
||||
|
||||
#ifndef MBED_FPGA_PWM_TEST_H
|
||||
#define MBED_FPGA_PWM_TEST_H
|
||||
|
||||
#if DEVICE_PWM
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Test that the PWM can be initialized/de-initialized using all possible
|
||||
* PWM pins.
|
||||
*
|
||||
* Given board provides PWM support.
|
||||
* When PWM is initialized (and then de-initialized) using valid PWM pin.
|
||||
* Then the operation is successfull.
|
||||
*
|
||||
*/
|
||||
void fpga_pwm_init_free(PinName pin);
|
||||
|
||||
/** Test that pwmout_period, pwmout_period_ms, pwmout_period_us functions sets the
|
||||
* PWM period correctly and pwmout_write, pwmout_pulsewidth, pwmout_pulsewidth_ms,
|
||||
* pwmout_pulsewidth_us functions sets the pulse width correctly.
|
||||
*
|
||||
* Given board provides PWM support.
|
||||
* When PWM period/width is set using pwmout_period, pwmout_period_ms, pwmout_period_us/pwmout_write, pwmout_pulsewidth, pwmout_pulsewidth_ms, pwmout_pulsewidth_us
|
||||
* Then the valid PWM puswidth and period is on output.
|
||||
*
|
||||
*/
|
||||
void fpga_pwm_period_fill_test(PinName pin);
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
|
|
@ -27,12 +27,13 @@
|
|||
#include "unity/unity.h"
|
||||
#include "greentea-client/test_env.h"
|
||||
#include "mbed.h"
|
||||
|
||||
using namespace utest::v1;
|
||||
|
||||
#include "SPIMasterTester.h"
|
||||
#include "pinmap.h"
|
||||
#include "test_utils.h"
|
||||
#include "spi_fpga_test.h"
|
||||
|
||||
using namespace utest::v1;
|
||||
|
||||
|
||||
typedef enum {
|
||||
TRANSFER_SPI_MASTER_WRITE_SYNC,
|
||||
|
|
@ -61,7 +62,7 @@ void spi_async_handler()
|
|||
}
|
||||
#endif
|
||||
|
||||
void spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
{
|
||||
spi_init(&spi, mosi, miso, sclk, ssel);
|
||||
spi_format(&spi, 8, SPITester::Mode0, 0);
|
||||
|
|
@ -69,7 +70,7 @@ void spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
|||
spi_free(&spi);
|
||||
}
|
||||
|
||||
void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
|
||||
void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
|
||||
{
|
||||
uint32_t sym_mask = ((1 << sym_size) - 1);
|
||||
|
||||
|
|
@ -161,32 +162,32 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI
|
|||
}
|
||||
|
||||
template<SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency>
|
||||
void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
{
|
||||
spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, frequency);
|
||||
fpga_spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, frequency);
|
||||
}
|
||||
|
||||
Case cases[] = {
|
||||
// This will be run for all pins
|
||||
Case("SPI - init/free test all pins", all_ports<SPIPort, DefaultFormFactor, spi_test_init_free>),
|
||||
Case("SPI - init/free test all pins", all_ports<SPIPort, DefaultFormFactor, fpga_spi_test_init_free>),
|
||||
|
||||
// This will be run for all peripherals
|
||||
Case("SPI - basic test", all_peripherals<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - basic test", all_peripherals<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
|
||||
// This will be run for single pin configuration
|
||||
Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
|
||||
Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
|
||||
Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
|
||||
Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),
|
||||
Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
|
||||
Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),
|
||||
|
||||
Case("SPI - block write", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
Case("SPI - block write", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ> >),
|
||||
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
Case("SPI - async mode", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ> >)
|
||||
Case("SPI - async mode", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ> >)
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,59 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2019 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/** \addtogroup hal_GeneralSPI_tests */
|
||||
/** @{*/
|
||||
|
||||
#ifndef MBED_FPGA_SPI_TEST_H
|
||||
#define MBED_FPGA_SPI_TEST_H
|
||||
|
||||
#if DEVICE_SPI
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Test that the spi-Master can be initialized/de-initialized using all possible
|
||||
* SPI pins.
|
||||
*
|
||||
* Given board provides SPI-Master support.
|
||||
* When SPI-Master is initialized (and then de-initialized) using valid set of SPI pins.
|
||||
* Then the operation is successfull.
|
||||
*
|
||||
*/
|
||||
void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel);
|
||||
|
||||
/** Test that the SPI-Master transfer can be performed in various configurations.
|
||||
*
|
||||
* Given board provides SPI-Master support.
|
||||
* When SPI transmission is performed using different settings.
|
||||
* Then data is successfully transfered.
|
||||
*
|
||||
*/
|
||||
void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel);
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
|
|
@ -26,17 +26,16 @@
|
|||
#include "utest/utest.h"
|
||||
#include "unity/unity.h"
|
||||
#include "greentea-client/test_env.h"
|
||||
|
||||
#include "platform/mbed_critical.h"
|
||||
|
||||
using namespace utest::v1;
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "UARTTester.h"
|
||||
#include "pinmap.h"
|
||||
#include "test_utils.h"
|
||||
#include "serial_api.h"
|
||||
#include "us_ticker_api.h"
|
||||
#include "uart_fpga_test.h"
|
||||
|
||||
using namespace utest::v1;
|
||||
|
||||
#define PUTC_REPS 16
|
||||
#define GETC_REPS 16
|
||||
|
|
@ -274,7 +273,7 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i
|
|||
tester.reset();
|
||||
}
|
||||
|
||||
void test_init_free(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC)
|
||||
void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC)
|
||||
{
|
||||
bool use_flow_control = (cts != NC && rts != NC) ? true : false;
|
||||
serial_t serial;
|
||||
|
|
@ -289,56 +288,56 @@ void test_init_free(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC)
|
|||
serial_free(&serial);
|
||||
}
|
||||
|
||||
void test_init_free_no_fc(PinName tx, PinName rx)
|
||||
void fpga_uart_init_free_test_no_fc(PinName tx, PinName rx)
|
||||
{
|
||||
test_init_free(tx, rx);
|
||||
fpga_uart_init_free_test(tx, rx);
|
||||
}
|
||||
|
||||
template<int BAUDRATE, int DATA_BITS, SerialParity PARITY, int STOP_BITS>
|
||||
void test_common(PinName tx, PinName rx, PinName cts, PinName rts)
|
||||
void fpga_uart_test_common(PinName tx, PinName rx, PinName cts, PinName rts)
|
||||
{
|
||||
uart_test_common(BAUDRATE, DATA_BITS, PARITY, STOP_BITS, tx, rx, cts, rts);
|
||||
}
|
||||
|
||||
template<int BAUDRATE, int DATA_BITS, SerialParity PARITY, int STOP_BITS>
|
||||
void test_common_no_fc(PinName tx, PinName rx)
|
||||
void fpga_uart_test_common_no_fc(PinName tx, PinName rx)
|
||||
{
|
||||
uart_test_common(BAUDRATE, DATA_BITS, PARITY, STOP_BITS, tx, rx);
|
||||
}
|
||||
|
||||
Case cases[] = {
|
||||
// Every set of pins from every peripheral.
|
||||
Case("init/free, FC off", all_ports<UARTNoFCPort, DefaultFormFactor, test_init_free_no_fc>),
|
||||
Case("init/free, FC off", all_ports<UARTNoFCPort, DefaultFormFactor, fpga_uart_init_free_test_no_fc>),
|
||||
|
||||
// One set of pins from every peripheral.
|
||||
Case("basic, 9600, 8N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, test_common_no_fc<9600, 8, ParityNone, 1> >),
|
||||
Case("basic, 9600, 8N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 1> >),
|
||||
|
||||
// One set of pins from one peripheral.
|
||||
// baudrate
|
||||
Case("19200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, test_common_no_fc<19200, 8, ParityNone, 1> >),
|
||||
Case("38400, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, test_common_no_fc<38400, 8, ParityNone, 1> >),
|
||||
Case("115200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, test_common_no_fc<115200, 8, ParityNone, 1> >),
|
||||
Case("19200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<19200, 8, ParityNone, 1> >),
|
||||
Case("38400, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<38400, 8, ParityNone, 1> >),
|
||||
Case("115200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<115200, 8, ParityNone, 1> >),
|
||||
// stop bits
|
||||
Case("9600, 8N2, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, test_common_no_fc<9600, 8, ParityNone, 2> >),
|
||||
Case("9600, 8N2, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 2> >),
|
||||
|
||||
#if DEVICE_SERIAL_FC
|
||||
// Every set of pins from every peripheral.
|
||||
Case("init/free, FC on", all_ports<UARTPort, DefaultFormFactor, test_init_free>),
|
||||
Case("init/free, FC on", all_ports<UARTPort, DefaultFormFactor, fpga_uart_init_free_test>),
|
||||
|
||||
// One set of pins from every peripheral.
|
||||
Case("basic, 9600, 8N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, test_common<9600, 8, ParityNone, 1> >),
|
||||
Case("basic, 9600, 8N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 1> >),
|
||||
|
||||
// One set of pins from one peripheral.
|
||||
// baudrate
|
||||
Case("19200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<19200, 8, ParityNone, 1> >),
|
||||
Case("38400, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<38400, 8, ParityNone, 1> >),
|
||||
Case("115200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<115200, 8, ParityNone, 1> >),
|
||||
Case("19200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<19200, 8, ParityNone, 1> >),
|
||||
Case("38400, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<38400, 8, ParityNone, 1> >),
|
||||
Case("115200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<115200, 8, ParityNone, 1> >),
|
||||
// data bits: not tested (some platforms support 8 bits only)
|
||||
// parity
|
||||
Case("9600, 8O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<9600, 8, ParityOdd, 1> >),
|
||||
Case("9600, 8E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<9600, 8, ParityEven, 1> >),
|
||||
Case("9600, 8O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityOdd, 1> >),
|
||||
Case("9600, 8E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityEven, 1> >),
|
||||
// stop bits
|
||||
Case("9600, 8N2, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<9600, 8, ParityNone, 2> >),
|
||||
Case("9600, 8N2, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 2> >),
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,82 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2019 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/** \addtogroup hal_GeneralSerial_tests */
|
||||
/** @{*/
|
||||
|
||||
#ifndef MBED_FPGA_UART_TEST_H
|
||||
#define MBED_FPGA_UART_TEST_H
|
||||
|
||||
#if DEVICE_UART
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Test that the uart can be initialized/de-initialized using all possible
|
||||
* uart pins (flow control enabled).
|
||||
*
|
||||
* Given board provides uart support with flow control.
|
||||
* When uart is initialized (and then de-initialized) using valid set of uart pins.
|
||||
* Then the operation is successfull.
|
||||
*
|
||||
*/
|
||||
void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts, PinName rts);
|
||||
|
||||
/** Test that the uart can be initialized/de-initialized using all possible
|
||||
* uart pins (flow control disabled).
|
||||
*
|
||||
* Given board provides uart support without flow control.
|
||||
* When uart is initialized (and then de-initialized) using valid set of uart pins.
|
||||
* Then the operation is successfull.
|
||||
*
|
||||
*/
|
||||
void fpga_uart_init_free_test_no_fc(PinName tx, PinName rx);
|
||||
{
|
||||
fpga_uart_init_free_test(tx, rx);
|
||||
}
|
||||
|
||||
/** Test that the uart transfer can be performed in various configurations (flow control enabled).
|
||||
*
|
||||
* Given board provides uart support with flow control.
|
||||
* When uart transmission is performed using different settings.
|
||||
* Then data is successfully transfered.
|
||||
*
|
||||
*/
|
||||
void fpga_uart_test_common(PinName tx, PinName rx, PinName cts, PinName rts);
|
||||
|
||||
/** Test that the uart transfer can be performed in various configurations (flow control disabled).
|
||||
*
|
||||
* Given board provides uart support without flow control.
|
||||
* When uart transmission is performed using different settings.
|
||||
* Then data is successfully transfered.
|
||||
*
|
||||
*/
|
||||
void fpga_uart_test_common_no_fc(PinName tx, PinName rx);
|
||||
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
Loading…
Reference in New Issue