From 7aea44f0cf0122f7c0f5e4226e357a05702d05fc Mon Sep 17 00:00:00 2001 From: Przemyslaw Stekiel Date: Thu, 11 Jul 2019 10:39:10 +0200 Subject: [PATCH] Add header files to fpga tests, update test names --- .../analogin/analogin_fpga_test.h | 60 +++++++++++++ .../analogin/main.cpp | 10 +-- .../gpio/gpio_fpga_test.h | 61 +++++++++++++ .../gpio/main.cpp | 12 +-- .../gpio_irq/gpio_irq_fpga_test.h | 58 ++++++++++++ .../gpio_irq/main.cpp | 11 ++- .../i2c/i2c_fpga_test.h | 86 ++++++++++++++++++ .../mbed_hal_fpga_ci_test_shield/i2c/main.cpp | 24 +++-- .../mbed_hal_fpga_ci_test_shield/pwm/main.cpp | 88 +++++++++---------- .../pwm/pwm_fpga_test.h | 61 +++++++++++++ .../mbed_hal_fpga_ci_test_shield/spi/main.cpp | 33 +++---- .../spi/spi_fpga_test.h | 59 +++++++++++++ .../uart/main.cpp | 45 +++++----- .../uart/uart_fpga_test.h | 82 +++++++++++++++++ 14 files changed, 579 insertions(+), 111 deletions(-) create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/analogin/analogin_fpga_test.h create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/gpio/gpio_fpga_test.h create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/gpio_irq_fpga_test.h create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/i2c/i2c_fpga_test.h create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/pwm/pwm_fpga_test.h create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/spi/spi_fpga_test.h create mode 100644 TESTS/mbed_hal_fpga_ci_test_shield/uart/uart_fpga_test.h diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/analogin_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/analogin_fpga_test.h new file mode 100644 index 0000000000..6150e32cf2 --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/analogin_fpga_test.h @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_analogin_tests */ +/** @{*/ + +#ifndef MBED_FPGA_ANALOG_IN_TEST_H +#define MBED_FPGA_ANALOG_IN_TEST_H + +#if DEVICE_ANALOGIN + +#ifdef __cplusplus +extern "C" { +#endif + +/** Test that the alalogin can be initialized using all possible analogin pins. + * + * Given board provides analogin support. + * When analogin is initialized using valid analogin pin. + * Then the operation is successfull. + * + */ +void fpga_analogin_init_test(PinName pin); + +/** Test that analogin correctly interprets given input voltage. + * + * Given board provides analogin support. + * When 0.0/3.3 V is provided to analogin pin. + * Then analogin_read returns 0.0/1.0, + * analogin_read_u16 returns 0/65535. + * + */ +void fpga_analogin_test(PinName pin); + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/**@}*/ diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp index 981ffff4d0..18e85665ba 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp @@ -26,11 +26,11 @@ #include "utest/utest.h" #include "unity/unity.h" #include "greentea-client/test_env.h" - #include "mbed.h" #include "pinmap.h" #include "test_utils.h" #include "MbedTester.h" +#include "analogin_fpga_test.h" using namespace utest::v1; @@ -44,14 +44,14 @@ const PinList *restricted = pinmap_restricted_pins(); MbedTester tester(form_factor, restricted); -void analogin_init(PinName pin) +void fpga_analogin_init_test(PinName pin) { analogin_t analogin; analogin_init(&analogin, pin); } -void analogin_test(PinName pin) +void fpga_analogin_test(PinName pin) { tester.reset(); tester.pin_map_set(pin, MbedTester::LogicalPinGPIO0); @@ -76,9 +76,9 @@ void analogin_test(PinName pin) Case cases[] = { // This will be run for all pins - Case("AnalogIn - init test", all_ports), + Case("AnalogIn - init test", all_ports), // This will be run for single pin - Case("AnalogIn - read test", all_ports), + Case("AnalogIn - read test", all_ports), }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/gpio/gpio_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/gpio/gpio_fpga_test.h new file mode 100644 index 0000000000..efca1fcf0e --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/gpio/gpio_fpga_test.h @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_gpio_tests */ +/** @{*/ + +#ifndef MBED_FPGA_GPIO_TEST_H +#define MBED_FPGA_GPIO_TEST_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Test basic input & output operations. + * + * Given a GPIO instance initialized with a generic gpio_init() function, + * when basic input and output operations are performed, + * then all operations succeed. + */ +void fpga_test_basic_input_output(PinName pin); + +/* Test explicit input initialization. + * + * Given a GPIO instance, + * when additional parameters are passed to the input init function, + * then the GPIO is correctly initialized as an input. + */ +void fpga_test_explicit_input(PinName pin); + +/* Test explicit output initialization. + * + * Given a GPIO instance, + * when additional parameters are passed to the output init function, + * then the GPIO is correctly initialized as an output. + */ +void fpga_test_explicit_output(PinName pin); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + + +/**@}*/ diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp index d42f5a16ff..7d4c3fd65a 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp @@ -25,12 +25,12 @@ #include "unity/unity.h" #include "greentea-client/test_env.h" #include "mbed.h" - -using namespace utest::v1; - #include "MbedTester.h" #include "pinmap.h" #include "test_utils.h" +#include "gpio_fpga_test.h" + +using namespace utest::v1; // This delay is used when reading a floating input that has an internal pull-up // or pull-down resistor. The voltage response is much slower when the input @@ -45,7 +45,7 @@ MbedTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins( * when basic input and output operations are performed, * then all operations succeed. */ -void test_basic_input_output(PinName pin) +void fpga_test_basic_input_output(PinName pin) { // Reset everything and set all tester pins to hi-Z. tester.reset(); @@ -128,7 +128,7 @@ void test_basic_input_output(PinName pin) * when additional parameters are passed to the input init function, * then the GPIO is correctly initialized as an input. */ -void test_explicit_input(PinName pin) +void fpga_test_explicit_input(PinName pin) { // Reset everything and set all tester pins to hi-Z. tester.reset(); @@ -180,7 +180,7 @@ void test_explicit_input(PinName pin) * when additional parameters are passed to the output init function, * then the GPIO is correctly initialized as an output. */ -void test_explicit_output(PinName pin) +void fpga_test_explicit_output(PinName pin) { // Reset everything and set all tester pins to hi-Z. tester.reset(); diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/gpio_irq_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/gpio_irq_fpga_test.h new file mode 100644 index 0000000000..793022a6e2 --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/gpio_irq_fpga_test.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_gpioirq_tests */ +/** @{*/ + +#ifndef MBED_FPGA_GPIO_IRQ_TEST_H +#define MBED_FPGA_GPIO_IRQ_TEST_H + +#if DEVICE_INTERRUPTIN + +#ifdef __cplusplus +extern "C" { +#endif + +/** Test that the GPIO IRQ can be initialized/de-initialized using all possible + * GPIO IRQ pins. + * + * Given board provides GPIO IRQ support. + * When GPIO IRQ is initialized (and then de-initialized) using valid GPIO IRQ pin. + * Then the operation is successfull. + * + */ +void fpga_gpio_irq_test(PinName pin); + +/** Test that the gpio interrupt is generated correctly. + * + * Given board provides interrupt-in feature. + * When gpio interrupt is configured to fire on rasing/falling/both edge(s). + * Then on rasing/falling/any edge registered interrupt handler is called. + * + */ +void fpga_gpio_irq_init_free_test(PinName pin); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif +/**@}*/ diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp index c1b2464fc9..98b4935e9b 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp @@ -27,6 +27,9 @@ #include "unity/unity.h" #include "greentea-client/test_env.h" #include "mbed.h" +#include "MbedTester.h" +#include "pinmap.h" +#include "gpio_irq_fpga_test.h" using namespace utest::v1; @@ -44,7 +47,7 @@ void test_gpio_irq_handler(uint32_t id, gpio_irq_event event) #define WAIT() wait_us(10) -void gpio_irq_test(PinName pin) +void fpga_gpio_irq_test(PinName pin) { // Reset everything and set all tester pins to hi-Z. tester.reset(); @@ -250,7 +253,7 @@ void gpio_irq_test(PinName pin) gpio_irq_free(&gpio_irq); } -void init_free_test(PinName pin) +void fpga_gpio_irq_init_free_test(PinName pin) { gpio_t gpio; gpio_irq_t gpio_irq; @@ -260,8 +263,8 @@ void init_free_test(PinName pin) } Case cases[] = { - Case("init/free", all_ports), - Case("rising & falling edge", all_ports), + Case("init/free", all_ports), + Case("rising & falling edge", all_ports), }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/i2c/i2c_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/i2c/i2c_fpga_test.h new file mode 100644 index 0000000000..9734eb49a7 --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/i2c/i2c_fpga_test.h @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_GeneralI2C_tests */ +/** @{*/ + +#ifndef MBED_FPGA_I2C_TEST_H +#define MBED_FPGA_I2C_TEST_H + +#if DEVICE_I2C + +#ifdef __cplusplus +extern "C" { +#endif + +/** Test that the i2c-master can be initialized/de-initialized using all possible + * i2c pins. + * + * Given board provides i2c-master support. + * When i2c-master is initialized (and then de-initialized) using valid set of i2c pins. + * Then the operation is successfull. + * + */ +void fpga_test_i2c_init_free(PinName sda, PinName scl); + +/** Test that I2C master is able to read data from I2C bus using i2c_byte_read. + * + * Given board provides I2C master support. + * When I2C master reads data from I2C bus using i2c_byte_read. + * Then data is successfully read. + * + */ +void fpga_i2c_test_byte_read(PinName sda, PinName scl); + +/** Test that I2C master is able to write data to I2C bus using i2c_byte_write. + * + * Given board provides I2C master support. + * When I2C master writes data to the I2C bus using i2c_byte_write. + * Then data is successfully transmitted. + * + */ +void fpga_i2c_test_byte_write(PinName sda, PinName scl); + +/** Test that I2C master is able to read data from I2C bus using i2c_read. + * + * Given board provides I2C master support. + * When I2C master reads data from I2C bus using i2c_read. + * Then data is successfully read. + * + */ +void fpga_i2c_test_read(PinName sda, PinName scl); + +/** Test that I2C master is able to write data to I2C bus using i2c_write. + * + * Given board provides I2C master support. + * When I2C master writes data to the I2C bus using i2c_write. + * Then data is successfully transmitted. + * + */ +void fpga_i2c_test_write(PinName sda, PinName scl); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/**@}*/ diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp index 7f1999ac7e..9714a68b4c 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp @@ -26,14 +26,12 @@ #include "utest/utest.h" #include "unity/unity.h" #include "greentea-client/test_env.h" -#include "mbed.h" - #include "mbed.h" #include "i2c_api.h" #include "pinmap.h" #include "test_utils.h" #include "I2CTester.h" - +#include "i2c_fpga_test.h" using namespace utest::v1; @@ -45,7 +43,7 @@ const int TRANSFER_COUNT = 300; I2CTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins()); -void test_i2c_init_free(PinName sda, PinName scl) +void fpga_test_i2c_init_free(PinName sda, PinName scl) { i2c_t obj = {}; memset(&obj, 0, sizeof(obj)); @@ -66,7 +64,7 @@ void test_i2c_init_free(PinName sda, PinName scl) gpio_set(scl); } -void i2c_test_write(PinName sda, PinName scl) +void fpga_i2c_test_write(PinName sda, PinName scl) { // Remap pins for test tester.reset(); @@ -153,7 +151,7 @@ void i2c_test_write(PinName sda, PinName scl) tester.pin_set_pull(scl, MbedTester::PullNone); } -void i2c_test_read(PinName sda, PinName scl) +void fpga_i2c_test_read(PinName sda, PinName scl) { // Remap pins for test tester.reset(); @@ -239,7 +237,7 @@ void i2c_test_read(PinName sda, PinName scl) tester.pin_set_pull(scl, MbedTester::PullNone); } -void i2c_test_byte_write(PinName sda, PinName scl) +void fpga_i2c_test_byte_write(PinName sda, PinName scl) { // Remap pins for test tester.reset(); @@ -336,7 +334,7 @@ void i2c_test_byte_write(PinName sda, PinName scl) tester.pin_set_pull(scl, MbedTester::PullNone); } -void i2c_test_byte_read(PinName sda, PinName scl) +void fpga_i2c_test_byte_read(PinName sda, PinName scl) { // Remap pins for test tester.reset(); @@ -437,11 +435,11 @@ void i2c_test_byte_read(PinName sda, PinName scl) } Case cases[] = { - Case("i2c - init/free test all pins", one_peripheral), - Case("i2c - test write i2c API", one_peripheral), - Case("i2c - test read i2c API", one_peripheral), - Case("i2c - test single byte write i2c API", one_peripheral), - Case("i2c - test single byte read i2c API", one_peripheral) + Case("i2c - init/free test all pins", one_peripheral), + Case("i2c - test write i2c API", one_peripheral), + Case("i2c - test read i2c API", one_peripheral), + Case("i2c - test single byte write i2c API", one_peripheral), + Case("i2c - test single byte read i2c API", one_peripheral) }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp index 2ec859cc3b..dd26813ace 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp @@ -27,12 +27,12 @@ #include "unity/unity.h" #include "greentea-client/test_env.h" #include "mbed.h" - -using namespace utest::v1; - #include "MbedTester.h" #include "pinmap.h" #include "test_utils.h" +#include "pwm_fpga_test.h" + +using namespace utest::v1; #define pwm_debug_printf(...) @@ -63,7 +63,7 @@ typedef enum { MbedTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins()); -void pwm_init_free(PinName pin) +void fpga_pwm_init_free(PinName pin) { pwmout_t pwm_out; @@ -74,7 +74,7 @@ void pwm_init_free(PinName pin) } -void pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pwm_api_test_t api_test) +void fpga_pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pwm_api_test_t api_test) { pwm_debug_printf("PWM test on pin = %s (%i)\r\n", pinmap_ff_default_pin_to_string(pin), pin); pwm_debug_printf("Testing period = %lu ms, duty-cycle = %lu %%\r\n", period_ms, fill_prc); @@ -157,59 +157,59 @@ void pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pw } template -void pwm_period_fill_test(PinName pin) +void fpga_pwm_period_fill_test(PinName pin) { - pwm_period_fill_test(pin, period_ms, fill_prc, api_test); + fpga_pwm_period_fill_test(pin, period_ms, fill_prc, api_test); } Case cases[] = { // This will be run for all pins - Case("PWM - init/free test", all_ports), + Case("PWM - init/free test", all_ports), // This will be run for single pin - Case("PWM - period: 10 ms, fill: 10%, api: period/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 10%, api: period/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 10%, api: period_ms/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 10%, api: period_us/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width", one_peripheral >), - Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral >), - Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_us", one_peripheral >), + Case("PWM - period: 10 ms, fill: 10%, api: period_ms/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 10%, api: period_us/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width", one_peripheral >), + Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral >), + Case("PWM - period: 10 ms, fill: 10%, api: period/pulse_width_us", one_peripheral >), - Case("PWM - period: 10 ms, fill: 50%, api: period/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 50%, api: period_ms/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 50%, api: period_us/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width", one_peripheral >), - Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral >), - Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_us", one_peripheral >), + Case("PWM - period: 10 ms, fill: 50%, api: period/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 50%, api: period_ms/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 50%, api: period_us/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width", one_peripheral >), + Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral >), + Case("PWM - period: 10 ms, fill: 50%, api: period/pulse_width_us", one_peripheral >), - Case("PWM - period: 10 ms, fill: 90%, api: period/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 90%, api: period_ms/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 90%, api: period_us/write", one_peripheral >), - Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width", one_peripheral >), - Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral >), - Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_us", one_peripheral >), + Case("PWM - period: 10 ms, fill: 90%, api: period/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 90%, api: period_ms/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 90%, api: period_us/write", one_peripheral >), + Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width", one_peripheral >), + Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral >), + Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_us", one_peripheral >), - Case("PWM - period: 50 ms, fill: 10%, api: period/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 10%, api: period_ms/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 10%, api: period_us/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width", one_peripheral >), - Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral >), - Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_us", one_peripheral >), + Case("PWM - period: 50 ms, fill: 10%, api: period/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 10%, api: period_ms/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 10%, api: period_us/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width", one_peripheral >), + Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral >), + Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_us", one_peripheral >), - Case("PWM - period: 50 ms, fill: 50%, api: period/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 50%, api: period_ms/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 50%, api: period_us/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width", one_peripheral >), - Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral >), - Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_us", one_peripheral >), + Case("PWM - period: 50 ms, fill: 50%, api: period/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 50%, api: period_ms/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 50%, api: period_us/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width", one_peripheral >), + Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral >), + Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_us", one_peripheral >), - Case("PWM - period: 50 ms, fill: 90%, api: period/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 90%, api: period_ms/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 90%, api: period_us/write", one_peripheral >), - Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width", one_peripheral >), - Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral >), - Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_us", one_peripheral >) + Case("PWM - period: 50 ms, fill: 90%, api: period/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 90%, api: period_ms/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 90%, api: period_us/write", one_peripheral >), + Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width", one_peripheral >), + Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral >), + Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_us", one_peripheral >) }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/pwm/pwm_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/pwm/pwm_fpga_test.h new file mode 100644 index 0000000000..26b57089b8 --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/pwm/pwm_fpga_test.h @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_pwmout_tests */ +/** @{*/ + +#ifndef MBED_FPGA_PWM_TEST_H +#define MBED_FPGA_PWM_TEST_H + +#if DEVICE_PWM + +#ifdef __cplusplus +extern "C" { +#endif + +/** Test that the PWM can be initialized/de-initialized using all possible + * PWM pins. + * + * Given board provides PWM support. + * When PWM is initialized (and then de-initialized) using valid PWM pin. + * Then the operation is successfull. + * + */ +void fpga_pwm_init_free(PinName pin); + +/** Test that pwmout_period, pwmout_period_ms, pwmout_period_us functions sets the + * PWM period correctly and pwmout_write, pwmout_pulsewidth, pwmout_pulsewidth_ms, + * pwmout_pulsewidth_us functions sets the pulse width correctly. + * + * Given board provides PWM support. + * When PWM period/width is set using pwmout_period, pwmout_period_ms, pwmout_period_us/pwmout_write, pwmout_pulsewidth, pwmout_pulsewidth_ms, pwmout_pulsewidth_us + * Then the valid PWM puswidth and period is on output. + * + */ +void fpga_pwm_period_fill_test(PinName pin); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/**@}*/ diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp index 0091b9801b..fcca981ede 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp @@ -27,12 +27,13 @@ #include "unity/unity.h" #include "greentea-client/test_env.h" #include "mbed.h" - -using namespace utest::v1; - #include "SPIMasterTester.h" #include "pinmap.h" #include "test_utils.h" +#include "spi_fpga_test.h" + +using namespace utest::v1; + typedef enum { TRANSFER_SPI_MASTER_WRITE_SYNC, @@ -61,7 +62,7 @@ void spi_async_handler() } #endif -void spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel) +void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel) { spi_init(&spi, mosi, miso, sclk, ssel); spi_format(&spi, 8, SPITester::Mode0, 0); @@ -69,7 +70,7 @@ void spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel) spi_free(&spi); } -void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency) +void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency) { uint32_t sym_mask = ((1 << sym_size) - 1); @@ -161,32 +162,32 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI } template -void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel) +void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel) { - spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, frequency); + fpga_spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, frequency); } Case cases[] = { // This will be run for all pins - Case("SPI - init/free test all pins", all_ports), + Case("SPI - init/free test all pins", all_ports), // This will be run for all peripherals - Case("SPI - basic test", all_peripherals >), + Case("SPI - basic test", all_peripherals >), // This will be run for single pin configuration - Case("SPI - mode testing (MODE_1)", one_peripheral >), - Case("SPI - mode testing (MODE_2)", one_peripheral >), - Case("SPI - mode testing (MODE_3)", one_peripheral >), + Case("SPI - mode testing (MODE_1)", one_peripheral >), + Case("SPI - mode testing (MODE_2)", one_peripheral >), + Case("SPI - mode testing (MODE_3)", one_peripheral >), Case("SPI - symbol size testing (16)", one_peripheral >), - Case("SPI - frequency testing (500 kHz)", one_peripheral >), - Case("SPI - frequency testing (2 MHz)", one_peripheral >), + Case("SPI - frequency testing (500 kHz)", one_peripheral >), + Case("SPI - frequency testing (2 MHz)", one_peripheral >), - Case("SPI - block write", one_peripheral >), + Case("SPI - block write", one_peripheral >), #if DEVICE_SPI_ASYNCH - Case("SPI - async mode", one_peripheral >) + Case("SPI - async mode", one_peripheral >) #endif }; diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/spi/spi_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/spi/spi_fpga_test.h new file mode 100644 index 0000000000..81d7d380e9 --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/spi/spi_fpga_test.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_GeneralSPI_tests */ +/** @{*/ + +#ifndef MBED_FPGA_SPI_TEST_H +#define MBED_FPGA_SPI_TEST_H + +#if DEVICE_SPI + +#ifdef __cplusplus +extern "C" { +#endif + +/** Test that the spi-Master can be initialized/de-initialized using all possible + * SPI pins. + * + * Given board provides SPI-Master support. + * When SPI-Master is initialized (and then de-initialized) using valid set of SPI pins. + * Then the operation is successfull. + * + */ +void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel); + +/** Test that the SPI-Master transfer can be performed in various configurations. + * + * Given board provides SPI-Master support. + * When SPI transmission is performed using different settings. + * Then data is successfully transfered. + * + */ +void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/**@}*/ diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp index 1ff3a37740..4b5054c209 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp @@ -26,17 +26,16 @@ #include "utest/utest.h" #include "unity/unity.h" #include "greentea-client/test_env.h" - #include "platform/mbed_critical.h" - -using namespace utest::v1; - #include #include "UARTTester.h" #include "pinmap.h" #include "test_utils.h" #include "serial_api.h" #include "us_ticker_api.h" +#include "uart_fpga_test.h" + +using namespace utest::v1; #define PUTC_REPS 16 #define GETC_REPS 16 @@ -274,7 +273,7 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i tester.reset(); } -void test_init_free(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) +void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) { bool use_flow_control = (cts != NC && rts != NC) ? true : false; serial_t serial; @@ -289,56 +288,56 @@ void test_init_free(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) serial_free(&serial); } -void test_init_free_no_fc(PinName tx, PinName rx) +void fpga_uart_init_free_test_no_fc(PinName tx, PinName rx) { - test_init_free(tx, rx); + fpga_uart_init_free_test(tx, rx); } template -void test_common(PinName tx, PinName rx, PinName cts, PinName rts) +void fpga_uart_test_common(PinName tx, PinName rx, PinName cts, PinName rts) { uart_test_common(BAUDRATE, DATA_BITS, PARITY, STOP_BITS, tx, rx, cts, rts); } template -void test_common_no_fc(PinName tx, PinName rx) +void fpga_uart_test_common_no_fc(PinName tx, PinName rx) { uart_test_common(BAUDRATE, DATA_BITS, PARITY, STOP_BITS, tx, rx); } Case cases[] = { // Every set of pins from every peripheral. - Case("init/free, FC off", all_ports), + Case("init/free, FC off", all_ports), // One set of pins from every peripheral. - Case("basic, 9600, 8N1, FC off", all_peripherals >), + Case("basic, 9600, 8N1, FC off", all_peripherals >), // One set of pins from one peripheral. // baudrate - Case("19200, 8N1, FC off", one_peripheral >), - Case("38400, 8N1, FC off", one_peripheral >), - Case("115200, 8N1, FC off", one_peripheral >), + Case("19200, 8N1, FC off", one_peripheral >), + Case("38400, 8N1, FC off", one_peripheral >), + Case("115200, 8N1, FC off", one_peripheral >), // stop bits - Case("9600, 8N2, FC off", one_peripheral >), + Case("9600, 8N2, FC off", one_peripheral >), #if DEVICE_SERIAL_FC // Every set of pins from every peripheral. - Case("init/free, FC on", all_ports), + Case("init/free, FC on", all_ports), // One set of pins from every peripheral. - Case("basic, 9600, 8N1, FC on", all_peripherals >), + Case("basic, 9600, 8N1, FC on", all_peripherals >), // One set of pins from one peripheral. // baudrate - Case("19200, 8N1, FC on", one_peripheral >), - Case("38400, 8N1, FC on", one_peripheral >), - Case("115200, 8N1, FC on", one_peripheral >), + Case("19200, 8N1, FC on", one_peripheral >), + Case("38400, 8N1, FC on", one_peripheral >), + Case("115200, 8N1, FC on", one_peripheral >), // data bits: not tested (some platforms support 8 bits only) // parity - Case("9600, 8O1, FC on", one_peripheral >), - Case("9600, 8E1, FC on", one_peripheral >), + Case("9600, 8O1, FC on", one_peripheral >), + Case("9600, 8E1, FC on", one_peripheral >), // stop bits - Case("9600, 8N2, FC on", one_peripheral >), + Case("9600, 8N2, FC on", one_peripheral >), #endif }; diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/uart/uart_fpga_test.h b/TESTS/mbed_hal_fpga_ci_test_shield/uart/uart_fpga_test.h new file mode 100644 index 0000000000..ff5618e446 --- /dev/null +++ b/TESTS/mbed_hal_fpga_ci_test_shield/uart/uart_fpga_test.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** \addtogroup hal_GeneralSerial_tests */ +/** @{*/ + +#ifndef MBED_FPGA_UART_TEST_H +#define MBED_FPGA_UART_TEST_H + +#if DEVICE_UART + +#ifdef __cplusplus +extern "C" { +#endif + +/** Test that the uart can be initialized/de-initialized using all possible + * uart pins (flow control enabled). + * + * Given board provides uart support with flow control. + * When uart is initialized (and then de-initialized) using valid set of uart pins. + * Then the operation is successfull. + * + */ +void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts, PinName rts); + +/** Test that the uart can be initialized/de-initialized using all possible + * uart pins (flow control disabled). + * + * Given board provides uart support without flow control. + * When uart is initialized (and then de-initialized) using valid set of uart pins. + * Then the operation is successfull. + * + */ +void fpga_uart_init_free_test_no_fc(PinName tx, PinName rx); +{ + fpga_uart_init_free_test(tx, rx); +} + +/** Test that the uart transfer can be performed in various configurations (flow control enabled). + * + * Given board provides uart support with flow control. + * When uart transmission is performed using different settings. + * Then data is successfully transfered. + * + */ +void fpga_uart_test_common(PinName tx, PinName rx, PinName cts, PinName rts); + +/** Test that the uart transfer can be performed in various configurations (flow control disabled). + * + * Given board provides uart support without flow control. + * When uart transmission is performed using different settings. + * Then data is successfully transfered. + * + */ +void fpga_uart_test_common_no_fc(PinName tx, PinName rx); + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/**@}*/