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Fix BOOT_HEADER_SIZE allocation in ARM scatter files (#13058) 

PSoC 64 secure BSP post-build hook (cysecuretools image signing)
expects the HEX file with start address 0x10000400 (first KB of
internal FLASH is reserved for MCUboot headers area).
In order to get the correct HEX file produced by ARM fromELF tool,
the ELF file should allocate LR_IROM1 starting from address
0x10000400, not 0x10000000. Otherwise the generated HEX file
allocates rows at addresses 0x10000000 ~ 010000400 and the
final application image is not signed correctly.

Fixes https://github.com/ARMmbed/mbed-os/issues/13058.
pull/13100/head
Volodymyr Medvid 2020-06-10 10:25:27 +03:00
parent 998d06a80b
commit dc937ab53b
5 changed files with 10 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
View File

@ -148,14 +148,9 @@
; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
View File

@ -148,14 +148,9 @@
; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct
View File

@ -134,9 +134,9 @@
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
View File

@ -148,14 +148,9 @@
; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct
View File

@ -134,9 +134,9 @@
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{
ER_FLASH_VECTORS +BOOT_HEADER_SIZE
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}