From dc937ab53b52115935bc22af47182136cd2e030f Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Wed, 10 Jun 2020 10:25:27 +0300 Subject: [PATCH] Fix BOOT_HEADER_SIZE allocation in ARM scatter files (#13058) PSoC 64 secure BSP post-build hook (cysecuretools image signing) expects the HEX file with start address 0x10000400 (first KB of internal FLASH is reserved for MCUboot headers area). In order to get the correct HEX file produced by ARM fromELF tool, the ELF file should allocate LR_IROM1 starting from address 0x10000400, not 0x10000000. Otherwise the generated HEX file allocates rows at addresses 0x10000000 ~ 010000400 and the final application image is not signed correctly. Fixes https://github.com/ARMmbed/mbed-os/issues/13058. --- .../COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct | 9 ++------- .../COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct | 9 ++------- .../device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct | 4 ++-- .../COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct | 9 ++------- .../device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct | 4 ++-- 5 files changed, 10 insertions(+), 25 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index 7fbcad279d..4e700abeaf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -148,14 +148,9 @@ ; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) { - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +BOOT_HEADER_SIZE + ER_FLASH_VECTORS +0 { * (RESET, +FIRST) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 1b90b6b4b5..548323c5b7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -148,14 +148,9 @@ ; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) { - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +BOOT_HEADER_SIZE + ER_FLASH_VECTORS +0 { * (RESET, +FIRST) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index 37b32f07bf..3e8e0478d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -134,9 +134,9 @@ ; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) { - ER_FLASH_VECTORS +BOOT_HEADER_SIZE + ER_FLASH_VECTORS +0 { * (RESET, +FIRST) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index b16001ceba..b451f65c85 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -148,14 +148,9 @@ ; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) { - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +BOOT_HEADER_SIZE + ER_FLASH_VECTORS +0 { * (RESET, +FIRST) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 0a03d5c5b6..140beae5bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -134,9 +134,9 @@ ; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) { - ER_FLASH_VECTORS +BOOT_HEADER_SIZE + ER_FLASH_VECTORS +0 { * (RESET, +FIRST) }