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code style fix 

replace tab with 4 spaces;
remove "#ifndef CONFIG_MBED_ENABLED" code;
make if else pretty;
add comment to PinNames.h;
pull/4438/head
Yuguo Zou 2017-04-07 19:29:38 +08:00 committed by Martin Kojtal
parent 0650ad1384
commit d18735dd31
16 changed files with 163 additions and 1242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h
View File

@ -109,6 +109,7 @@ typedef enum {
PF_3 = (PORT_F<<4|3),
PF_4 = (PORT_F<<4|4),
PF_5 = (PORT_F<<4|5),
/* unavailable pins */
// PF_6 = (PORT_F<<4|6),
// PF_7 = (PORT_F<<4|7),
@ -146,6 +147,7 @@ typedef enum {
PJ_4 = (PORT_J<<4|4),
PJ_5 = (PORT_J<<4|5),
PJ_6 = (PORT_J<<4|6),
/* unavailable pins */
// PJ_7 = (PORT_J<<4|7),
PK_0 = (PORT_K<<4|0),
@ -155,6 +157,7 @@ typedef enum {
PK_4 = (PORT_K<<4|4),
PK_5 = (PORT_K<<4|5),
PK_6 = (PORT_K<<4|6),
/* unavailable pins */
// PK_7 = (PORT_K<<4|7),
AD_1 = (PORT_V<<4|1),
@ -193,15 +196,15 @@ typedef enum {
// Generic signals namings
/* LED1~4 are defined as alias of GPIO pins, they are not the LEDs on board*/
LED1 = PB_4,
LED2 = PB_5,
LED3 = PB_6,
LED4 = PB_7,
SERIAL_TX = PA_7,
SERIAL_RX = PA_6,
USBTX = PB_0, //PA_7
USBRX = PB_1, //PA_6
USBTX = PB_0,
USBRX = PB_1,
I2C_SCL = PC_5,
I2C_SDA = PC_4,
SPI_MOSI = PC_2,

41
targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c
View File

@ -76,8 +76,7 @@ void flash_init(flash_t *obj)
DBG_8195A("SPI Init Fail!!!!!!\n");
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3)|0xf);
}
else {
} else {
isinit = 1;
}
flashobj.SpicInitPara.flashtype = SpicInitParaAllClk[0][0].flashtype;
@ -168,8 +167,7 @@ int flash_write_word(flash_t *obj, uint32_t address, uint32_t data)
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
SpicDisableRtl8195A();
@ -232,8 +230,7 @@ int flash_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t * d
address += 4;
len -= 4;
}
}
else {
} else {
while (len >= 4) {
*((u32 *)pbuf) = HAL_READ32(SPI_FLASH_BASE, address);
pbuf += 4;
@ -301,8 +298,7 @@ int flash_stream_write(flash_t *obj, uint32_t address, uint32_t len, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
@ -320,16 +316,14 @@ int flash_stream_write(flash_t *obj, uint32_t address, uint32_t len, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
pbuf += 4;
address += 4;
len -= 4;
}
}
else {
} else {
while (len >= 4) {
//Write word
HAL_WRITE32(SPI_FLASH_BASE, address, (u32)*((u32 *)pbuf));
@ -338,8 +332,7 @@ int flash_stream_write(flash_t *obj, uint32_t address, uint32_t len, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
pbuf += 4;
@ -362,8 +355,7 @@ int flash_stream_write(flash_t *obj, uint32_t address, uint32_t len, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
@ -406,10 +398,11 @@ int flash_burst_write(flash_t *obj, uint32_t address ,uint32_t Length, uint8_t *
flashtype = flashobj.SpicInitPara.flashtype;
OccuSize = address & 0xFF;
if((Length >= PageSize) ||((Length + OccuSize) >= PageSize))
if((Length >= PageSize) ||((Length + OccuSize) >= PageSize)){
ProgramSize = PageSize - OccuSize;
else
} else {
ProgramSize = Length;
}
flashobj.Length = Length;
while(Length > 0){
@ -420,16 +413,14 @@ int flash_burst_write(flash_t *obj, uint32_t address ,uint32_t Length, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
address += ProgramSize;
data+= ProgramSize;
Length -= ProgramSize;
OccuSize = 0;
}
else{
} else{
while((flashobj.Length) >= PageSize){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
@ -437,8 +428,7 @@ int flash_burst_write(flash_t *obj, uint32_t address ,uint32_t Length, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
address += PageSize;
@ -453,8 +443,7 @@ int flash_burst_write(flash_t *obj, uint32_t address ,uint32_t Length, uint8_t *
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
}
else
} else
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
break;

73
targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c
View File

@ -55,16 +55,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
obj->hal_pin.pin_mode = INT_FALLING;
break;
#ifndef CONFIG_MBED_ENABLED
case IRQ_LOW:
obj->hal_pin.pin_mode = INT_LOW;
break;
case IRQ_HIGH:
obj->hal_pin.pin_mode = INT_HIGH;
break;
#endif
case IRQ_NONE:
break;
@ -76,8 +66,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
HAL_GPIO_IntCtrl(&obj->hal_pin, enable);
if(enable){
HAL_GPIO_UnMaskIrq(&obj->hal_pin);
}
else{
} else{
HAL_GPIO_MaskIrq(&obj->hal_pin);
}
}
@ -91,63 +80,5 @@ void gpio_irq_disable(gpio_irq_t *obj)
{
HAL_GPIO_MaskIrq(&obj->hal_pin);
}
#ifndef CONFIG_MBED_ENABLED
void gpio_irq_deinit(gpio_irq_t *obj)
{
HAL_GPIO_DeInit(&obj->hal_pin);
}
void gpio_irq_pull_ctrl(gpio_irq_t *obj, PinMode pull_type)
{
HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type);
}
void gpio_irq_set_event(gpio_irq_t *obj, gpio_irq_event event)
{
uint32_t reg_value;
uint32_t level_edge;
uint32_t polarity;
uint8_t pin_num;
pin_num = obj->hal_pin_num & 0x1f; // Max 31
switch (event) {
case IRQ_LOW:
level_edge = 0; // level trigger
polarity = 0; // active low
break;
case IRQ_HIGH:
level_edge = 0; // level trigger
polarity = 1; // active high
break;
case IRQ_FALL:
level_edge = 1; // edge trigger
polarity = 0; // active low
break;
case IRQ_RISE:
level_edge = 1; // edge trigger
polarity = 1; // active high
break;
default:
DBG_GPIO_ERR("Unknow Interrupt Trigger Type(%d)\n", event);
return;
}
// Config Level or Edge trigger
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_INT_TYPE);
reg_value &= ~(1 << pin_num);
reg_value |= (level_edge << pin_num);
HAL_WRITE32(GPIO_REG_BASE, GPIO_INT_TYPE, reg_value);
// Config Low active or Gigh active
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_INT_POLARITY);
reg_value &= ~(1 << pin_num);
reg_value |= (polarity << pin_num);
HAL_WRITE32(GPIO_REG_BASE, GPIO_INT_POLARITY, reg_value);
}
#endif
#endif

220
targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c
View File

@ -203,14 +203,11 @@ void i2c_frequency(i2c_t *obj, int hz) {
i2c_reset(obj);
if (i2c_user_clk <= 100) {
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
}
else if ((i2c_user_clk > 100) && (i2c_user_clk <= 400)) {
} else if ((i2c_user_clk > 100) && (i2c_user_clk <= 400)) {
pSalI2CHND->I2CSpdMod = I2C_FS_MODE;
}
else if (i2c_user_clk > 400) {
} else if (i2c_user_clk > 400) {
pSalI2CHND->I2CSpdMod = I2C_HS_MODE;
}
else {
} else {
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
}
@ -270,8 +267,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
if (RtkI2CReceive(pSalI2CHND) != HAL_OK) {
length = length - pSalI2CHND->pRXBuf->DataLen;
return ((int)length);
}
else {
} else {
//DBG_8195A(">\n");
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
@ -290,8 +286,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
return ((int)(length));
}
}
else {
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
@ -300,12 +295,13 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pRXBuf->DataLen));
else
} else {
return ((int)(length));
}
}
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
@ -340,8 +336,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
length = length - pSalI2CHND->pTXBuf->DataLen;
return ((int)length);
}
else {
} else {
//DBG_8195A("(\n");
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
@ -359,8 +354,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO;
return ((int)(length));
}
}
else {
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO;
@ -369,12 +363,13 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pTXBuf->DataLen));
else
} else {
return ((int)(length));
}
}
}
int i2c_byte_read(i2c_t *obj, int last) {
uint8_t i2cdatlocal;
@ -431,129 +426,7 @@ void i2c_reset(i2c_t *obj) {
/* Deinit I2C directly */
RtkI2CDeInitForPS(pSalI2CHND);
}
#ifndef CONFIG_MBED_ENABLED
void i2c_restart_enable(i2c_t *obj) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
uint32_t i2clocaltmp;
uint8_t i2cen;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
i2cen = pSalI2CHND->pInitDat->I2CEn;
if (i2cen == I2C_ENABLE) {
pSalI2CHND->pInitDat->I2CEn = I2C_DISABLE;
pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat);
}
i2clocaltmp = HalI2CRead32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON);
i2clocaltmp |= BIT_IC_CON_IC_RESTART_EN;
HalI2CWrite32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON, i2clocaltmp);
if (i2cen == I2C_ENABLE) {
pSalI2CHND->pInitDat->I2CEn = I2C_ENABLE;
pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat);
}
pSalI2CHND->pInitDat->I2CReSTR = I2C_ENABLE;
}
void i2c_restart_disable(i2c_t *obj) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
uint32_t i2clocaltmp;
uint8_t i2cen;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
i2cen = pSalI2CHND->pInitDat->I2CEn;
if (i2cen == I2C_ENABLE) {
pSalI2CHND->pInitDat->I2CEn = I2C_DISABLE;
pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat);
}
i2clocaltmp = HalI2CRead32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON);
i2clocaltmp &= (~BIT_IC_CON_IC_RESTART_EN);
HalI2CWrite32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON, i2clocaltmp);
if (i2cen == I2C_ENABLE) {
pSalI2CHND->pInitDat->I2CEn = I2C_ENABLE;
pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat);
}
pSalI2CHND->pInitDat->I2CReSTR = I2C_DISABLE;
}
void i2c_set_user_callback(i2c_t *obj, I2CCallback i2ccb, void(*i2c_callback)(void *)) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
if ((i2ccb >= I2C_TX_COMPLETE) && (i2ccb <= I2C_ERR_OCCURRED)) {
switch (i2ccb) {
case I2C_TX_COMPLETE:
pSalI2CHND->pUserCB->pTXCCB->USERCB = i2c_callback;
break;
case I2C_RX_COMPLETE:
pSalI2CHND->pUserCB->pRXCCB->USERCB = i2c_callback;
break;
case I2C_RD_REQ_COMMAND:
pSalI2CHND->pUserCB->pRDREQCB->USERCB = i2c_callback;
break;
case I2C_ERR_OCCURRED:
pSalI2CHND->pUserCB->pERRCB->USERCB = i2c_callback;
break;
default:
break;
}
}
}
void i2c_clear_user_callback(i2c_t *obj, I2CCallback i2ccb) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
if ((i2ccb >= I2C_TX_COMPLETE) && (i2ccb <= I2C_ERR_OCCURRED)) {
switch (i2ccb) {
case I2C_TX_COMPLETE:
pSalI2CHND->pUserCB->pTXCCB = NULL;
break;
case I2C_RX_COMPLETE:
pSalI2CHND->pUserCB->pRXCCB = NULL;
break;
case I2C_ERR_OCCURRED:
pSalI2CHND->pUserCB->pERRCB = NULL;
break;
default:
break;
}
}
}
int i2c_enable_control(i2c_t *obj, int enable) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pSalI2CHND->pInitDat->I2CEn = enable;
if(pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat) != HAL_OK)
return 0; // error
else
return 1;
}
#endif
#if DEVICE_I2CSLAVE
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
@ -630,8 +503,7 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
if (RtkI2CReceive(pSalI2CHND) != HAL_OK) {
return 0; //error
}
else {
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
@ -648,8 +520,7 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
}
else {
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
@ -658,12 +529,13 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pTXBuf->DataLen));
else
} else {
return ((int)(length));
}
}
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
@ -693,62 +565,6 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
* read command is sent to it.
* \return result
*/
#ifndef CONFIG_MBED_ENABLED
int i2c_slave_set_for_rd_req(i2c_t *obj, int set) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL;
PHAL_I2C_OP pHalI2COP = NULL;
u32 I2CLocalTemp;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat;
pHalI2COP = pSalI2CMngtAdpt->pHalOp;
I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK);
if (set) {
I2CLocalTemp |= BIT_IC_INTR_MASK_M_RD_REQ;
} else {
I2CLocalTemp &= (~BIT_IC_INTR_MASK_M_RD_REQ);
}
pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp;
pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat);
return 1;
}
/** \brief Description of i2c_slave_set_for_data_nak
*
* i2c_slave_set_for_data_nak is used to set/clear i2c slave NAK or ACK data part in transfer.
*
* \param i2c_t *obj : i2c object
* \param int set : set or clear for data NAK.
* \return result
*/
int i2c_slave_set_for_data_nak(i2c_t *obj, int set_nak) {
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL;
PHAL_I2C_OP pHalI2COP = NULL;
u32 I2CLocalTemp;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat;
pHalI2COP = pSalI2CMngtAdpt->pHalOp;
I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS);
while (BIT_IC_STATUS_SLV_ACTIVITY & I2CLocalTemp) {
I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS);
}
HAL_I2C_WRITE32(pSalI2CHND->DevNum, REG_DW_I2C_IC_SLV_DATA_NACK_ONLY, set_nak);
return 1;
}
#endif
#endif // CONFIG_I2C_SLAVE_EN
#endif // CONFIG_I2C_EN

3
targets/TARGET_Realtek/TARGET_AMEBA/pwmout_api.c
View File

@ -88,8 +88,7 @@ void pwmout_write(pwmout_t* obj, float value)
{
if (value < (float)0.0) {
value = 0.0;
}
else if (value > (float)1.0) {
} else if (value > (float)1.0) {
value = 1.0;
}

822
targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c
View File

@ -17,10 +17,6 @@
#include "objects.h"
#include "spi_api.h"
#ifndef CONFIG_MBED_ENABLED
#include "spi_ex_api.h"
#endif
#include "PinNames.h"
#include "pinmap.h"
#include "hal_ssi.h"
@ -125,25 +121,6 @@ void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName sse
DBG_SSI_ERR(ANSI_COLOR_RED"spi_init(): SPI %x init fails.\n"ANSI_COLOR_RESET,pHalSsiAdaptor->Index);
return;
}
#ifndef CONFIG_MBED_ENABLED
pHalSsiAdaptor->TxCompCallback = spi_tx_done_callback;
pHalSsiAdaptor->TxCompCbPara = (void*)obj;
pHalSsiAdaptor->RxCompCallback = spi_rx_done_callback;
pHalSsiAdaptor->RxCompCbPara = (void*)obj;
pHalSsiAdaptor->TxIdleCallback = spi_bus_tx_done_callback;
pHalSsiAdaptor->TxIdleCbPara = (void*)obj;
#ifdef CONFIG_GDMA_EN
HalGdmaOpInit((VOID*)&SpiGdmaOp);
pHalSsiAdaptor->DmaConfig.pHalGdmaOp = &SpiGdmaOp;
pHalSsiAdaptor->DmaConfig.pRxHalGdmaAdapter = &obj->spi_gdma_adp_rx;
pHalSsiAdaptor->DmaConfig.pTxHalGdmaAdapter = &obj->spi_gdma_adp_tx;
obj->dma_en = 0;
pHalSsiAdaptor->HaveTxChannel = 0;
pHalSsiAdaptor->HaveRxChannel = 0;
#endif
#endif
osDelay(1);
}
@ -154,18 +131,6 @@ void spi_free (spi_t *obj)
HalSsiDeInit(pHalSsiAdaptor);
SPI0_MULTI_CS_CTRL(OFF);
#ifndef CONFIG_MBED_ENABLED
#ifdef CONFIG_GDMA_EN
if (obj->dma_en & SPI_DMA_RX_EN) {
HalSsiRxGdmaDeInit(pHalSsiAdaptor);
}
if (obj->dma_en & SPI_DMA_TX_EN) {
HalSsiTxGdmaDeInit(pHalSsiAdaptor);
}
obj->dma_en = 0;
#endif
#endif
}
void spi_format (spi_t *obj, int bits, int mode, int slave)
@ -221,13 +186,11 @@ void spi_format (spi_t *obj, int bits, int mode, int slave)
pHalSsiAdaptor->Role = SSI_SLAVE;
pHalSsiAdaptor->SlaveOutputEnable = SLV_TXD_ENABLE; // <-- Slave only
DBG_SSI_INFO("SPI0 is as slave\n");
}
else {
} else {
DBG_SSI_ERR("The SPI%d cannot work as Slave mode, only SPI0 does.\r\n", pHalSsiAdaptor->Index);
pHalSsiAdaptor->Role = SSI_MASTER;
}
}
else {
} else {
pHalSsiAdaptor->Role = SSI_MASTER;
}
pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role);
@ -236,8 +199,7 @@ void spi_format (spi_t *obj, int bits, int mode, int slave)
if (pHalSsiAdaptor->Role == SSI_SLAVE) {
if (pHalSsiAdaptor->SclkPolarity == SCPOL_INACTIVE_IS_LOW) {
HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullDown);
}
else {
} else {
HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullUp);
}
}
@ -253,117 +215,6 @@ void spi_frequency (spi_t *obj, int hz)
HalSsiSetSclk(pHalSsiAdaptor, (u32)hz);
}
#ifndef CONFIG_MBED_ENABLED
void spi_slave_select(spi_t *obj, ChipSelect slaveindex)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
u8 Index;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
Index = pHalSsiAdaptor->Index;
if((pHalSsiAdaptor->Role == SSI_MASTER) && (Index == 0)){
pHalSsiOp->HalSsiSetSlaveEnableRegister((VOID*)pHalSsiAdaptor,slaveindex);
if(slaveindex != CS_0){
SPI0_MULTI_CS_CTRL(ON);
}
}
else{
DBG_SSI_ERR("Only SPI 0 master mode supports slave selection.\n");
}
}
void spi_slave_select_bypin(spi_t *obj, PinName pinname)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
u8 Index;
u8 slaveindex = 8;
u8 pinmux;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
Index = pHalSsiAdaptor->Index;
pinmux = pHalSsiAdaptor->PinmuxSelect;
if((pHalSsiAdaptor->Role == SSI_MASTER) && (Index == 0)){
if(pinmux == S0){
switch (pinname){
case PE_0:
slaveindex = CS_0;
break;
case PE_4:
slaveindex = CS_1;
break;
case PE_5:
slaveindex = CS_2;
break;
case PE_6:
slaveindex = CS_3;
break;
case PE_7:
slaveindex = CS_4;
break;
case PE_8:
slaveindex = CS_5;
break;
case PE_9:
slaveindex = CS_6;
break;
case PE_A:
slaveindex = CS_7;
break;
default:
slaveindex = 8;
}
}
if(pinmux == S1){
switch (pinname){
case PC_0:
slaveindex = CS_0;
break;
case PC_4:
slaveindex = CS_1;
break;
case PC_5:
slaveindex = CS_2;
break;
case PC_6:
slaveindex = CS_3;
break;
case PC_7:
slaveindex = CS_4;
break;
case PC_8:
slaveindex = CS_5;
break;
case PC_9:
slaveindex = CS_6;
break;
default:
slaveindex = 8;
}
}
if(slaveindex != 8){
pHalSsiOp->HalSsiSetSlaveEnableRegister((VOID*)pHalSsiAdaptor,slaveindex);
if(slaveindex != CS_0){
SPI0_MULTI_CS_CTRL(ON);
}
}
else
DBG_SSI_ERR("Wrong Chip Seleect Pin.\n");
}
else{
DBG_SSI_ERR("Only SPI 0 master mode supports slave selection.\n");
}
}
#endif
static inline void ssi_write (spi_t *obj, int value)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
@ -430,671 +281,4 @@ int spi_busy (spi_t *obj)
return (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor);
}
#ifndef CONFIG_MBED_ENABLED
//Discard data in the rx fifo, SPI bus can observe these data
void spi_flush_rx_fifo (spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
u32 rx_fifo_level;
u32 i;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
while(pHalSsiOp->HalSsiReadable(pHalSsiAdaptor)){
rx_fifo_level = pHalSsiOp->HalSsiGetRxFifoLevel(pHalSsiAdaptor);
for(i=0;i<rx_fifo_level;i++) {
pHalSsiOp->HalSsiRead(pHalSsiAdaptor);
}
}
}
//This function is only for the slave device to flush tx fifo
//It will discard all data in both tx fifo and rx fifo, then reset the state of slave tx.
//Data in the tx & rx fifo will be dropped without being able to be observed from SPI bus
void spi_slave_flush_fifo(spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
u8 index;
pHalSsiAdaptor = &obj->spi_adp;
index = pHalSsiAdaptor->Index;
if(index != 0){
DBG_SSI_ERR("spi %x is not a slave\n", index);
}
HalSsiClearFIFO(pHalSsiAdaptor);
obj->state &= ~SPI_STATE_TX_BUSY;
}
// Slave mode read a sequence of data by interrupt mode
int32_t spi_slave_read_stream(spi_t *obj, char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_slave_read_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
obj->state |= SPI_STATE_RX_BUSY;
if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
return ret;
}
// Slave mode write a sequence of data by interrupt mode
int32_t spi_slave_write_stream(spi_t *obj, char *tx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_TX_BUSY) {
DBG_SSI_WARN("spi_slave_write_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
obj->state |= SPI_STATE_TX_BUSY;
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_TX_BUSY;
}
return ret;
}
// Master mode read a sequence of data by interrupt mode
// The length unit is byte, for both 16-bits and 8-bits mode
int32_t spi_master_read_stream(spi_t *obj, char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_master_read_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
// wait bus idle
while(pHalSsiOp->HalSsiBusy(pHalSsiAdaptor));
obj->state |= SPI_STATE_RX_BUSY;
if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) == HAL_OK) {
/* as Master mode, it need to push data to TX FIFO to generate clock out
then the slave can transmit data out */
// send some dummy data out
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, NULL, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
}
else {
obj->state &= ~SPI_STATE_RX_BUSY;
}
return ret;
}
// Master mode write a sequence of data by interrupt mode
// The length unit is byte, for both 16-bits and 8-bits mode
int32_t spi_master_write_stream(spi_t *obj, char *tx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_TX_BUSY) {
DBG_SSI_WARN("spi_master_write_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
obj->state |= SPI_STATE_TX_BUSY;
/* as Master mode, sending data will receive data at sametime, so we need to
drop those received dummy data */
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_TX_BUSY;
}
return ret;
}
// Master mode write a sequence of data by interrupt mode
// The length unit is byte, for both 16-bits and 8-bits mode
int32_t spi_master_write_read_stream(spi_t *obj, char *tx_buffer,
char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & (SPI_STATE_RX_BUSY|SPI_STATE_TX_BUSY)) {
DBG_SSI_WARN("spi_master_write_and_read_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
// wait bus idle
while(pHalSsiOp->HalSsiBusy(pHalSsiAdaptor));
obj->state |= SPI_STATE_RX_BUSY;
/* as Master mode, sending data will receive data at sametime */
if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) == HAL_OK) {
obj->state |= SPI_STATE_TX_BUSY;
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
obj->state &= ~(SPI_STATE_RX_BUSY|SPI_STATE_TX_BUSY);
// Disable RX IRQ
pHalSsiAdaptor->InterruptMask &= ~(BIT_IMR_RXFIM | BIT_IMR_RXOIM | BIT_IMR_RXUIM);
pHalSsiOp->HalSsiSetInterruptMask((VOID*)pHalSsiAdaptor);
}
}
else {
obj->state &= ~(SPI_STATE_RX_BUSY);
}
return ret;
}
int32_t spi_slave_read_stream_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int ret,timeout = 0;
uint32_t StartCount, TimeoutCount = 0;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_slave_read_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
obj->state |= SPI_STATE_RX_BUSY;
HalSsiEnterCritical(pHalSsiAdaptor);
if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
HalSsiExitCritical(pHalSsiAdaptor);
if ((ret == HAL_OK) && (timeout_ms > 0)) {
TimeoutCount = (timeout_ms*1000/TIMER_TICK_US);
StartCount = HalTimerOp.HalTimerReadCount(1);
while (obj->state & SPI_STATE_RX_BUSY) {
if (HAL_TIMEOUT == HalSsiTimeout(StartCount, TimeoutCount)) {
ret = HalSsiStopRecv(pHalSsiAdaptor);
obj->state &= ~ SPI_STATE_RX_BUSY;
timeout = 1;
DBG_SSI_INFO("Slave is timeout\n");
break;
}
}
if ((pHalSsiAdaptor->DataFrameSize+1) > 8){
pHalSsiAdaptor->RxLength <<= 1;
}
if(timeout)
return (length - pHalSsiAdaptor->RxLength);
else
return length;
}
else {
return (-ret);
}
}
int32_t spi_slave_read_stream_terminate(spi_t *obj, char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
volatile u8 csterminate;
int ret;
volatile u32 spistate;
csterminate = 0;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_slave_read_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
obj->state |= SPI_STATE_RX_BUSY;
HalSsiEnterCritical(pHalSsiAdaptor);
if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
HalSsiExitCritical(pHalSsiAdaptor);
while(obj->state & SPI_STATE_RX_BUSY){
spistate = pHalSsiOp->HalSsiGetStatus(pHalSsiAdaptor);
while((spistate & 0x1) == 1){
if((obj->state & SPI_STATE_RX_BUSY) == 0){
csterminate = 0;
break;
}
spistate = pHalSsiOp->HalSsiGetStatus(pHalSsiAdaptor);
if((spistate & 0x1) == 0){
ret = HalSsiStopRecv(pHalSsiAdaptor);
goto EndOfCS;
}
}
}
EndOfCS:
if((obj->state & SPI_STATE_RX_BUSY) != 0){
csterminate = 1;
obj->state &= ~ SPI_STATE_RX_BUSY;
}
if ((pHalSsiAdaptor->DataFrameSize+1) > 8){
pHalSsiAdaptor->RxLength <<= 1;
}
if(csterminate == 1)
return (length - pHalSsiAdaptor->RxLength);
else
return length;
}
// Bus Idle: Real TX done, TX FIFO empty and bus shift all data out already
void spi_bus_tx_done_callback(VOID *obj)
{
spi_t *spi_obj = (spi_t *)obj;
spi_irq_handler handler;
if (spi_obj->bus_tx_done_handler) {
handler = (spi_irq_handler)spi_obj->bus_tx_done_handler;
handler(spi_obj->bus_tx_done_irq_id, 0);
}
}
void spi_tx_done_callback(VOID *obj)
{
spi_t *spi_obj = (spi_t *)obj;
spi_irq_handler handler;
if (spi_obj->state & SPI_STATE_TX_BUSY) {
spi_obj->state &= ~SPI_STATE_TX_BUSY;
if (spi_obj->irq_handler) {
handler = (spi_irq_handler)spi_obj->irq_handler;
handler(spi_obj->irq_id, SpiTxIrq);
}
}
}
void spi_rx_done_callback(VOID *obj)
{
spi_t *spi_obj = (spi_t *)obj;
spi_irq_handler handler;
spi_obj->state &= ~SPI_STATE_RX_BUSY;
if (spi_obj->irq_handler) {
handler = (spi_irq_handler)spi_obj->irq_handler;
handler(spi_obj->irq_id, SpiRxIrq);
}
}
void spi_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id)
{
obj->irq_handler = (u32)handler;
obj->irq_id = (u32)id;
}
void spi_bus_tx_done_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id)
{
obj->bus_tx_done_handler = (u32)handler;
obj->bus_tx_done_irq_id = (u32)id;
}
void spi_enable(spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdapter;
pHalSsiAdapter = &obj->spi_adp;
HalSsiEnable((VOID*)pHalSsiAdapter);
}
void spi_disable(spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdapter;
pHalSsiAdapter = &obj->spi_adp;
HalSsiDisable((VOID*)pHalSsiAdapter);
}
#ifdef CONFIG_GDMA_EN
int32_t spi_slave_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_slave_read_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_RX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_RX_BUSY;
ret = HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length);
if (ret != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
return (ret);
}
int32_t spi_slave_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_TX_BUSY) {
DBG_SSI_WARN("spi_slave_write_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_TX_EN)==0) {
if (HAL_OK == HalSsiTxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_TX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_TX_BUSY;
ret = HalSsiDmaSend(pHalSsiAdaptor, (u8 *) tx_buffer, length);
if (ret != HAL_OK) {
obj->state &= ~SPI_STATE_TX_BUSY;
}
return (ret);
}
int32_t spi_master_write_read_stream_dma(spi_t *obj, char *tx_buffer,
char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & (SPI_STATE_RX_BUSY|SPI_STATE_TX_BUSY)) {
DBG_SSI_WARN("spi_master_write_and_read_stream: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_TX_EN)==0) {
if (HAL_OK == HalSsiTxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_TX_EN;
}
else {
return HAL_BUSY;
}
}
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_RX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_RX_BUSY;
/* as Master mode, sending data will receive data at sametime */
if ((ret=HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length)) == HAL_OK) {
obj->state |= SPI_STATE_TX_BUSY;
if ((ret=HalSsiDmaSend(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
obj->state &= ~(SPI_STATE_RX_BUSY|SPI_STATE_TX_BUSY);
}
}
else {
obj->state &= ~(SPI_STATE_RX_BUSY);
}
return ret;
}
int32_t spi_master_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_master_read_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_RX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_RX_BUSY;
ret = HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length);
if (ret != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
// for master mode, we need to send data to generate clock out
if (obj->dma_en & SPI_DMA_TX_EN) {
// TX DMA is on already, so use DMA to TX data
// Make the GDMA to use the rx_buffer too
ret = HalSsiDmaSend(pHalSsiAdaptor, (u8 *) rx_buffer, length);
if (ret != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
}
else {
// TX DMA isn't enabled, so we just use Interrupt mode to TX dummy data
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, NULL, length)) != HAL_OK) {
obj->state &= ~SPI_STATE_RX_BUSY;
}
}
return ret;
}
int32_t spi_master_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int32_t ret;
if (obj->state & SPI_STATE_TX_BUSY) {
DBG_SSI_WARN("spi_master_write_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_TX_EN)==0) {
if (HAL_OK == HalSsiTxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_TX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_TX_BUSY;
ret = HalSsiDmaSend(pHalSsiAdaptor, (u8 *) tx_buffer, length);
if (ret != HAL_OK) {
obj->state &= ~SPI_STATE_TX_BUSY;
}
return ret;
}
int32_t spi_slave_read_stream_dma_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int ret,timeout = 0;
uint32_t StartCount, TimeoutCount = 0;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_slave_read_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_RX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_RX_BUSY;
HalSsiEnterCritical(pHalSsiAdaptor);
ret = HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length);
HalSsiExitCritical(pHalSsiAdaptor);
if ((ret == HAL_OK) && (timeout_ms > 0)) {
TimeoutCount = (timeout_ms*1000/TIMER_TICK_US);
StartCount = HalTimerOp.HalTimerReadCount(1);
while (obj->state & SPI_STATE_RX_BUSY) {
if (HAL_TIMEOUT == HalSsiTimeout(StartCount, TimeoutCount)) {
ret = HalSsiStopRecv(pHalSsiAdaptor);
obj->state &= ~ SPI_STATE_RX_BUSY;
timeout = 1;
DBG_SSI_INFO("Slave is timeout\n");
break;
}
}
if(timeout)
return (length - pHalSsiAdaptor->RxLength);
else
return length;
}
else {
obj->state &= ~ SPI_STATE_RX_BUSY;
return (-ret);
}
}
int32_t spi_slave_read_stream_dma_terminate(spi_t *obj, char *rx_buffer, uint32_t length)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
volatile u8 csterminate;
int ret;
volatile u32 spistate;
csterminate = 0;
if (obj->state & SPI_STATE_RX_BUSY) {
DBG_SSI_WARN("spi_slave_read_stream_dma: state(0x%x) is not ready\r\n",
obj->state);
return HAL_BUSY;
}
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
obj->dma_en |= SPI_DMA_RX_EN;
}
else {
return HAL_BUSY;
}
}
obj->state |= SPI_STATE_RX_BUSY;
HalSsiEnterCritical(pHalSsiAdaptor);
ret = HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length);
HalSsiExitCritical(pHalSsiAdaptor);
while(obj->state & SPI_STATE_RX_BUSY){
spistate = pHalSsiOp->HalSsiGetStatus(pHalSsiAdaptor);
while((spistate & 0x1) == 1){
if((obj->state & SPI_STATE_RX_BUSY) == 0){
csterminate = 0;
break;
}
spistate = pHalSsiOp->HalSsiGetStatus(pHalSsiAdaptor);
if((spistate & 0x1) == 0){
ret = HalSsiStopRecv(pHalSsiAdaptor);
goto EndOfDMACS;
}
}
}
EndOfDMACS:
if((obj->state & SPI_STATE_RX_BUSY) != 0){
csterminate = 1;
obj->state &= ~ SPI_STATE_RX_BUSY;
}
if(csterminate == 1)
return (length - pHalSsiAdaptor->RxLength);
else
return length;
}
#endif
#endif // end of "#ifdef CONFIG_GDMA_EN"

3
targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c
View File

@ -83,8 +83,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
cur_time_us = us_ticker_read();
if ((uint32_t)timestamp >= cur_time_us) {
time_def = (uint32_t)timestamp - cur_time_us;
}
else {
} else {
time_def = 0xffffffff - cur_time_us + (uint32_t)timestamp;
}