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CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets

pull/6273/head
Bartek Szatkowski 2017-07-04 15:22:20 +01:00
parent 4360b7bbf8
commit cc2e0517e1
3 changed files with 21 additions and 0 deletions
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7
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S
View File

@ -74,17 +74,22 @@ SVC_Context
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 ; FPCCR Address LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state) BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch B SVC_ContextSwitch
#endif
SVC_ContextSave SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11 STMDB R12!,{R4-R11} ; Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@ -103,9 +108,11 @@ SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11 LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP MSR PSP,R0 ; Set PSP

7
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S
View File

@ -74,17 +74,22 @@ SVC_Context:
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
TST LR,#0x10 // Check if extended stack frame TST LR,#0x10 // Check if extended stack frame
BNE SVC_ContextSwitch BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 // FPCCR Address LDR R1,=0xE000EF34 // FPCCR Address
LDR R0,[R1] // Load FPCCR LDR R0,[R1] // Load FPCCR
BIC R0,R0,#1 // Clear LSPACT (Lazy state) BIC R0,R0,#1 // Clear LSPACT (Lazy state)
STR R0,[R1] // Store FPCCR STR R0,[R1] // Store FPCCR
B SVC_ContextSwitch B SVC_ContextSwitch
#endif
SVC_ContextSave: SVC_ContextSave:
STMDB R12!,{R4-R11} // Save R4..R11 STMDB R12!,{R4-R11} // Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 // Check if extended stack frame TST LR,#0x10 // Check if extended stack frame
IT EQ IT EQ
VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31 VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] // Store SP STR R12,[R1,#TCB_SP_OFS] // Store SP
STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information
@ -96,9 +101,11 @@ SVC_ContextRestore:
LDR R0,[R2,#TCB_SP_OFS] // Load SP LDR R0,[R2,#TCB_SP_OFS] // Load SP
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 // Check if extended stack frame TST LR,#0x10 // Check if extended stack frame
IT EQ IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31 VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} // Restore R4..R11 LDMIA R0!,{R4-R11} // Restore R4..R11
MSR PSP,R0 // Set PSP MSR PSP,R0 // Set PSP

7
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S
View File

@ -74,17 +74,22 @@ SVC_Context
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 ; FPCCR Address LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state) BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch B SVC_ContextSwitch
#endif
SVC_ContextSave SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11 STMDB R12!,{R4-R11} ; Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@ -96,9 +101,11 @@ SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11 LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP MSR PSP,R0 ; Set PSP