diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S
index 7d405b7e4e..803c7c378c 100644
--- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S
+++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S
@@ -74,17 +74,22 @@ SVC_Context
                 CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
                 TST      LR,#0x10               ; Check if extended stack frame
                 BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
                 LDR      R1,=0xE000EF34         ; FPCCR Address
                 LDR      R0,[R1]                ; Load FPCCR
                 BIC      R0,R0,#1               ; Clear LSPACT (Lazy state)
                 STR      R0,[R1]                ; Store FPCCR
                 B        SVC_ContextSwitch
+#endif
 
 SVC_ContextSave
                 STMDB    R12!,{R4-R11}          ; Save R4..R11
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31
+#endif
+
                 STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
                 STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information
 
@@ -103,9 +108,11 @@ SVC_ContextRestore
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
                 LDMIA    R0!,{R4-R11}           ; Restore R4..R11
                 MSR      PSP,R0                 ; Set PSP
 
diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S
index 568419a33c..cd59935afb 100644
--- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S
+++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S
@@ -74,17 +74,22 @@ SVC_Context:
         CBNZ     R1,SVC_ContextSave     // Branch if running thread is not deleted
         TST      LR,#0x10               // Check if extended stack frame
         BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
         LDR      R1,=0xE000EF34         // FPCCR Address
         LDR      R0,[R1]                // Load FPCCR
         BIC      R0,R0,#1               // Clear LSPACT (Lazy state)
         STR      R0,[R1]                // Store FPCCR
         B        SVC_ContextSwitch
+#endif
 
 SVC_ContextSave:
         STMDB    R12!,{R4-R11}          // Save R4..R11
+#ifdef __FPU_PRESENT
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VSTMDBEQ R12!,{S16-S31}         //  Save VFP S16.S31
+#endif
+
         STR      R12,[R1,#TCB_SP_OFS]   // Store SP
         STRB     LR, [R1,#TCB_SF_OFS]   // Store stack frame information
 
@@ -96,9 +101,11 @@ SVC_ContextRestore:
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
         ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
 
+#ifdef __FPU_PRESENT
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
+#endif
         LDMIA    R0!,{R4-R11}           // Restore R4..R11
         MSR      PSP,R0                 // Set PSP
 
diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S
index 5a956481e8..4f8f3d4c8f 100644
--- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S
+++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S
@@ -74,17 +74,22 @@ SVC_Context
                 CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
                 TST      LR,#0x10               ; Check if extended stack frame
                 BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
                 LDR      R1,=0xE000EF34         ; FPCCR Address
                 LDR      R0,[R1]                ; Load FPCCR
                 BIC      R0,R0,#1               ; Clear LSPACT (Lazy state)
                 STR      R0,[R1]                ; Store FPCCR
                 B        SVC_ContextSwitch
+#endif
 
 SVC_ContextSave
                 STMDB    R12!,{R4-R11}          ; Save R4..R11
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31
+#endif
+
                 STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
                 STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information
 
@@ -96,9 +101,11 @@ SVC_ContextRestore
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
                 LDMIA    R0!,{R4-R11}           ; Restore R4..R11
                 MSR      PSP,R0                 ; Set PSP