mirror of https://github.com/ARMmbed/mbed-os.git
mbed_hal-qspi test code refactoring after PR 7783 review
- refactoring of status/config register logging code, - make QspiCommand a class,pull/7783/head
parent
3bf9df7b56
commit
c94f22c7ad
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@ -247,13 +247,17 @@ void qspi_write_read_test(void)
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WAIT_FOR(WRSR_MAX_TIME, qspi);
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WAIT_FOR(WRSR_MAX_TIME, qspi);
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#ifdef QSPI_TEST_LOG_FLASH_STATUS
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#ifdef QSPI_TEST_LOG_FLASH_STATUS
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utest_printf("Status\r\n"); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi);
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//utest_printf("Status register:\r\n");
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utest_printf("Config 0\r\n"); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi);
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log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi, "Status register");
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//utest_printf("Config register 0:\r\n");
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log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi, "Config register 0");
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#ifdef CONFIG_REG1
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#ifdef CONFIG_REG1
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utest_printf("Config 1\r\n"); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi);
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//utest_printf("Config register 1:\r\n");
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log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi, "Config register 1");
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#endif
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#endif
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#ifdef CONFIG_REG2
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#ifdef CONFIG_REG2
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utest_printf("Config 2\r\n"); log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi);
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//utest_printf("Config register 2:\r\n");
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log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi, "Config register 2");
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#endif
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#endif
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#endif
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#endif
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@ -314,13 +318,17 @@ void qspi_init_free_test(void)
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flash_init(qspi);
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flash_init(qspi);
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#ifdef QSPI_TEST_LOG_FLASH_STATUS
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#ifdef QSPI_TEST_LOG_FLASH_STATUS
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utest_printf("Status\r\n"); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi);
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//utest_printf("Status register:\r\n");
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utest_printf("Config 0\r\n"); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi);
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log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi, "Status register");
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//utest_printf("Config register 0:\r\n");
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log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi, "Config register 0");
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#ifdef CONFIG_REG1
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#ifdef CONFIG_REG1
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utest_printf("Config 1\r\n"); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi);
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//utest_printf("Config register 1:\r\n");
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log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi, "Config register 1");
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#endif
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#endif
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#ifdef CONFIG_REG2
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#ifdef CONFIG_REG2
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utest_printf("Config 2\r\n"); log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi);
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//utest_printf("Config register 2:\r\n");
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log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi, "Config register 2");
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#endif
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#endif
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#endif
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#endif
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@ -32,39 +32,39 @@ void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_w
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qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
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qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
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int dummy_cycles)
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int dummy_cycles)
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{
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{
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memset(&cmd, 0, sizeof(qspi_command_t) );
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memset(&_cmd, 0, sizeof(qspi_command_t) );
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cmd.instruction.disabled = cmd.address.disabled = cmd.alt.disabled = true;
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_cmd.instruction.disabled = _cmd.address.disabled = _cmd.alt.disabled = true;
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cmd.instruction.bus_width = inst_width;
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_cmd.instruction.bus_width = inst_width;
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cmd.address.bus_width = addr_width;
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_cmd.address.bus_width = addr_width;
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cmd.address.size = addr_size;
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_cmd.address.size = addr_size;
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cmd.alt.bus_width = alt_width;
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_cmd.alt.bus_width = alt_width;
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cmd.alt.size = alt_size;
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_cmd.alt.size = alt_size;
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cmd.data.bus_width = data_width;
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_cmd.data.bus_width = data_width;
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cmd.dummy_count = dummy_cycles;
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_cmd.dummy_count = dummy_cycles;
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}
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}
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void QspiCommand::build(int instruction, int address, int alt)
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void QspiCommand::build(int instruction, int address, int alt)
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{
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{
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cmd.instruction.disabled = (instruction == QSPI_NONE);
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_cmd.instruction.disabled = (instruction == QSPI_NONE);
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if (!cmd.instruction.disabled) {
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if (!_cmd.instruction.disabled) {
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cmd.instruction.value = instruction;
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_cmd.instruction.value = instruction;
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}
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}
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cmd.address.disabled = (address == QSPI_NONE);
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_cmd.address.disabled = (address == QSPI_NONE);
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if (!cmd.address.disabled) {
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if (!_cmd.address.disabled) {
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cmd.address.value = address;
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_cmd.address.value = address;
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}
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}
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cmd.alt.disabled = (alt == QSPI_NONE);
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_cmd.alt.disabled = (alt == QSPI_NONE);
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if (!cmd.alt.disabled) {
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if (!_cmd.alt.disabled) {
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cmd.alt.value = alt;
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_cmd.alt.value = alt;
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}
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}
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}
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}
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qspi_command_t* QspiCommand::get()
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qspi_command_t* QspiCommand::get()
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{
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{
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return &cmd;
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return &_cmd;
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}
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}
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@ -165,7 +165,7 @@ qspi_status_t write_disable(Qspi &qspi)
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return ((reg[0] & STATUS_BIT_WEL) == 0 ? QSPI_STATUS_OK : QSPI_STATUS_ERROR);
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return ((reg[0] & STATUS_BIT_WEL) == 0 ? QSPI_STATUS_OK : QSPI_STATUS_ERROR);
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}
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}
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void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi)
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void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str)
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{
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{
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qspi_status_t ret;
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qspi_status_t ret;
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static uint8_t reg[QSPI_MAX_REG_SIZE];
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static uint8_t reg[QSPI_MAX_REG_SIZE];
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@ -174,9 +174,9 @@ void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi)
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TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
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TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
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for (uint32_t j = 0; j < reg_size; j++) {
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for (uint32_t j = 0; j < reg_size; j++) {
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utest_printf("register byte %u data: ", j);
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utest_printf("%s byte %u (MSB first): ", str != NULL ? str : "", j);
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for(int i = 0; i < 8; i++) {
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for(int i = 0; i < 8; i++) {
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utest_printf("%s ", ((reg[j] & (1 << i)) & 0xFF) == 0 ? "0" : "1");
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utest_printf("%s ", ((reg[j] & (1 << (7 - i))) & 0xFF) == 0 ? "0" : "1");
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}
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}
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utest_printf("\r\n");
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utest_printf("\r\n");
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}
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}
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@ -28,8 +28,8 @@ enum QspiStatus {
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sUnknown
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sUnknown
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};
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};
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struct QspiCommand {
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class QspiCommand {
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public:
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void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
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void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
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qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
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qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
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int dummy_cycles = 0);
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int dummy_cycles = 0);
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@ -38,7 +38,8 @@ struct QspiCommand {
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qspi_command_t * get();
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qspi_command_t * get();
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qspi_command_t cmd;
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private:
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qspi_command_t _cmd;
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};
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};
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struct Qspi {
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struct Qspi {
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@ -122,7 +123,7 @@ qspi_status_t write_enable(Qspi &qspi);
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qspi_status_t write_disable(Qspi &qspi);
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qspi_status_t write_disable(Qspi &qspi);
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void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi);
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void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
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qspi_status_t dual_enable(Qspi &qspi);
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qspi_status_t dual_enable(Qspi &qspi);
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