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[NUCLEO_F103RB] Code cleanup, correction in pins definition

pull/150/head
bcostm 2014-01-13 09:24:31 +01:00
parent 7d145c8dc4
commit bef6fdf339
2 changed files with 47 additions and 32 deletions
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3
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PinNames.h
View File

@ -102,8 +102,9 @@ typedef enum {
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_0 = 0x30,
PD_1 = 0x31,
PD_2 = 0x32,
PD_8 = 0x38,
// Arduino connector namings
A0 = PA_0,

76
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c
View File

@ -29,6 +29,19 @@
#include "us_ticker_api.h"
#include "PeripheralNames.h"
// Timers selection:
// The Master timer clocks the Slave timer
#define TIM_MST TIM1
#define TIM_MST_IRQ TIM1_CC_IRQn
#define TIM_MST_RCC RCC_APB2Periph_TIM1
#define TIM_SLV TIM4
#define TIM_SLV_IRQ TIM4_IRQn
#define TIM_SLV_RCC RCC_APB1Periph_TIM4
#define MST_SLV_ITR TIM_TS_ITR0
int us_ticker_inited = 0;
void us_ticker_init(void) {
@ -40,19 +53,18 @@ void us_ticker_init(void) {
us_ticker_inited = 1;
// Enable Timers clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
RCC_APB2PeriphClockCmd(TIM_MST_RCC, ENABLE);
RCC_APB1PeriphClockCmd(TIM_SLV_RCC, ENABLE);
// Time base configuration
// TIM1 is used as "master", "TIM4" as "slave". TIM4 is clocked by TIM1.
// Master and Slave timers time base configuration
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
TIM_TimeBaseInit(TIM_SLV, &TIM_TimeBaseStructure);
// Master timer configuration
TIM_OCStructInit(&TIM_OCInitStructure);
@ -60,32 +72,34 @@ void us_ticker_init(void) {
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 0;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable);
TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update);
TIM_OC1Init(TIM_MST, &TIM_OCInitStructure);
TIM_SelectMasterSlaveMode(TIM_MST, TIM_MasterSlaveMode_Enable);
TIM_SelectOutputTrigger(TIM_MST, TIM_TRGOSource_Update);
// Slave timer configuration
TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_External1);
TIM_SelectInputTrigger(TIM4, TIM_TS_ITR0);
TIM_SelectSlaveMode(TIM_SLV, TIM_SlaveMode_External1);
// The connection between Master and Slave is done here
TIM_SelectInputTrigger(TIM_SLV, MST_SLV_ITR);
// Enable timers
TIM_Cmd(TIM4, ENABLE);
TIM_Cmd(TIM1, ENABLE);
TIM_Cmd(TIM_SLV, ENABLE);
TIM_Cmd(TIM_MST, ENABLE);
}
uint32_t us_ticker_read() {
uint32_t counter, counter2;
if (!us_ticker_inited) us_ticker_init();
// A situation might appear when TIM1 overflows right after TIM4 is read and before the
// new (overflowed) value of TIM1 is read, which would make the code below consider the
// previous (incorrect) value of TIM4 and the new value of TIM1, which would return a
// A situation might appear when Master overflows right after Slave is read and before the
// new (overflowed) value of Master is read. Which would make the code below consider the
// previous (incorrect) value of Slave and the new value of Master, which would return a
// value in the past. Avoid this by computing consecutive values of the timer until they
// are properly ordered.
counter = counter2 = (uint32_t)((uint32_t)TIM_GetCounter(TIM4) << 16) + (uint32_t)TIM_GetCounter(TIM1);
counter = counter2 = (uint32_t)((uint32_t)TIM_GetCounter(TIM_SLV) << 16) + (uint32_t)TIM_GetCounter(TIM_MST);
while (1) {
counter2 = (uint32_t)((uint32_t)TIM_GetCounter(TIM4) << 16) + (uint32_t)TIM_GetCounter(TIM1);
if (counter2 > counter)
counter2 = (uint32_t)((uint32_t)TIM_GetCounter(TIM_SLV) << 16) + (uint32_t)TIM_GetCounter(TIM_MST);
if (counter2 > counter) {
break;
}
counter = counter2;
}
return counter2;
@ -93,25 +107,25 @@ uint32_t us_ticker_read() {
void us_ticker_set_interrupt(unsigned int timestamp) {
if (timestamp > 0xFFFF) {
TIM_SetCompare1(TIM4, (uint16_t)((timestamp >> 16) & 0xFFFF));
TIM_ITConfig(TIM4, TIM_IT_CC1, ENABLE);
NVIC_SetVector(TIM4_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(TIM4_IRQn);
TIM_SetCompare1(TIM_SLV, (uint16_t)((timestamp >> 16) & 0xFFFF));
TIM_ITConfig(TIM_SLV, TIM_IT_CC1, ENABLE);
NVIC_SetVector(TIM_SLV_IRQ, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(TIM_SLV_IRQ);
}
else {
TIM_SetCompare1(TIM1, (uint16_t)timestamp);
TIM_ITConfig(TIM1, TIM_IT_CC1, ENABLE);
NVIC_SetVector(TIM1_CC_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(TIM1_CC_IRQn);
TIM_SetCompare1(TIM_MST, (uint16_t)timestamp);
TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE);
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(TIM_MST_IRQ);
}
}
void us_ticker_disable_interrupt(void) {
TIM_ITConfig(TIM1, TIM_IT_CC1, DISABLE);
TIM_ITConfig(TIM4, TIM_IT_CC1, DISABLE);
TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE);
TIM_ITConfig(TIM_SLV, TIM_IT_CC1, DISABLE);
}
void us_ticker_clear_interrupt(void) {
TIM_ClearITPendingBit(TIM1, TIM_IT_CC1);
TIM_ClearITPendingBit(TIM4, TIM_IT_CC1);
TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
TIM_ClearITPendingBit(TIM_SLV, TIM_IT_CC1);
}