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STM32 TARGET_STM astyle corrections

pull/12069/head
jeromecoutant 2019-12-10 14:35:32 +01:00
parent 54aa300a3c
commit bea83d02c2
12 changed files with 154 additions and 161 deletions
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16
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c
View File

@ -209,8 +209,7 @@ void SystemInit (void)
EXTI_D2->EMR3 |= 0x4000UL;
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) {
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t *)0x51008108) = 0x000000001U;
@ -288,8 +287,7 @@ void SystemCoreClockUpdate (void)
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
switch (RCC->CFGR & RCC_CFGR_SWS) {
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
SystemD1Clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
@ -313,10 +311,8 @@ void SystemCoreClockUpdate (void)
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
if (pllm != 0U)
{
switch (pllsource)
{
if (pllm != 0U) {
switch (pllsource) {
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)) ;
@ -338,9 +334,7 @@ void SystemCoreClockUpdate (void)
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
SystemD1Clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
}
else
{
} else {
SystemD1Clock = 0U;
}
break;

3
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c
View File

@ -102,8 +102,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
{
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) {
return 0; // FAIL
}

6
targets/TARGET_STM/watchdog_api.c
View File

@ -51,7 +51,8 @@
#define INVALID_IWDG_PR ((MAX_IWDG_PR) + 1) // Arbitrary value used to mark an invalid PR bits value.
// Pick a minimal Prescaler_divider bits (PR) value suitable for given timeout.
static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms) {
static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms)
{
for (uint8_t pr = 0; pr <= MAX_IWDG_PR; pr++) {
// Check that max timeout for given pr is greater than
// or equal to timeout_ms.
@ -80,8 +81,7 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config)
IwdgHandle.Init.Window = IWDG_WINDOW_DISABLE;
#endif
if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK)
{
if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK) {
error("HAL_IWDG_Init error\n");
}