diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index 4f9d32eaf8..04a160a9d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -254,7 +254,7 @@ void serial_clear(serial_t *obj) UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; /* Clear RXNE and error flags */ - volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; HAL_UART_ErrorCallback(huart); } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralNames.h index f31610176b..38f0b62135 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralNames.h @@ -4,7 +4,7 @@ * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralPins.c index 8a5cb459fa..6390106406 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PeripheralPins.c @@ -4,7 +4,7 @@ * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PinNames.h index 24b32dbb70..a957df6f98 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/TARGET_ARCH_MAX/PinNames.h @@ -4,7 +4,7 @@ * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/objects.h index 6fbe9cbbcc..c04266a641 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xE/objects.h @@ -4,7 +4,7 @@ * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h b/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h index 1d8e0cf0ee..bc6f761f18 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h @@ -57,5 +57,5 @@ extern const pwm_apb_map_t pwm_apb_map_table[]; #ifdef __cplusplus } #endif - + #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c index eab9464245..5ac4e4c72d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c @@ -311,13 +311,13 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#1- USART2_CTS_NSS {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX - {PA_9_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_TX + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_TX {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to SPI2_SCK {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to HDMI_CEC {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to HDMI_CEC - {PB_6_ALT1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, // Connected to HDMI_CEC + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, // Connected to HDMI_CEC {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#19_DFSDM-DATA7 {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D3 {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D6 @@ -343,12 +343,12 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ULPI_D0 {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to CEC_CK/MCO1 {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX - {PA_10_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_RX + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_RX {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to PMOD\#1 {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D7 {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#20_DFSDM-CK7 {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D4 {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D5 @@ -373,7 +373,7 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SPI2_SCK - {PA_12_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to SPI2_SCK + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to SPI2_SCK {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD\#9 {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#9 @@ -391,7 +391,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD\#1- USART2_CTS_NSS {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to PMOD\#1 - {PA_11_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to PMOD\#1 + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to PMOD\#1 {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ULPI_D1 {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D6 {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#8 diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c index 2c8f878263..660376d067 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c @@ -57,11 +57,11 @@ #endif /* HSE_VALUE */ #if !defined (CSI_VALUE) - #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -104,14 +104,14 @@ /** @addtogroup STM32H7xx_System_Private_Variables * @{ */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ +/* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ #if defined(CORE_CM7) #define SystemCoreClock SystemD1Clock #elif defined(CORE_CM4) @@ -119,9 +119,9 @@ #else #error "Wrong core selection" #endif - uint32_t SystemD1Clock = 64000000; - uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +uint32_t SystemD1Clock = 64000000; +uint32_t SystemD2Clock = 64000000; +const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -146,95 +146,94 @@ * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ - #endif + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */ +#endif /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is detectable by the CPU after a WFI/WFE instruction.*/ - SCB->SCR |= SCB_SCR_SEVONPEND_Pos; + SCB->SCR |= SCB_SCR_SEVONPEND_Pos; #ifdef CORE_CM7 - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= RCC_CR_HSION; + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; - /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEAF6ED7FU; + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; - /* Reset D1CFGR register */ - RCC->D1CFGR = 0x00000000; + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; - /* Reset D2CFGR register */ - RCC->D2CFGR = 0x00000000; + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; - /* Reset D3CFGR register */ - RCC->D3CFGR = 0x00000000; + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; - /* Reset PLLCKSELR register */ - RCC->PLLCKSELR = 0x00000000; + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00000000; - /* Reset PLL1DIVR register */ - RCC->PLL1DIVR = 0x00000000; - /* Reset PLL1FRACR register */ - RCC->PLL1FRACR = 0x00000000; + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; - /* Reset PLL2DIVR register */ - RCC->PLL2DIVR = 0x00000000; + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; - /* Reset PLL2FRACR register */ + /* Reset PLL2FRACR register */ - RCC->PLL2FRACR = 0x00000000; - /* Reset PLL3DIVR register */ - RCC->PLL3DIVR = 0x00000000; + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; - /* Reset PLL3FRACR register */ - RCC->PLL3FRACR = 0x00000000; + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; - /* Disable all interrupts */ - RCC->CIER = 0x00000000; + /* Disable all interrupts */ + RCC->CIER = 0x00000000; - /* Enable CortexM7 HSEM EXTI line (line 78)*/ - EXTI_D2->EMR3 |= 0x4000UL; + /* Enable CortexM7 HSEM EXTI line (line 78)*/ + EXTI_D2->EMR3 |= 0x4000UL; - if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) - { - /* if stm32h7 revY*/ - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ - *((__IO uint32_t*)0x51008108) = 0x000000001U; - } + if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t *)0x51008108) = 0x000000001U; + } #endif /* CORE_CM7*/ #ifdef CORE_CM4 - /* Configure the Vector Table location add offset address ------------------*/ + /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader #endif #else #ifdef CORE_CM7 - /* Configure the Vector Table location add offset address ------------------*/ + /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ #else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader #endif #else @@ -281,83 +280,78 @@ void SystemInit (void) * @param None * @retval None */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { - uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; - float_t fracn1, pllvco; + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + float_t fracn1, pllvco; - /* Get SYSCLK source -------------------------------------------------------*/ + /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemD1Clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + switch (RCC->CFGR & RCC_CFGR_SWS) { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + SystemD1Clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); - break; + break; - case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - SystemD1Clock = CSI_VALUE; - break; + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + SystemD1Clock = CSI_VALUE; + break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - SystemD1Clock = HSE_VALUE; - break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + SystemD1Clock = HSE_VALUE; + break; - case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; - pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); - if (pllm != 0U) - { - switch (pllsource) - { - case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + if (pllm != 0U) { + switch (pllsource) { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ - hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; - pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); - break; + break; - case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; - default: - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; - } - pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - SystemD1Clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; + SystemD1Clock = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } else { + SystemD1Clock = 0U; + } + break; + + default: + SystemD1Clock = CSI_VALUE; + break; } - else - { - SystemD1Clock = 0U; - } - break; - default: - SystemD1Clock = CSI_VALUE; - break; - } + /* Compute SystemClock frequency --------------------------------------------------*/ + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]; - /* Compute SystemClock frequency --------------------------------------------------*/ - tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + /* SystemD1Clock frequency : CM7 CPU frequency */ + SystemD1Clock >>= tmp; - /* SystemD1Clock frequency : CM7 CPU frequency */ - SystemD1Clock >>= tmp; - - /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c index e55f6cf447..0e9dd3d7ae 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c @@ -234,15 +234,15 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_VBUS {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SCL {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to USART3_TX - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USART3_RX - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D1 + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USART3_RX + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D1 {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A1 {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D2 {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D2 {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CLK // {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_WE // Connected to the same UART as STDIO_UART_TX {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13 - {PG_7, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_15 + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_15 {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OCTOSPIM_P2_IO6 {NC, NC, 0} }; @@ -273,15 +273,15 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to DFDATIN1 + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to DFDATIN1 {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_MISO {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_CMD {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_OE {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A17 - {PG_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OCTOSPIM_P2_CS {NC, NC, 0} }; @@ -289,16 +289,16 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_A4 {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_CS - {PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CS + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CS {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_DM {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SAI1_SDB {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PSRAM_ADV {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_CLK - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CLK + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CLK {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_CLK {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A16 - {PG_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to PSRAM_A15 + {PG_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to PSRAM_A15 {PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c index 61bfd7d782..27286f78d4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c @@ -102,10 +102,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) - { + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { return 0; // FAIL - } + } // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; diff --git a/targets/TARGET_STM/reset_reason.c b/targets/TARGET_STM/reset_reason.c index b73d1f1869..f962b8746d 100644 --- a/targets/TARGET_STM/reset_reason.c +++ b/targets/TARGET_STM/reset_reason.c @@ -28,7 +28,7 @@ reset_reason_t hal_reset_reason_get(void) #endif #ifdef RCC_FLAG_LPWR1RST - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR1RST))||(__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR2RST))) { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR1RST)) || (__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR2RST))) { return RESET_REASON_WAKE_LOW_POWER; } #endif diff --git a/targets/TARGET_STM/watchdog_api.c b/targets/TARGET_STM/watchdog_api.c index eb0f1141d0..27a152652b 100644 --- a/targets/TARGET_STM/watchdog_api.c +++ b/targets/TARGET_STM/watchdog_api.c @@ -34,12 +34,12 @@ // and Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR) // to a timeout value [ms]. #define PR_RL2UINT64_TIMEOUT_MS(PR_BITS, RL_BITS) \ - ((PR2PRESCALER_DIV(PR_BITS)) * (RL_BITS) * 1000ULL / (LSI_VALUE)) + ((PR2PRESCALER_DIV(PR_BITS)) * (RL_BITS) * 1000ULL / (LSI_VALUE)) // Convert Prescaler_divider bits (PR) of Prescaler_register (IWDG_PR) and a timeout value [ms] // to Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR) #define PR_TIMEOUT_MS2RL(PR_BITS, TIMEOUT_MS) \ - (((TIMEOUT_MS) * (LSI_VALUE) / (PR2PRESCALER_DIV(PR_BITS)) + 999UL) / 1000UL) + (((TIMEOUT_MS) * (LSI_VALUE) / (PR2PRESCALER_DIV(PR_BITS)) + 999UL) / 1000UL) #define MAX_TIMEOUT_MS_UINT64 PR_RL2UINT64_TIMEOUT_MS(MAX_IWDG_PR, MAX_IWDG_RL) #if (MAX_TIMEOUT_MS_UINT64 > UINT32_MAX) @@ -51,7 +51,8 @@ #define INVALID_IWDG_PR ((MAX_IWDG_PR) + 1) // Arbitrary value used to mark an invalid PR bits value. // Pick a minimal Prescaler_divider bits (PR) value suitable for given timeout. -static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms) { +static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms) +{ for (uint8_t pr = 0; pr <= MAX_IWDG_PR; pr++) { // Check that max timeout for given pr is greater than // or equal to timeout_ms. @@ -72,16 +73,15 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) } const uint32_t rl = PR_TIMEOUT_MS2RL(pr, config->timeout_ms); - IwdgHandle.Instance = IWDG; + IwdgHandle.Instance = IWDG; - IwdgHandle.Init.Prescaler = pr; - IwdgHandle.Init.Reload = rl; + IwdgHandle.Init.Prescaler = pr; + IwdgHandle.Init.Reload = rl; #if defined IWDG_WINR_WIN - IwdgHandle.Init.Window = IWDG_WINDOW_DISABLE; + IwdgHandle.Init.Window = IWDG_WINDOW_DISABLE; #endif - if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK) - { + if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK) { error("HAL_IWDG_Init error\n"); } @@ -123,7 +123,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void) features.max_timeout = MAX_TIMEOUT_MS; features.update_config = true; features.disable_watchdog = false; - + /* STM32 IWDG (Independent Watchdog) is clocked by its own dedicated low-speed clock (LSI) */ features.clock_typical_frequency = LSI_VALUE; @@ -139,7 +139,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void) #elif defined(STM32H7) || defined(STM32L4) || defined(STM32WB) features.clock_max_frequency = 33600; #else -#error "unsupported target" +#error "unsupported target" #endif return features;