mirror of https://github.com/ARMmbed/mbed-os.git
CMSIS5: Replace target defined NVIC_Set/GetVector with CMSIS implementation
Bartek Szatkowski
Martin Kojtal
parent
7b022f8785
commit
b97ffe8fdc
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@ -1,43 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2015-2016 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* CMSIS-style functionality to support dynamic vectors
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*/
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#include "cmsis_nvic.h"
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#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) //Location of vectors in RAM
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#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) //Initial vector position in flash
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void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
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uint32_t i;
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// Copy and switch to dynamic vectors if the first time called
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if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
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uint32_t *old_vectors = vectors;
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vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
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for (i=0; i<NVIC_NUM_VECTORS; i++) {
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vectors[i] = old_vectors[i];
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}
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SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
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}
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vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
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}
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uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
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return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
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}
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@ -13,27 +13,11 @@
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* See the License for the specific language governing permissions and
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* limitations under the License.
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*/
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*/
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/*
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* CMSIS-style functionality to support dynamic vectors
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*/
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#ifndef MBED_CMSIS_NVIC_H
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#ifndef MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#include "cmsis.h"
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 //Location of vectors in RAM
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_USER_IRQ_OFFSET 16
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#ifdef __cplusplus
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extern "C" {
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#endif
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void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
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uint32_t __NVIC_GetVector(IRQn_Type IRQn);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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@ -1,58 +0,0 @@
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/* MPS2 CMSIS Library
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*
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* Copyright (c) 2006-2016 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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#include "cmsis_nvic.h"
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#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
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#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
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uint32_t i;
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// Copy and switch to dynamic vectors if the first time called
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if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
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uint32_t *old_vectors = vectors;
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vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
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for (i=0; i<NVIC_NUM_VECTORS; i++) {
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vectors[i] = old_vectors[i];
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}
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SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
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}
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vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
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}
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uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
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return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
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}
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@ -28,27 +28,12 @@
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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*******************************************************************************/
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#ifndef MBED_CMSIS_NVIC_H
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#ifndef MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#include "cmsis.h"
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#define NVIC_NUM_VECTORS (16 + 64)
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#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
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#define NVIC_NUM_VECTORS (16 + 64)
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#define NVIC_USER_IRQ_OFFSET 16
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
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uint32_t NVIC_GetVector(IRQn_Type IRQn);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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@ -1,54 +0,0 @@
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/* MPS2 CMSIS Library
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*
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* Copyright (c) 2006-2016 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
|
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* specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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#include "cmsis_nvic.h"
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#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
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#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
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// int i;
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// Space for dynamic vectors, initialised to allocate in R/W
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static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
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// Set the vector
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vectors[IRQn + 16] = vector;
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}
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uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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// We can always read vectors at 0x0, as the addresses are remapped
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uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
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// Return the vector
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return vectors[IRQn + 16];
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}
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@ -28,27 +28,12 @@
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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*******************************************************************************/
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#ifndef MBED_CMSIS_NVIC_H
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#ifndef MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#include "cmsis.h"
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_USER_IRQ_OFFSET 16
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
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uint32_t NVIC_GetVector(IRQn_Type IRQn);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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@ -1,54 +0,0 @@
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/* MPS2 CMSIS Library
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*
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* Copyright (c) 2006-2016 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the following disclaimer.
|
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
|
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
|
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* specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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#include "cmsis_nvic.h"
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#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
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#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
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// int i;
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// Space for dynamic vectors, initialised to allocate in R/W
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static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
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// Set the vector
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vectors[IRQn + 16] = vector;
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}
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uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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// We can always read vectors at 0x0, as the addresses are remapped
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uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
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// Return the vector
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return vectors[IRQn + 16];
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}
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@ -28,27 +28,12 @@
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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*******************************************************************************/
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#ifndef MBED_CMSIS_NVIC_H
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#ifndef MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#include "cmsis.h"
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_USER_IRQ_OFFSET 16
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
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uint32_t NVIC_GetVector(IRQn_Type IRQn);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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@ -1,58 +0,0 @@
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/* MPS2 CMSIS Library
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*
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* Copyright (c) 2006-2016 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
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* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
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*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
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||||||
*
|
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* 3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software without
|
|
||||||
* specific prior written permission.
|
|
||||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
||||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -28,27 +28,12 @@
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
*******************************************************************************
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 48)
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 48)
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/* MPS2 CMSIS Library
|
|
||||||
*
|
|
||||||
* Copyright (c) 2006-2016 ARM Limited
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software without
|
|
||||||
* specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
||||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -28,27 +28,12 @@
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
*******************************************************************************
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 48)
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 48)
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/* MPS2 CMSIS Library
|
|
||||||
*
|
|
||||||
* Copyright (c) 2006-2015 ARM Limited
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software without
|
|
||||||
* specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
||||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -28,27 +28,12 @@
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
*******************************************************************************
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 48)
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 48)
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,57 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 +29) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
|
||||||
//extern uint32_t _sdvectors;
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 +29) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
|
||||||
//extern uint32_t _sdvectors;
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 +28) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 28) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,57 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x00400000)// Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 +50) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 50) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFE000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2012 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFF8000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFFC00) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFFC00 // Vectors positioned at start of RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFF000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFF000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (__vector_table) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR < NVIC_RAM_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFE000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 100) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -32,20 +32,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 107) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t __NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 107) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 65) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -32,20 +32,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
#include "cmsis.h"
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
/* Symbols defined by the linker script */
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 74) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
|
#endif /* defined(__CC_ARM) */
|
||||||
|
|
||||||
#include "cmsis.h"
|
/* Symbols defined by the linker script */
|
||||||
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
#ifdef __cplusplus
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -32,20 +32,14 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
|
#endif /* defined(__CC_ARM) */
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t __NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
|
|
||||||
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
InstallIRQHandler(IRQn, vector);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
|
#if defined(__CC_ARM)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||||
|
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||||
|
#else
|
||||||
|
extern uint32_t __VECTOR_RAM[];
|
||||||
|
#endif /* defined(__CC_ARM) */
|
||||||
|
|
||||||
#include "cmsis.h"
|
/* Symbols defined by the linker script */
|
||||||
|
#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals
|
||||||
#ifdef __cplusplus
|
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t __NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,65 +0,0 @@
|
||||||
/*******************************************************************************
|
|
||||||
* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included
|
|
||||||
* in all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|
||||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
||||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
|
||||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
||||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
||||||
* OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* Except as contained in this notice, the name of Maxim Integrated
|
|
||||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
|
||||||
* Products, Inc. Branding Policy.
|
|
||||||
*
|
|
||||||
* The mere transfer of this software does not imply any licenses
|
|
||||||
* of trade secrets, proprietary technology, copyrights, patents,
|
|
||||||
* trademarks, maskwork rights, or any other form of intellectual
|
|
||||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
|
||||||
* ownership rights.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
|
|
||||||
__attribute__((aligned(256)))
|
|
||||||
#endif
|
|
||||||
#if defined(TOOLCHAIN_IAR)
|
|
||||||
#pragma data_alignment=256
|
|
||||||
#endif
|
|
||||||
static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR != (uint32_t)ramVectorTable) {
|
|
||||||
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
vectors = (uint32_t*)ramVectorTable;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)ramVectorTable;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -34,20 +34,9 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
extern void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS MXC_IRQ_COUNT
|
#define NVIC_NUM_VECTORS (MXC_IRQ_COUNT)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (ramVectorTable) // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* MBED_CMSIS_NVIC_H */
|
#endif /* MBED_CMSIS_NVIC_H */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "mbed_toolchain.h"
|
||||||
|
|
||||||
|
/* RAM vector_table needs to be aligned with the size of the vector table */
|
||||||
|
/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
|
||||||
|
/* Vector Table Offset which requires the next-power-of-two alignment. This */
|
||||||
|
/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
|
||||||
|
MBED_ALIGN(512)
|
||||||
|
void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
@ -1,65 +0,0 @@
|
||||||
/*******************************************************************************
|
|
||||||
* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included
|
|
||||||
* in all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|
||||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
||||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
|
||||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
||||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
||||||
* OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* Except as contained in this notice, the name of Maxim Integrated
|
|
||||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
|
||||||
* Products, Inc. Branding Policy.
|
|
||||||
*
|
|
||||||
* The mere transfer of this software does not imply any licenses
|
|
||||||
* of trade secrets, proprietary technology, copyrights, patents,
|
|
||||||
* trademarks, maskwork rights, or any other form of intellectual
|
|
||||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
|
||||||
* ownership rights.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
|
|
||||||
__attribute__((aligned(256)))
|
|
||||||
#endif
|
|
||||||
#if defined(TOOLCHAIN_IAR)
|
|
||||||
#pragma data_alignment=256
|
|
||||||
#endif
|
|
||||||
static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR != (uint32_t)ramVectorTable) {
|
|
||||||
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
vectors = (uint32_t*)ramVectorTable;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)ramVectorTable;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -34,20 +34,9 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
extern void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS MXC_IRQ_COUNT
|
#define NVIC_NUM_VECTORS (MXC_IRQ_COUNT)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (ramVectorTable) // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* MBED_CMSIS_NVIC_H */
|
#endif /* MBED_CMSIS_NVIC_H */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "mbed_toolchain.h"
|
||||||
|
|
||||||
|
/* RAM vector_table needs to be aligned with the size of the vector table */
|
||||||
|
/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
|
||||||
|
/* Vector Table Offset which requires the next-power-of-two alignment. This */
|
||||||
|
/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
|
||||||
|
MBED_ALIGN(512)
|
||||||
|
void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
@ -1,65 +0,0 @@
|
||||||
/*******************************************************************************
|
|
||||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included
|
|
||||||
* in all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|
||||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
||||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
|
||||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
||||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
||||||
* OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* Except as contained in this notice, the name of Maxim Integrated
|
|
||||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
|
||||||
* Products, Inc. Branding Policy.
|
|
||||||
*
|
|
||||||
* The mere transfer of this software does not imply any licenses
|
|
||||||
* of trade secrets, proprietary technology, copyrights, patents,
|
|
||||||
* trademarks, maskwork rights, or any other form of intellectual
|
|
||||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
|
||||||
* ownership rights.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
|
|
||||||
__attribute__((aligned(256)))
|
|
||||||
#endif
|
|
||||||
#if defined(TOOLCHAIN_IAR)
|
|
||||||
#pragma data_alignment=256
|
|
||||||
#endif
|
|
||||||
static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR != (uint32_t)ramVectorTable) {
|
|
||||||
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
vectors = (uint32_t*)ramVectorTable;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)ramVectorTable;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -34,20 +34,9 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
extern void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS MXC_IRQ_COUNT
|
#define NVIC_NUM_VECTORS (MXC_IRQ_COUNT)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (ramVectorTable) // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* MBED_CMSIS_NVIC_H */
|
#endif /* MBED_CMSIS_NVIC_H */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "mbed_toolchain.h"
|
||||||
|
|
||||||
|
/* RAM vector_table needs to be aligned with the size of the vector table */
|
||||||
|
/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
|
||||||
|
/* Vector Table Offset which requires the next-power-of-two alignment. This */
|
||||||
|
/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
|
||||||
|
MBED_ALIGN(512)
|
||||||
|
void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
@ -1,65 +0,0 @@
|
||||||
/*******************************************************************************
|
|
||||||
* Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included
|
|
||||||
* in all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|
||||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
||||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
|
||||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
||||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
||||||
* OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* Except as contained in this notice, the name of Maxim Integrated
|
|
||||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
|
||||||
* Products, Inc. Branding Policy.
|
|
||||||
*
|
|
||||||
* The mere transfer of this software does not imply any licenses
|
|
||||||
* of trade secrets, proprietary technology, copyrights, patents,
|
|
||||||
* trademarks, maskwork rights, or any other form of intellectual
|
|
||||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
|
||||||
* ownership rights.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
|
|
||||||
__attribute__((aligned(256)))
|
|
||||||
#endif
|
|
||||||
#if defined(TOOLCHAIN_IAR)
|
|
||||||
#pragma data_alignment=256
|
|
||||||
#endif
|
|
||||||
static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR != (uint32_t)ramVectorTable) {
|
|
||||||
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
vectors = (uint32_t*)ramVectorTable;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)ramVectorTable;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -34,20 +34,10 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
extern void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS MXC_IRQ_COUNT
|
#define NVIC_NUM_VECTORS (MXC_IRQ_COUNT)
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (ramVectorTable) // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* MBED_CMSIS_NVIC_H */
|
#endif /* MBED_CMSIS_NVIC_H */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "mbed_toolchain.h"
|
||||||
|
|
||||||
|
/* RAM vector_table needs to be aligned with the size of the vector table */
|
||||||
|
/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
|
||||||
|
/* Vector Table Offset which requires the next-power-of-two alignment. This */
|
||||||
|
/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
|
||||||
|
MBED_ALIGN(512)
|
||||||
|
void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "mbed_toolchain.h"
|
||||||
|
|
||||||
|
/* RAM vector_table needs to be aligned with the size of the vector table */
|
||||||
|
/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
|
||||||
|
/* Vector Table Offset which requires the next-power-of-two alignment. This */
|
||||||
|
/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
|
||||||
|
MBED_ALIGN(512)
|
||||||
|
void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
|
|
@ -1,93 +0,0 @@
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
* @brief This file contains the implementations of the vendor
|
|
||||||
* defined NVIC function.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/* ****************************************************************************
|
|
||||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included
|
|
||||||
* in all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|
||||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
||||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
|
||||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
||||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
||||||
* OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* Except as contained in this notice, the name of Maxim Integrated
|
|
||||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
|
||||||
* Products, Inc. Branding Policy.
|
|
||||||
*
|
|
||||||
* The mere transfer of this software does not imply any licenses
|
|
||||||
* of trade secrets, proprietary technology, copyrights, patents,
|
|
||||||
* trademarks, maskwork rights, or any other form of intellectual
|
|
||||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
|
||||||
* ownership rights.
|
|
||||||
*
|
|
||||||
* $Date: 2016-09-28 10:27:00 -0500 (Wed, 28 Sep 2016) $
|
|
||||||
* $Revision: 24512 $
|
|
||||||
*
|
|
||||||
*************************************************************************** */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @ingroup mxc_nvic
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* **** Includes **** */
|
|
||||||
#include "mxc_config.h"
|
|
||||||
#include <string.h>
|
|
||||||
#include "nvic_table.h"
|
|
||||||
|
|
||||||
/* RAM vector_table needs to be aligned with the size of the vector table */
|
|
||||||
/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
|
|
||||||
/* Vector Table Offset which requires the next-power-of-two alignment. This */
|
|
||||||
/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma data_alignment = 512
|
|
||||||
#define __isr_vector __vector_table
|
|
||||||
#else
|
|
||||||
__attribute__ ((aligned (512)))
|
|
||||||
#endif
|
|
||||||
static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
|
||||||
|
|
||||||
/* **** Definitions **** */
|
|
||||||
|
|
||||||
/* **** Globals **** */
|
|
||||||
|
|
||||||
/* **** Functions **** */
|
|
||||||
|
|
||||||
/* ************************************************************************* */
|
|
||||||
void NVIC_SetRAM(void)
|
|
||||||
{
|
|
||||||
memcpy(&ramVectorTable, (uint32_t*)SCB->VTOR, sizeof(ramVectorTable));
|
|
||||||
SCB->VTOR = (uint32_t)&ramVectorTable;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ************************************************************************* */
|
|
||||||
int NVIC_SetVector(IRQn_Type irqn, uint32_t irq_handler)
|
|
||||||
{
|
|
||||||
int index = irqn + 16; /* offset for externals */
|
|
||||||
|
|
||||||
/* If not copied, do copy */
|
|
||||||
if(SCB->VTOR != (uint32_t)&ramVectorTable) {
|
|
||||||
NVIC_SetRAM();
|
|
||||||
}
|
|
||||||
|
|
||||||
ramVectorTable[index] = (void(*)(void))irq_handler;
|
|
||||||
NVIC_EnableIRQ(irqn);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
/**@} end of group mxc_nvic */
|
|
||||||
|
|
@ -43,46 +43,9 @@
|
||||||
#ifndef _NVIC_TABLE_H
|
#ifndef _NVIC_TABLE_H
|
||||||
#define _NVIC_TABLE_H
|
#define _NVIC_TABLE_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
extern void (*ramVectorTable[MXC_IRQ_COUNT])(void);
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
#define NVIC_NUM_VECTORS (MXC_IRQ_COUNT)
|
||||||
* @defgroup mxc_nvic NVIC Functions
|
#define NVIC_RAM_VECTOR_ADDRESS (ramVectorTable) // Vectors positioned at start of RAM
|
||||||
* @ingroup sysconfig
|
|
||||||
* @brief Utility function for setting an IRQ handler dynamically
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Type alias for an IRQ handler.
|
|
||||||
* @details Type alias for an IRQ handler function with prototype:.
|
|
||||||
* @code
|
|
||||||
* void irq_handler(void);
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
typedef void (*irq_fn)(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set an IRQ hander function for an IRQ specified by @p irqn.
|
|
||||||
* @details If the IRQ table is in flash, this function will copy the IRQ table to RAM.
|
|
||||||
*
|
|
||||||
* @param irqn ARM external IRQ number, see #IRQn_Type
|
|
||||||
* @param irq_handler Function to be called at IRQ context
|
|
||||||
*/
|
|
||||||
int NVIC_SetVector(IRQn_Type irqn, uint32_t irq_handler);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Copy NVIC vector table to RAM and set NVIC to RAM based table.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void NVIC_SetRAM(void);
|
|
||||||
|
|
||||||
/**@} end of group mxc_nvic */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _NVIC_TABLE_H */
|
#endif /* _NVIC_TABLE_H */
|
||||||
|
|
|
||||||
|
|
@ -1,103 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
|
||||||
* whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
|
|
||||||
* the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
|
|
||||||
* to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
|
|
||||||
*
|
|
||||||
* If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
|
|
||||||
* above the vector table before 0x200 will actually go to RAM. So we need to provide
|
|
||||||
* a solution where the compiler gets the right results based on the memory map
|
|
||||||
*
|
|
||||||
* Option 1 - We allocate and copy 0x200 of RAM rather than just the table
|
|
||||||
* - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
|
|
||||||
* - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
|
|
||||||
*
|
|
||||||
* Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
|
|
||||||
* - No flash accesses will go to ram, as there will be nothing there
|
|
||||||
* - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
|
|
||||||
* - RAM overhead: 0, FLASH overhead: 320 bytes
|
|
||||||
*
|
|
||||||
* Option 2 is the one to go for, as RAM is the most valuable resource
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
/*
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}*/
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
// int i;
|
|
||||||
// Space for dynamic vectors, initialised to allocate in R/W
|
|
||||||
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
/*
|
|
||||||
// Copy and switch to dynamic vectors if first time called
|
|
||||||
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
|
|
||||||
uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
|
|
||||||
for(i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
|
|
||||||
}*/
|
|
||||||
|
|
||||||
// Set the vector
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
// We can always read vectors at 0x0, as the addresses are remapped
|
|
||||||
uint32_t *vectors = (uint32_t*)0;
|
|
||||||
|
|
||||||
// Return the vector
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -32,22 +32,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)
|
||||||
|
|
||||||
#include "nrf51.h"
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2016 ARM Limited. All rights reserved.
|
* Copyright (c) 2016 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2015-2016 Nuvoton
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t *) SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
/* Copy and switch to dynamic vectors if the first time called */
|
|
||||||
if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
|
|
||||||
vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t *) SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -17,57 +17,15 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 64)
|
||||||
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
#define NVIC_USER_IRQ_NUMBER 64
|
|
||||||
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
|
|
||||||
|
|
||||||
#if defined(__CC_ARM)
|
#if defined(__CC_ARM)
|
||||||
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
|
||||||
#elif defined(__ICCARM__)
|
#elif defined(__ICCARM__)
|
||||||
# pragma section = "IRAMVEC"
|
# pragma section = "IRAMVEC"
|
||||||
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
|
||||||
#elif defined(__GNUC__)
|
#elif defined(__GNUC__)
|
||||||
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(__CC_ARM)
|
|
||||||
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
|
|
||||||
#elif defined(__ICCARM__)
|
|
||||||
#pragma section=".intvec"
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
extern uint32_t __vector_table;
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)&__vector_table)
|
|
||||||
#else
|
|
||||||
#error "Flash vector address not set for this toolchain"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** Set the ISR for IRQn
|
|
||||||
*
|
|
||||||
* Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
|
|
||||||
* the first time this function is called
|
|
||||||
* @param[in] IRQn The Interrupt Request number for which a vector will be registered
|
|
||||||
* @param[in] vector The ISR vector to register for IRQn
|
|
||||||
*/
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
|
|
||||||
/** Get the ISR registered for IRQn
|
|
||||||
*
|
|
||||||
* Reads the Interrupt Service Routine currently registered for IRQn
|
|
||||||
* @param[in] IRQn The Interrupt Request number the vector of which will be read
|
|
||||||
* @return Returns the ISR registered for IRQn
|
|
||||||
*/
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2015-2016 Nuvoton
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t *) SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
/* Copy and switch to dynamic vectors if the first time called */
|
|
||||||
if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
|
|
||||||
vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
|
||||||
{
|
|
||||||
uint32_t *vectors = (uint32_t *) SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
@ -17,11 +17,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 142)
|
||||||
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
#define NVIC_USER_IRQ_NUMBER 142
|
|
||||||
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
|
|
||||||
|
|
||||||
#if defined(__CC_ARM)
|
#if defined(__CC_ARM)
|
||||||
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
|
||||||
|
|
@ -32,42 +28,4 @@
|
||||||
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(__CC_ARM)
|
|
||||||
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
|
|
||||||
#elif defined(__ICCARM__)
|
|
||||||
#pragma section=".intvec"
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
extern uint32_t __vector_table;
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)&__vector_table)
|
|
||||||
#else
|
|
||||||
#error "Flash vector address not set for this toolchain"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** Set the ISR for IRQn
|
|
||||||
*
|
|
||||||
* Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
|
|
||||||
* the first time this function is called
|
|
||||||
* @param[in] IRQn The Interrupt Request number for which a vector will be registered
|
|
||||||
* @param[in] vector The ISR vector to register for IRQn
|
|
||||||
*/
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
|
|
||||||
/** Get the ISR registered for IRQn
|
|
||||||
*
|
|
||||||
* Reads the Interrupt Service Routine currently registered for IRQn
|
|
||||||
* @param[in] IRQn The Interrupt Request number the vector of which will be read
|
|
||||||
* @return Returns the ISR registered for IRQn
|
|
||||||
*/
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,81 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
|
||||||
* whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
|
|
||||||
* the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
|
|
||||||
* to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
|
|
||||||
*
|
|
||||||
* If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
|
|
||||||
* above the vector table before 0x200 will actually go to RAM. So we need to provide
|
|
||||||
* a solution where the compiler gets the right results based on the memory map
|
|
||||||
*
|
|
||||||
* Option 1 - We allocate and copy 0x200 of RAM rather than just the table
|
|
||||||
* - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
|
|
||||||
* - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
|
|
||||||
*
|
|
||||||
* Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
|
|
||||||
* - No flash accesses will go to ram, as there will be nothing there
|
|
||||||
* - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
|
|
||||||
* - RAM overhead: 0, FLASH overhead: 320 bytes
|
|
||||||
*
|
|
||||||
* Option 2 is the one to go for, as RAM is the most valuable resource
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
int i;
|
|
||||||
// Space for dynamic vectors, initialised to allocate in R/W
|
|
||||||
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if first time called
|
|
||||||
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
|
|
||||||
uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
|
|
||||||
for(i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the vector
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
// We can always read vectors at 0x0, as the addresses are remapped
|
|
||||||
uint32_t *vectors = (uint32_t*)0;
|
|
||||||
|
|
||||||
// Return the vector
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -32,20 +32,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,82 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
|
|
||||||
* whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
|
|
||||||
* the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
|
|
||||||
* to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
|
|
||||||
*
|
|
||||||
* If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
|
|
||||||
* above the vector table before 0x200 will actually go to RAM. So we need to provide
|
|
||||||
* a solution where the compiler gets the right results based on the memory map
|
|
||||||
*
|
|
||||||
* Option 1 - We allocate and copy 0x200 of RAM rather than just the table
|
|
||||||
* - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
|
|
||||||
* - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
|
|
||||||
*
|
|
||||||
* Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
|
|
||||||
* - No flash accesses will go to ram, as there will be nothing there
|
|
||||||
* - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
|
|
||||||
* - RAM overhead: 0, FLASH overhead: 320 bytes
|
|
||||||
*
|
|
||||||
* Option 2 is the one to go for, as RAM is the most valuable resource
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
int i;
|
|
||||||
// Space for dynamic vectors, initialised to allocate in R/W
|
|
||||||
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if first time called
|
|
||||||
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
|
|
||||||
uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
|
|
||||||
for(i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the vector
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
// We can always read vectors at 0x0, as the addresses are remapped
|
|
||||||
uint32_t *vectors = (uint32_t*)0;
|
|
||||||
|
|
||||||
// Return the vector
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -34,18 +34,7 @@
|
||||||
|
|
||||||
#include "cmsis.h"
|
#include "cmsis.h"
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,56 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Location of vectors in RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x02000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,56 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR < NVIC_RAM_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#include "cmsis.h"
|
#define NVIC_NUM_VECTORS (16 + 33)
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Location of vectors in RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 33)
|
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,56 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 41) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 41) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Location of vectors in RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,61 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
|
|
||||||
|
|
||||||
// The LPC43xx can boot from multiple memories (internal Flash, external NOR,
|
|
||||||
// external SPIFI) so we don't know the initial value of VTOR. Thus we use
|
|
||||||
// a variable to keep track if the vector table was relocated or not
|
|
||||||
static unsigned char vtor_relocated;
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if first time called
|
|
||||||
if (!vtor_relocated) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
vtor_relocated = 1;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 53) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 53) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Location of vectors in RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
|
||||||
uint32_t *old_vectors = vectors;
|
|
||||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
|
||||||
vectors[i] = old_vectors[i];
|
|
||||||
}
|
|
||||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
}
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -1,5 +1,4 @@
|
||||||
/* mbed Microcontroller Library
|
/* mbed Microcontroller Library
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
*******************************************************************************
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
@ -32,20 +31,7 @@
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
#define MBED_CMSIS_NVIC_H
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,43 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file cmsis_nvic.c
|
|
||||||
* @brief Contains relocatable exception table.
|
|
||||||
* @internal
|
|
||||||
* @author ON Semiconductor.
|
|
||||||
* $Rev: 0.1 $
|
|
||||||
* $Date: 2015-11-06 $
|
|
||||||
******************************************************************************
|
|
||||||
* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
|
|
||||||
* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
|
|
||||||
* under limited terms and conditions. The terms and conditions pertaining to the software
|
|
||||||
* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
|
|
||||||
* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
|
|
||||||
* if applicable the software license agreement. Do not use this software and/or
|
|
||||||
* documentation unless you have carefully read and you agree to the limited terms and
|
|
||||||
* conditions. By using this software and/or documentation, you agree to the limited
|
|
||||||
* terms and conditions.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
|
||||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
|
||||||
* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
|
|
||||||
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
|
||||||
* @endinternal
|
|
||||||
*
|
|
||||||
* @ingroup
|
|
||||||
*
|
|
||||||
* @details
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <cmsis_nvic.h>
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x3FFF4000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
|
|
||||||
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|
||||||
{
|
|
||||||
static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
|
|
||||||
|
|
||||||
vectors[IRQn + 16] = vector;
|
|
||||||
}
|
|
||||||
|
|
@ -28,6 +28,6 @@
|
||||||
*
|
*
|
||||||
* @details
|
* @details
|
||||||
*/
|
*/
|
||||||
#include "NCS36510.h"
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
#define NVIC_NUM_VECTORS (16 + 20)
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS 0x3FFF4000 // Vectors positioned at start of RAM
|
||||||
|
|
|
||||||
|
|
@ -1,56 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2015, STMicroelectronics
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
|
||||||
int i;
|
|
||||||
|
|
||||||
// Copy and switch to dynamic vectors if first time called
|
|
||||||
if ((SYSCFG->CFGR1 & SYSCFG_CFGR1_MEM_MODE) != SYSCFG_CFGR1_MEM_MODE) {
|
|
||||||
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
|
|
||||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
|
||||||
*((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i*4))) = old_vectors[i];
|
|
||||||
}
|
|
||||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; // Embedded SRAM mapped at 0x00000000
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the vector
|
|
||||||
*((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn*4) + (NVIC_USER_IRQ_OFFSET*4))) = vector;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
|
||||||
uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
|
||||||
// Return the vector
|
|
||||||
return vectors[IRQn + 16];
|
|
||||||
}
|
|
||||||
|
|
@ -36,20 +36,7 @@
|
||||||
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||||
// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
|
// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
|
||||||
// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
|
// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
|
||||||
#define NVIC_NUM_VECTORS (16 + 32 )
|
#define NVIC_NUM_VECTORS (16 + 32 )
|
||||||
#define NVIC_USER_IRQ_OFFSET 16
|
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
|
||||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
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Reference in New Issue