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Cypress: Fix non-compliant ADC range 

The ADC range was previously 0-VBGR*2 (0 - 2.4 V). Change the reference
so that the ADC range is 0 - VDDA, to bring it in line with the documented
behavior of the mbed hal.
pull/12909/head
Kyle Kearney 2020-04-27 17:11:44 -07:00
parent a63fe7d801
commit af39f0512a
1 changed files with 1 additions and 1 deletions
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2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c
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@ -61,7 +61,7 @@ static const en_clk_dst_t cyhal_sar_clock[] =
#endif
};
#define CYHAL_SAR_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_BGR \
#define CYHAL_SAR_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_VDDA_DIV_2 \
| (uint32_t)CY_SAR_BYPASS_CAP_DISABLE | (uint32_t)CY_SAR_NEG_SEL_VREF \
| (uint32_t)CY_SAR_CTRL_NEGVREF_HW | (uint32_t)CY_SAR_CTRL_COMP_DLY_12 \
| (uint32_t)CY_SAR_COMP_PWR_100 | (uint32_t)CY_SAR_DEEPSLEEP_SARMUX_OFF \