From af39f0512aa8a8d453c4c990d4979d274f084e43 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Mon, 27 Apr 2020 17:11:44 -0700 Subject: [PATCH] Cypress: Fix non-compliant ADC range The ADC range was previously 0-VBGR*2 (0 - 2.4 V). Change the reference so that the ADC range is 0 - VDDA, to bring it in line with the documented behavior of the mbed hal. --- .../TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c index 4a7f8a9a30..5be7d05d6f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c @@ -61,7 +61,7 @@ static const en_clk_dst_t cyhal_sar_clock[] = #endif }; -#define CYHAL_SAR_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_BGR \ +#define CYHAL_SAR_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_VDDA_DIV_2 \ | (uint32_t)CY_SAR_BYPASS_CAP_DISABLE | (uint32_t)CY_SAR_NEG_SEL_VREF \ | (uint32_t)CY_SAR_CTRL_NEGVREF_HW | (uint32_t)CY_SAR_CTRL_COMP_DLY_12 \ | (uint32_t)CY_SAR_COMP_PWR_100 | (uint32_t)CY_SAR_DEEPSLEEP_SARMUX_OFF \