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[LPC1114]: uARM fixed 

Tested with only "[ 32] MBED_11: Ticker"
pull/17/head
ytsuboi 2013-07-27 02:06:12 +09:00
parent 8c2ede6f4f
commit a9f0d9a3f7
1 changed files with 171 additions and 82 deletions
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253
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s
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@ -1,59 +1,46 @@
;/**************************************************************************//** ;/*****************************************************************************
; * @file startup_LPC11xx.s ; * @file: startup_LPC11xx.s
; * @brief CMSIS Cortex-M0 Core Device Startup File ; * @purpose: CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11xx/LPC11Cxx Device Series ; * for the NXP LPC11xx Device Series
; * @version V1.10 ; * @version: V1.0
; * @date 24. November 2010 ; * @date: 25. Nov. 2008
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; * ; *
; * @note ; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * Copyright (C) 2009-2010 ARM Limited. All rights reserved. ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed ; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors. ; * within development tools that are supporting such ARM based processors.
; * ; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; * ; *
; ******************************************************************************/ ; *****************************************************************************/
Stack_Size EQU 0x00000400
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3 AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp EXPORT __initial_sp
Stack_Mem SPACE Stack_Size Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114 __initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000 Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3 AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base EXPORT __heap_base
EXPORT __heap_limit EXPORT __heap_limit
__heap_base __heap_base
Heap_Mem SPACE Heap_Size Heap_Mem SPACE Heap_Size
__heap_limit __heap_limit
PRESERVE8 PRESERVE8
THUMB THUMB
; Vector Table Mapped to Address 0 at Reset ; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY AREA RESET, DATA, READONLY
@ -76,41 +63,129 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD PendSV_Handler ; PendSV Handler DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler DCD SysTick_Handler ; SysTick Handler
; External Interrupts DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD WAKEUP_IRQHandler ; 16+ 0: Wakeup PIO0.0 DCD FLEX_INT1_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 1: Wakeup PIO0.1 DCD FLEX_INT2_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 2: Wakeup PIO0.2 DCD FLEX_INT3_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 3: Wakeup PIO0.3 DCD FLEX_INT4_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 4: Wakeup PIO0.4 DCD FLEX_INT5_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 5: Wakeup PIO0.5 DCD FLEX_INT6_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 6: Wakeup PIO0.6 DCD FLEX_INT7_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 7: Wakeup PIO0.7 DCD GINT0_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+ 8: Wakeup PIO0.8 DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD WAKEUP_IRQHandler ; 16+ 9: Wakeup PIO0.9 DCD Reserved_IRQHandler ; Reserved
DCD WAKEUP_IRQHandler ; 16+10: Wakeup PIO0.10 DCD Reserved_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+11: Wakeup PIO0.11 DCD Reserved_IRQHandler ;
DCD WAKEUP_IRQHandler ; 16+12: Wakeup PIO1.0 DCD Reserved_IRQHandler ;
DCD CAN_IRQHandler ; 16+13: CAN DCD SSP1_IRQHandler ; SSP1
DCD SSP1_IRQHandler ; 16+14: SSP1 DCD I2C_IRQHandler ; I2C
DCD I2C_IRQHandler ; 16+15: I2C DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_0_IRQHandler ; 16+16: 16-bit Counter-Timer 0 DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER16_1_IRQHandler ; 16+17: 16-bit Counter-Timer 1 DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_0_IRQHandler ; 16+18: 32-bit Counter-Timer 0 DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD TIMER32_1_IRQHandler ; 16+19: 32-bit Counter-Timer 1 DCD SSP0_IRQHandler ; SSP0
DCD SSP0_IRQHandler ; 16+20: SSP0 DCD UART_IRQHandler ; UART
DCD UART_IRQHandler ; 16+21: UART DCD USB_IRQHandler ; USB IRQ
DCD USB_IRQHandler ; 16+22: USB IRQ DCD USB_FIQHandler ; USB FIQ
DCD USB_FIQHandler ; 16+24: USB FIQ DCD ADC_IRQHandler ; A/D Converter
DCD ADC_IRQHandler ; 16+24: A/D Converter DCD WDT_IRQHandler ; Watchdog timer
DCD WDT_IRQHandler ; 16+25: Watchdog Timer DCD BOD_IRQHandler ; Brown Out Detect
DCD BOD_IRQHandler ; 16+26: Brown Out Detect DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD FMC_IRQHandler ; 16+27: IP2111 Flash Memory Controller DCD Reserved_IRQHandler ; Reserved
DCD PIOINT3_IRQHandler ; 16+28: PIO INT3 DCD Reserved_IRQHandler ; Reserved
DCD PIOINT2_IRQHandler ; 16+29: PIO INT2 DCD Reserved_IRQHandler ; Reserved
DCD PIOINT1_IRQHandler ; 16+30: PIO INT1 DCD Reserved_IRQHandler ; Reserved
DCD PIOINT0_IRQHandler ; 16+31: PIO INT0
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
IF :LNOT::DEF:NO_CRP IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF CRP_Key DCD 0xFFFFFFFF
@ -120,6 +195,7 @@ CRP_Key DCD 0xFFFFFFFF
AREA |.text|, CODE, READONLY AREA |.text|, CODE, READONLY
; Reset Handler ; Reset Handler
Reset_Handler PROC Reset_Handler PROC
@ -132,13 +208,14 @@ Reset_Handler PROC
BX R0 BX R0
ENDP ENDP
; Dummy Exception Handlers (infinite loops which can be modified) ; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC ; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
EXPORT NMI_Handler [WEAK] ; for particular peripheral.
B . ;NMI_Handler PROC
ENDP ; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\ HardFault_Handler\
PROC PROC
EXPORT HardFault_Handler [WEAK] EXPORT HardFault_Handler [WEAK]
@ -156,11 +233,24 @@ SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK] EXPORT SysTick_Handler [WEAK]
B . B .
ENDP ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC Default_Handler PROC
; for LPC11Uxx (With USB)
EXPORT WAKEUP_IRQHandler [WEAK] EXPORT NMI_Handler [WEAK]
EXPORT CAN_IRQHandler [WEAK] EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK] EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK] EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK] EXPORT TIMER16_0_IRQHandler [WEAK]
@ -169,19 +259,26 @@ Default_Handler PROC
EXPORT TIMER32_1_IRQHandler [WEAK] EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK] EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK] EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK] EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK] EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK] EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK] EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK]
EXPORT PIOINT3_IRQHandler [WEAK] EXPORT USBWakeup_IRQHandler [WEAK]
EXPORT PIOINT2_IRQHandler [WEAK]
EXPORT PIOINT1_IRQHandler [WEAK]
EXPORT PIOINT0_IRQHandler [WEAK]
WAKEUP_IRQHandler NMI_Handler
CAN_IRQHandler FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler SSP1_IRQHandler
I2C_IRQHandler I2C_IRQHandler
TIMER16_0_IRQHandler TIMER16_0_IRQHandler
@ -196,19 +293,11 @@ ADC_IRQHandler
WDT_IRQHandler WDT_IRQHandler
BOD_IRQHandler BOD_IRQHandler
FMC_IRQHandler FMC_IRQHandler
PIOINT3_IRQHandler USBWakeup_IRQHandler
PIOINT2_IRQHandler
PIOINT1_IRQHandler
PIOINT0_IRQHandler
B . B .
ENDP ENDP
ALIGN ALIGN
; @toyowata removed "User Initial Stack & Heap" block here,
; since arm.py script doesn't pass -D__MICROLIB definision to armasm.
; Now, required symbols (__initial_sp etc) were exported in this code.
END END