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Merge pull request #10570 from jeromecoutant/PR_ASTYLE 

STM32 astyle updates
pull/10594/head
Martin Kojtal 2019-05-14 09:22:18 +01:00 committed by GitHub
parent 3ea1c56124 0352bbbd5b
commit a2cde2e24e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 172 additions and 183 deletions
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12
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/system_clock.c
View File

@ -103,8 +103,7 @@ static void Config_HSE(void)
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
if (p_otp)
{
if (p_otp) {
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
}
@ -182,8 +181,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
@ -198,8 +196,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0; // FAIL
}
/** Initializes the peripherals clocks
@ -208,8 +205,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}

20
targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c
View File

@ -67,18 +67,14 @@ static void LPM_EnterStopMode(void)
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
{
if( LL_PWR_IsActiveFlag_C2DS() )
{
if (! LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID)) {
if (LL_PWR_IsActiveFlag_C2DS()) {
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
Switch_On_HSI();
}
}
else
{
} else {
Switch_On_HSI();
}
@ -97,21 +93,17 @@ static void LPM_ExitStopMode(void)
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
if( (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) || (LL_PWR_IsActiveFlag_C1STOP() != 0) )
{
if ((LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) || (LL_PWR_IsActiveFlag_C1STOP() != 0)) {
LL_PWR_ClearFlag_C1STOP_C1STB();
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
if(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
LL_RCC_HSE_Enable();
while (!LL_RCC_HSE_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
}
else
{
} else {
/**
* As long as the current application is fine with HSE as system clock source,
* there is nothing to do here

6
targets/TARGET_STM/mbed_crc_api.c
View File

@ -77,8 +77,7 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
current_state.Init.InitValue = config->initial_xor;
current_state.Init.GeneratingPolynomial = config->polynomial;
switch (config->width)
{
switch (config->width) {
case HAL_CRC_LENGTH_32B:
current_state.Init.CRCLength = CRC_POLYLENGTH_32B;
break;
@ -137,8 +136,9 @@ uint32_t hal_crc_get_result(void)
*/
if (current_state.Init.CRCLength == CRC_POLYLENGTH_7B &&
current_state.Init.GeneratingPolynomial == POLY_7BIT_SD &&
current_state.Init.OutputDataInversionMode == CRC_OUTPUTDATA_INVERSION_DISABLE)
current_state.Init.OutputDataInversionMode == CRC_OUTPUTDATA_INVERSION_DISABLE) {
result = result << 1;
}
#endif
return (result ^ final_xor) & crc_mask;
}

3
targets/TARGET_STM/stm_spi_api.c
View File

@ -92,7 +92,8 @@ void init_spi(spi_t *obj)
}
}
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
{
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);