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Update Cypress udb-sdio-whd to 1.1.0.19214

pull/14062/head
Dustin Crossman 2020-12-01 14:56:02 -08:00 committed by Dustin Crossman
parent d6784c3ee6
commit 9cd6dcabdc
10 changed files with 3965 additions and 3421 deletions
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1696
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c Normal file → Executable file
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101
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h Normal file → Executable file
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@ -1,29 +1,28 @@
/***************************************************************************//**
* \file SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/***********************************************************************************************//**
* \file COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
***************************************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#if !defined(CY_SDIO_CFG_H)
#define CY_SDIO_CFG_H
#pragma once
#include <string.h>
@ -95,10 +94,10 @@ extern "C" {
#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u
/*************Defines for UDBs from Creator*****************************/
/***********These come for cyfitter.h**********************************/
// *************Defines for UDBs from Creator*****************************
// ***********These come for cyfitter.h**********************************
/* SDIO_HOST_bSDIO */
// SDIO_HOST_bSDIO
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x40341008u
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x40341108u
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x40341208u
@ -764,79 +763,80 @@ extern "C" {
#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1
/***************************CMD DMA***************************************/
// **************************CMD DMA***************************************
#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u)
#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_CMD_DMA_HW (DW0)
#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_CMD_DMA_PRIORITY (1u)
#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true)
#define SDIO_HOST_CMD_DMA_BUFFERABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
/***************************Read DMA***************************************/
// **************************Read DMA***************************************
#define SDIO_HOST_Read_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u)
#define SDIO_HOST_Read_DMA_HW (DW1)
#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Read_DMA_PRIORITY (0u)
#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Read_DMA_PREEMPTABLE (false)
#define SDIO_HOST_Read_DMA_BUFFERABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
/***************************Resp DMA***************************************/
// **************************Resp DMA***************************************
#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u)
#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u)
#define SDIO_HOST_Resp_DMA_HW (DW0)
#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Resp_DMA_PRIORITY (1u)
#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true)
#define SDIO_HOST_Resp_DMA_BUFFERABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
/***************************Write DMA***************************************/
// **************************Write DMA***************************************
#define SDIO_HOST_Write_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_Write_DMA_HW (DW1)
#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Write_DMA_PRIORITY (0u)
#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Write_DMA_PREEMPTABLE (false)
#define SDIO_HOST_Write_DMA_BUFFERABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
/***************************SDIO Clock**************************************/
// **************************SDIO Clock**************************************
/** The peripheral clock divider number */
#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)SDIO_HOST_Internal_Clock__DIV_NUM)
/** The peripheral clock divider type */
#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE)
#define SDIO_HOST_Internal_Clock_DIV_TYPE \
((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE)
/*Function for configuring TriggerMuxes*/
// Function for configuring TriggerMuxes
void SDIO_Host_Config_TriggerMuxes(void);
/*Function for configuring UDBs*/
// Function for configuring UDBs
void SDIO_Host_Config_UDBs(void);
/* SDIO_HOST_Read_Int */
// SDIO_HOST_Read_Int
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int__INTC_NUMBER 69u
@ -844,7 +844,7 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int_INTC_NUMBER 69u
/* SDIO_HOST_sdio_int */
// SDIO_HOST_sdio_int
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int__INTC_NUMBER 122u
@ -852,7 +852,7 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int_INTC_NUMBER 122u
/* SDIO_HOST_Write_Int */
// SDIO_HOST_Write_Int
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int__INTC_NUMBER 67u
@ -860,10 +860,9 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int_INTC_NUMBER 67u
// ****************************SDIO Port**************************************
#define SDIO_HOST_GPIO_PORT GPIO_PRT12
#if defined(__cplusplus)
}
#endif
#endif /* !defined(CY_SDIO_CFG_H) */
/* [] END OF FILE */

1540
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c Normal file → Executable file
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106
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h Normal file → Executable file
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@ -1,29 +1,28 @@
/***************************************************************************//**
* \file SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/***********************************************************************************************//**
* \file COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
***************************************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#if !defined(CY_SDIO_CFG_H)
#define CY_SDIO_CFG_H
#pragma once
#include <string.h>
@ -95,10 +94,10 @@ extern "C" {
#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u
/*************Defines for UDBs from Creator*****************************/
/***********These come for cyfitter.h**********************************/
// *************Defines for UDBs from Creator*****************************
// ***********These come for cyfitter.h**********************************
/* TFT_DMA */
// TFT_DMA
#define TFT_DMA_DW__BLOCK_HW DW0
#define TFT_DMA_DW__BLOCK_NUMBER 0u
#define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2
@ -106,7 +105,7 @@ extern "C" {
#define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2
#define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2
/* TFT_CTRL */
// TFT_CTRL
#define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u
#define TFT_CTRL_Sync_ctrl_reg__0__POS 0
#define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u
@ -137,7 +136,7 @@ extern "C" {
#define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u
#define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u
/* SDIO_HOST */
// SDIO_HOST
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu
@ -830,75 +829,75 @@ extern "C" {
#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1
/***************************CMD DMA***************************************/
// ***************************CMD DMA***************************************
#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u)
#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_CMD_DMA_HW (DW0)
#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_CMD_DMA_PRIORITY (1u)
#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
/***************************Read DMA***************************************/
// ***************************Read DMA***************************************
#define SDIO_HOST_Read_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u)
#define SDIO_HOST_Read_DMA_HW (DW1)
#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Read_DMA_PRIORITY (0u)
#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Read_DMA_PREEMPTABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
/***************************Resp DMA***************************************/
// ***************************Resp DMA***************************************
#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u)
#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u)
#define SDIO_HOST_Resp_DMA_HW (DW0)
#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Resp_DMA_PRIORITY (1u)
#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
/***************************Write DMA***************************************/
// ***************************Write DMA***************************************
#define SDIO_HOST_Write_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_Write_DMA_HW (DW1)
#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Write_DMA_PRIORITY (0u)
#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Write_DMA_PREEMPTABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
/***************************SDIO Clock**************************************/
/* The peripheral clock divider number */
// ***************************SDIO Clock**************************************
// The peripheral clock divider number
#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0)
/* The peripheral clock divider type */
// The peripheral clock divider type
#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT)
/*Function for configuring TriggerMuxes*/
// Function for configuring TriggerMuxes
void SDIO_Host_Config_TriggerMuxes(void);
/*Function for configuring UDBs*/
// Function for configuring UDBs
void SDIO_Host_Config_UDBs(void);
/* SDIO_HOST_Read_Int */
// SDIO_HOST_Read_Int
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int__INTC_NUMBER 69u
@ -906,7 +905,7 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int_INTC_NUMBER 69u
/* SDIO_HOST_sdio_int */
// SDIO_HOST_sdio_int
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int__INTC_NUMBER 122u
@ -914,7 +913,7 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int_INTC_NUMBER 122u
/* SDIO_HOST_Write_Int */
// SDIO_HOST_Write_Int
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int__INTC_NUMBER 67u
@ -922,10 +921,9 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int_INTC_NUMBER 67u
// ****************************SDIO Port**************************************
#define SDIO_HOST_GPIO_PORT GPIO_PRT2
#if defined(__cplusplus)
}
#endif
#endif /* !defined(CY_SDIO_CFG_H) */
/* [] END OF FILE */

1669
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c Normal file → Executable file
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101
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h Normal file → Executable file
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@ -1,29 +1,28 @@
/***************************************************************************//**
* \file SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/***********************************************************************************************//**
* \file COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h
*
* \brief
* This file provides the configuration of the UDB based SDIO driver.
*
***************************************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#if !defined(CY_SDIO_CFG_H)
#define CY_SDIO_CFG_H
#pragma once
#include <string.h>
@ -95,10 +94,10 @@ extern "C" {
#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u
/*************Defines for UDBs from Creator*****************************/
/***********These come for cyfitter.h**********************************/
// *************Defines for UDBs from Creator*****************************
// ***********These come for cyfitter.h**********************************
/* SDIO_HOST_bSDIO */
// SDIO_HOST_bSDIO
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x40341008u
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x40341108u
#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x40341208u
@ -764,75 +763,76 @@ extern "C" {
#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1
/***************************CMD DMA***************************************/
// ***************************CMD DMA***************************************
#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u)
#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_CMD_DMA_HW (DW0)
#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_CMD_DMA_PRIORITY (1u)
#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc;
/***************************Read DMA***************************************/
// ***************************Read DMA***************************************
#define SDIO_HOST_Read_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u)
#define SDIO_HOST_Read_DMA_HW (DW1)
#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Read_DMA_PRIORITY (0u)
#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Read_DMA_PREEMPTABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc;
/***************************Resp DMA***************************************/
// ***************************Resp DMA***************************************
#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u)
#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u)
#define SDIO_HOST_Resp_DMA_HW (DW0)
#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Resp_DMA_PRIORITY (1u)
#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc;
/***************************Write DMA***************************************/
// ***************************Write DMA***************************************
#define SDIO_HOST_Write_DMA_DW_BLOCK (1u)
#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u)
#define SDIO_HOST_Write_DMA_HW (DW1)
#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK)
/* Channel settings */
// Channel settings
#define SDIO_HOST_Write_DMA_PRIORITY (0u)
#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u)
#define SDIO_HOST_Write_DMA_PREEMPTABLE (false)
extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
/***************************SDIO Clock**************************************/
// ***************************SDIO Clock**************************************
/** The peripheral clock divider number */
#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)SDIO_HOST_Internal_Clock__DIV_NUM)
/** The peripheral clock divider type */
#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE)
#define SDIO_HOST_Internal_Clock_DIV_TYPE \
((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE)
/*Function for configuring TriggerMuxes*/
// Function for configuring TriggerMuxes
void SDIO_Host_Config_TriggerMuxes(void);
/*Function for configuring UDBs*/
// Function for configuring UDBs
void SDIO_Host_Config_UDBs(void);
/* SDIO_HOST_Read_Int */
// SDIO_HOST_Read_Int
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int__INTC_NUMBER 69u
@ -840,7 +840,7 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Read_Int_INTC_NUMBER 69u
/* SDIO_HOST_sdio_int */
// SDIO_HOST_sdio_int
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int__INTC_NUMBER 122u
@ -848,7 +848,7 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_sdio_int_INTC_NUMBER 122u
/* SDIO_HOST_Write_Int */
// SDIO_HOST_Write_Int
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1
#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int__INTC_NUMBER 67u
@ -856,10 +856,9 @@ void SDIO_Host_Config_UDBs(void);
#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u
#define SDIO_HOST_Write_Int_INTC_NUMBER 67u
// ****************************SDIO Port**************************************
#define SDIO_HOST_GPIO_PORT GPIO_PRT9
#if defined(__cplusplus)
}
#endif
#endif /* !defined(CY_SDIO_CFG_H) */
/* [] END OF FILE */

165
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@ -0,0 +1,165 @@
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373
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.h Normal file → Executable file
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@ -1,59 +1,58 @@
/***************************************************************************//**
* \file SDIO_HOST.h
*
* \brief
* This file provides types definition, constants and function definition for
* the SDIO driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/***********************************************************************************************//**
* \file SDIO_HOST.h
*
* \brief
* This file provides types definition, constants and function definition for
* the SDIO driver.
*
***************************************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
/**
* \defgroup group_bsp_pin_state Pin States
* \defgroup group_bsp_pins Pin Mappings
* \defgroup group_bsp_macros Macros
* \defgroup group_bsp_functions Functions
*
* \defgroup group_udb_sdio UDB_SDIO
* \{
* SDIO - Secure Digital Input Output is a standard for communicating with various
* \defgroup group_bsp_pin_state Pin States
* \defgroup group_bsp_pins Pin Mappings
* \defgroup group_bsp_macros Macros
* \defgroup group_bsp_functions Functions
*
* \defgroup group_udb_sdio UDB_SDIO
* \{
* SDIO - Secure Digital Input Output is a standard for communicating with various
external devices such as Wifi and bluetooth devices.
* <p>
* The driver is currently designed to only support communication with certain
* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general
* SDIO card, or even and SD card. It is only intended to be used by the WiFi
* driver for communication.
* <p>
* This is not intended to be used as a general purpose API.
*
* \section group_udb_sdio_section_configuration_considerations Configuration Considerations
* Features:
* * Always Four Wire Mode
* * Supports Card Interrupt
* * Uses DMA for command and data transfer
*
* \defgroup group_udb_sdio_macros Macros
* \defgroup group_udb_sdio_functions Functions
* \defgroup group_udb_sdio_data_structures Data Structures
*/
* <p>
* The driver is currently designed to only support communication with certain
* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general
* SDIO card, or even and SD card. It is only intended to be used by the WiFi
* driver for communication.
* <p>
* This is not intended to be used as a general purpose API.
*
* \section group_udb_sdio_section_configuration_considerations Configuration Considerations
* Features:
* * Always Four Wire Mode
* * Supports Card Interrupt
* * Uses DMA for command and data transfer
*
* \defgroup group_udb_sdio_macros Macros
* \defgroup group_udb_sdio_functions Functions
* \defgroup group_udb_sdio_data_structures Data Structures
*/
#if !defined(CY_SDIO_H)
#define CY_SDIO_H
#pragma once
#if defined(CYHAL_UDB_SDIO)
#include "SDIO_HOST_cfg.h"
@ -63,23 +62,25 @@ extern "C" {
#endif
/***************************************
* API Constants
***************************************/
//==================================================================================================
// API Constants
//==================================================================================================
/**
* \addtogroup group_udb_sdio_macros
* \{
*/
* \addtogroup group_udb_sdio_macros
* \{
*/
#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/
#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/
#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/
#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/
#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/
#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/
#define SDIO_DAT_BUSY_TIMEOUT_MS (500u) /**< Value used for firmware timeout*/
#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/
#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7
bit counters*/
/*!
\defgroup group_sdio_cmd_constants Constants for the command channel
*/
\defgroup group_sdio_cmd_constants Constants for the command channel
*/
/* @{*/
#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */
#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/
@ -88,35 +89,41 @@ extern "C" {
/*@} group_sdio_cmd_constants */
/*!
\defgroup group_sdio_ctrl_reg SDIO control register bits
*/
\defgroup group_sdio_ctrl_reg SDIO control register bits
*/
/* @{*/
#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/
#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO
block*/
#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/
#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/
#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/
#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/
#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if
ENABLE_READ is set*/
#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if
ENABLE_WRITE is set*/
#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the
command*/
#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/
#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/
#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/
/*@} group_sdio_ctrl_reg */
/*!
\defgroup group_sdio_status_reg SDIO status register bits
*/
\defgroup group_sdio_status_reg SDIO status register bits
*/
/* @{*/
#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/
#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/
#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/
#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/
#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or
write*/
#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/
#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/
#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/
#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by
driving DAT[1] low*/
/*@} group_sdio_status_reg */
/*!
\defgroup group_sdio_crc Constants for 7bit CRC for command
*/
\defgroup group_sdio_crc Constants for 7bit CRC for command
*/
/* @{*/
#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/
#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/
@ -125,166 +132,168 @@ extern "C" {
/** \} group_udb_sdio_macros */
/***************************************
* Type Definitions
***************************************/
//==================================================================================================
// Type Definitions
//==================================================================================================
/**
* \addtogroup group_udb_sdio_data_structures
* \{
*/
* \addtogroup group_udb_sdio_data_structures
* \{
*/
/**
* Create a type for the card interrupt call back
*/
* Create a type for the card interrupt call back
*/
typedef void (* sdio_card_int_cb_t)(void);
/**
* \brief This enum is used when checking for specific events
*/
* \brief This enum is used when checking for specific events
*/
typedef enum en_sdio_event
{
SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/
SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/
}en_sdio_event_t;
SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/
SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/
} en_sdio_event_t;
/**
* \brief Used to indicate the result of a function
*/
* \brief Used to indicate the result of a function
*/
typedef enum en_sdio_result
{
Ok = 0x00, /**< No error*/
Error = 0x01, /**< Non-specific error code*/
CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/
CommandIdxError = 0x04, /**< The index for the command didn't match*/
CommandEndError = 0x08, /**< There was an end bit error on the command*/
DataCrcError = 0x10, /**< There was a data CRC Error*/
CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/
DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/
Ok = 0x00, /**< No error*/
Error = 0x01, /**< Non-specific error code*/
CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/
CommandIdxError = 0x04, /**< The index for the command didn't match*/
CommandEndError = 0x08, /**< There was an end bit error on the command*/
DataCrcError = 0x10, /**< There was a data CRC Error*/
CMDTimeout = 0x20, /**< The command didn't finish before the timeout period
was over*/
DataTimeout = 0x40, /**< The data didn't finish before the timeout period
was over*/
ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/
} en_sdio_result_t;
/**
* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function
*/
* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check
* events function
*/
typedef struct stc_sdcmd_event_flag
{
uint8_t u8CmdComplete; /**< If non-zero a command has completed*/
uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/
uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/
}stc_sdio_event_flag_t;
uint8_t u8CmdComplete; /**< If non-zero a command has completed*/
uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/
uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data
transfer*/
} stc_sdio_event_flag_t;
/**
* \brief Holds pointers to callback functions
*/
* \brief Holds pointers to callback functions
*/
typedef struct stc_sdio_irq_cb
{
sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/
}stc_sdio_irq_cb_t;
} stc_sdio_irq_cb_t;
/**
* \brief Global structure used to hold data from interrupt and other functions
*/
* \brief Global structure used to hold data from interrupt and other functions
*/
typedef struct stc_sdio_gInternalData
{
stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/
stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/
}stc_sdio_gInternalData_t;
stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/
stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in
interrupt used in check events*/
} stc_sdio_gInternalData_t;
/**
* \brief structure used for configuring command
*/
* \brief structure used for configuring command
*/
typedef struct stc_sdio_cmd_config
{
uint8_t u8CmdIndex; /**< Command index*/
uint32_t u32Argument; /**< The argument of command */
uint8_t bResponseRequired; /**< TRUE: A Response is required*/
uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/
}stc_sdio_cmd_config_t;
uint8_t u8CmdIndex; /**< Command index*/
uint32_t u32Argument; /**< The argument of command */
uint8_t bResponseRequired; /**< TRUE: A Response is required*/
uint8_t* pu8ResponseBuf; /**< Pointer to location to store response*/
} stc_sdio_cmd_config_t;
/**
* \brief structure used for the data channel
*/
* \brief structure used for the data channel
*/
typedef struct stc_sdio_data_config
{
uint8_t bRead; /**< TRUE: Read, FALSE: write*/
uint16_t u16BlockSize; /**< Block size*/
uint16_t u16BlockCount; /**< Holds the number of blocks to send*/
uint8_t *pu8Data; /**< Pointer data buffer*/
}stc_sdio_data_config_t;
uint8_t bRead; /**< TRUE: Read, FALSE: write*/
uint16_t u16BlockSize; /**< Block size*/
uint16_t u16BlockCount; /**< Holds the number of blocks to send*/
uint8_t* pu8Data; /**< Pointer data buffer*/
} stc_sdio_data_config_t;
/**
* \brief structure used for configuring command and data
*/
* \brief structure used for configuring command and data
*/
typedef struct stc_sdio_cmd
{
uint32_t u32CmdIdx; /**< Command index*/
uint32_t u32Arg; /**< The argument of command*/
uint32_t *pu32Response; /**< Pointer to location to store response*/
uint8_t *pu8Data; /**< Pointer data buffer*/
uint8_t bRead; /**< TRUE: Read, FALSE: write*/
uint16_t u16BlockCnt; /**< Number of blocks to send*/
uint16_t u16BlockSize; /**< Block size*/
}stc_sdio_cmd_t;
uint32_t u32CmdIdx; /**< Command index*/
uint32_t u32Arg; /**< The argument of command*/
uint32_t* pu32Response; /**< Pointer to location to store response*/
uint8_t* pu8Data; /**< Pointer data buffer*/
uint8_t bRead; /**< TRUE: Read, FALSE: write*/
uint16_t u16BlockCnt; /**< Number of blocks to send*/
uint16_t u16BlockSize; /**< Block size*/
} stc_sdio_cmd_t;
/** \} group_udb_sdio_data_structures */
/***************************************
* Function Prototypes
***************************************/
//==================================================================================================
// Function Prototypes
//==================================================================================================
/**
* \addtogroup group_udb_sdio_functions
* \{
*/
* \addtogroup group_udb_sdio_functions
* \{
*/
/* Main functions*/
void SDIO_Init(stc_sdio_irq_cb_t* pfuCb);
en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd);
void SDIO_EnableIntClock(void);
void SDIO_DisableIntClock(void);
void SDIO_EnableSdClk(void);
void SDIO_DisableSdClk(void);
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
void SDIO_Reset(void);
void SDIO_EnableChipInt(void);
void SDIO_DisableChipInt(void);
void SDIO_Free(void);
// Main functions
void SDIO_Init(stc_sdio_irq_cb_t* pfuCb);
en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t* pstcCmd);
void SDIO_EnableIntClock(void);
void SDIO_DisableIntClock(void);
void SDIO_EnableSdClk(void);
void SDIO_DisableSdClk(void);
void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
void SDIO_Reset(void);
void SDIO_EnableChipInt(void);
void SDIO_DisableChipInt(void);
void SDIO_Free(void);
/*Low Level Functions*/
void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig);
en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf);
void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig);
en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType);
uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size);
void SDIO_SetBlockSize(uint8_t u8ByteCount);
void SDIO_SetNumBlocks(uint8_t u8BlockCount);
// Low Level Functions
void SDIO_SendCommand(stc_sdio_cmd_config_t* pstcCmdConfig);
en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx,
uint32_t* pu32Response, uint8_t* pu8ResponseBuf);
void SDIO_InitDataTransfer(stc_sdio_data_config_t* pstcDataConfig);
en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType);
uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size);
void SDIO_SetBlockSize(uint8_t u8ByteCount);
void SDIO_SetNumBlocks(uint8_t u8BlockCount);
/*DMA setup function*/
void SDIO_SetupDMA(void);
// DMA setup function
void SDIO_SetupDMA(void);
/*Interrupt Function*/
void SDIO_IRQ(void);
void SDIO_READ_DMA_IRQ(void);
void SDIO_WRITE_DMA_IRQ(void);
// Interrupt Function
void SDIO_IRQ(void);
void SDIO_READ_DMA_IRQ(void);
void SDIO_WRITE_DMA_IRQ(void);
void SDIO_Crc7Init(void);
void SDIO_Crc7Init(void);
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode);
cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t* params,
cy_en_syspm_callback_mode_t mode);
/** \endcond */
/** \} group_udb_sdio_functions */
/***************************************
* Hardware Registers
***************************************/
//==================================================================================================
// Hardware Registers
//==================================================================================================
/** \cond INTERNAL */
@ -390,10 +399,6 @@ SDIO_HOST_bSDIO_byteCounter__PERIOD_REG)
}
#endif
#endif /* defined(CYHAL_UDB_SDIO) */
#endif /* (CY_SDIO_H) */
#endif // defined(CYHAL_UDB_SDIO)
/** \} group_udb_sdio */
/* [] END OF FILE */

1
targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/version.xml Executable file
View File

@ -0,0 +1 @@
<version>.19214</version>