From 9cd6dcabdc9d6981c02ff440a9e59b167eec0411 Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Tue, 1 Dec 2020 14:56:02 -0800 Subject: [PATCH] Update Cypress udb-sdio-whd to 1.1.0.19214 --- .../COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c | 1696 +++++++++-------- .../COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h | 101 +- .../COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c | 1540 ++++++++------- .../COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h | 106 +- .../COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c | 1669 ++++++++-------- .../COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h | 101 +- .../TARGET_PSOC6/common/udb-sdio-whd/LICENSE | 165 ++ .../common/udb-sdio-whd/SDIO_HOST.c | 1634 ++++++++-------- .../common/udb-sdio-whd/SDIO_HOST.h | 373 ++-- .../common/udb-sdio-whd/version.xml | 1 + 10 files changed, 3965 insertions(+), 3421 deletions(-) mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h create mode 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/LICENSE mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.c mode change 100644 => 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.h create mode 100755 targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/version.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c old mode 100644 new mode 100755 index e89c7c74b5..cdad190a89 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c @@ -1,26 +1,26 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.c -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.c + * + * \brief + * This file provides the configuration of the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #include "SDIO_HOST_cfg.h" @@ -53,11 +53,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -86,11 +86,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -119,11 +119,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -152,11 +152,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -180,9 +180,9 @@ cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") -#else +#else // if defined(__GNUC__) || defined(__ARMCC_VERSION) #error Unsupported toolchain -#endif +#endif // if defined(__GNUC__) || defined(__ARMCC_VERSION) #ifndef CYCODE @@ -194,27 +194,41 @@ cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); +static void CYMEMZERO(void* s, size_t n); CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYMEMZERO +//-------------------------------------------------------------------------------------------------- +static void CYMEMZERO(void* s, size_t n) { (void)memset(s, 0, n); } + + CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); +static void CYCONFIGCPY(void* dest, const void* src, size_t n); CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYCONFIGCPY +//-------------------------------------------------------------------------------------------------- +static void CYCONFIGCPY(void* dest, const void* src, size_t n) { (void)memcpy(dest, src, n); } + + CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +static void CYCONFIGCPYCODE(void* dest, const void* src, size_t n); CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYCONFIGCPYCODE +//-------------------------------------------------------------------------------------------------- +static void CYCONFIGCPYCODE(void* dest, const void* src, size_t n) { (void)memcpy(dest, src, n); } + CYPACKED typedef struct { uint8 offset; @@ -238,800 +252,912 @@ CYPACKED typedef struct *******************************************************************************/ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +//-------------------------------------------------------------------------------------------------- +// cfg_write_bytes32 +//-------------------------------------------------------------------------------------------------- static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) { - /* For 32-bit little-endian architectures */ + // For 32-bit little-endian architectures uint32 i, j = 0u; for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) { uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; + uint8 count = (uint8)baseAddr; baseAddr &= 0xFFFFFF00u; while (count != 0u) { - CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + CY_SET_REG8((void*)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } } } -static const uint32 CYCODE cy_cfg_addr_table[] = + +static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40340002u, /* Base address: 0x40340000 Count: 2 */ - 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ - 0x40340301u, /* Base address: 0x40340300 Count: 1 */ - 0x40340405u, /* Base address: 0x40340400 Count: 5 */ - 0x4034205Cu, /* Base address: 0x40342000 Count: 92 */ - 0x40342238u, /* Base address: 0x40342200 Count: 56 */ - 0x4034242Cu, /* Base address: 0x40342400 Count: 44 */ - 0x4034262Eu, /* Base address: 0x40342600 Count: 46 */ - 0x40342837u, /* Base address: 0x40342800 Count: 55 */ - 0x40342A29u, /* Base address: 0x40342A00 Count: 41 */ - 0x40347104u, /* Base address: 0x40347100 Count: 4 */ - 0x40347804u, /* Base address: 0x40347800 Count: 4 */ + 0x40340002u, // Base address: 0x40340000 Count: 2 + 0x4034010Au, // Base address: 0x40340100 Count: 10 + 0x40340301u, // Base address: 0x40340300 Count: 1 + 0x40340405u, // Base address: 0x40340400 Count: 5 + 0x4034205Cu, // Base address: 0x40342000 Count: 92 + 0x40342238u, // Base address: 0x40342200 Count: 56 + 0x4034242Cu, // Base address: 0x40342400 Count: 44 + 0x4034262Eu, // Base address: 0x40342600 Count: 46 + 0x40342837u, // Base address: 0x40342800 Count: 55 + 0x40342A29u, // Base address: 0x40342A00 Count: 41 + 0x40347104u, // Base address: 0x40347100 Count: 4 + 0x40347804u, // Base address: 0x40347800 Count: 4 }; -static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = +static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { -{0x00u, 0xFFu}, - {0x09u, 0x01u}, - {0x09u, 0x01u}, - {0x0Du, 0x02u}, - {0x10u, 0x10u}, - {0x14u, 0x88u}, - {0x18u, 0x10u}, - {0x1Cu, 0x88u}, - {0x20u, 0x10u}, - {0x24u, 0x88u}, - {0x28u, 0x10u}, - {0x2Cu, 0x88u}, - {0x19u, 0x40u}, - {0x10u, 0x07u}, - {0x18u, 0x47u}, - {0x24u, 0x03u}, - {0x28u, 0x0Fu}, - {0x2Cu, 0x2Fu}, - {0x00u, 0x01u}, - {0x0Eu, 0x0Eu}, - {0x10u, 0x08u}, - {0x18u, 0x01u}, - {0x1Au, 0x08u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x22u, 0x01u}, - {0x28u, 0x01u}, - {0x2Au, 0x04u}, - {0x2Eu, 0x01u}, - {0x30u, 0x0Fu}, - {0x3Cu, 0x02u}, - {0x40u, 0x63u}, - {0x41u, 0x04u}, - {0x42u, 0x10u}, - {0x44u, 0x02u}, - {0x45u, 0x0Fu}, - {0x46u, 0xECu}, - {0x47u, 0xB0u}, - {0x48u, 0x2Du}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x02u}, - {0x4Fu, 0x0Cu}, - {0x50u, 0x08u}, - {0x51u, 0x10u}, - {0x5Cu, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x65u, 0x08u}, - {0x68u, 0xC0u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x71u, 0x10u}, - {0x72u, 0x50u}, - {0x73u, 0xA8u}, - {0x81u, 0x01u}, - {0x83u, 0x02u}, - {0x85u, 0x02u}, - {0x89u, 0x02u}, - {0x8Du, 0x02u}, - {0x91u, 0x30u}, - {0x93u, 0x04u}, - {0x95u, 0x06u}, - {0x97u, 0x38u}, - {0x99u, 0x20u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x10u}, - {0x9Du, 0x06u}, - {0x9Fu, 0x38u}, - {0xA3u, 0x02u}, - {0xA5u, 0x02u}, - {0xA6u, 0x01u}, - {0xABu, 0x01u}, - {0xB1u, 0x01u}, - {0xB2u, 0x01u}, - {0xB3u, 0x20u}, - {0xB5u, 0x10u}, - {0xB7u, 0x0Eu}, - {0xBDu, 0x80u}, - {0xBEu, 0x04u}, - {0xBFu, 0x14u}, - {0xC0u, 0x54u}, - {0xC1u, 0x06u}, - {0xC2u, 0x32u}, - {0xC6u, 0xF0u}, - {0xC7u, 0x0Eu}, - {0xC8u, 0x18u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCFu, 0x2Fu}, - {0xD0u, 0x08u}, - {0xD1u, 0x10u}, - {0xDCu, 0x04u}, - {0xDDu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xDFu, 0x04u}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE6u, 0x08u}, - {0xE7u, 0x03u}, - {0xE8u, 0x08u}, - {0xEAu, 0x18u}, - {0xEBu, 0x03u}, - {0xF0u, 0x58u}, - {0xF1u, 0xECu}, - {0x00u, 0x18u}, - {0x01u, 0x15u}, - {0x03u, 0x20u}, - {0x04u, 0x43u}, - {0x06u, 0x34u}, - {0x07u, 0x35u}, - {0x08u, 0x40u}, - {0x0Cu, 0x5Au}, - {0x0Eu, 0x25u}, - {0x0Fu, 0x4Au}, - {0x11u, 0x20u}, - {0x13u, 0x15u}, - {0x14u, 0x40u}, - {0x15u, 0x40u}, - {0x17u, 0x0Au}, - {0x18u, 0x20u}, - {0x19u, 0x10u}, - {0x1Bu, 0x25u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x0Au}, - {0x1Fu, 0x40u}, - {0x20u, 0x20u}, - {0x21u, 0x0Cu}, - {0x23u, 0x03u}, - {0x24u, 0x40u}, - {0x2Au, 0x20u}, - {0x2Cu, 0x45u}, - {0x2Eu, 0x3Au}, - {0x30u, 0x40u}, - {0x32u, 0x0Eu}, - {0x33u, 0x70u}, - {0x34u, 0x01u}, - {0x35u, 0x0Cu}, - {0x36u, 0x31u}, - {0x37u, 0x03u}, - {0x3Au, 0xA8u}, - {0x3Cu, 0xA8u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x54u}, - {0x40u, 0x42u}, - {0x41u, 0x05u}, - {0x45u, 0x20u}, - {0x46u, 0x06u}, - {0x48u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Du, 0xA0u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x66u, 0x40u}, - {0x67u, 0x40u}, - {0x68u, 0x10u}, - {0x69u, 0x50u}, - {0x02u, 0x60u}, - {0x08u, 0x87u}, - {0x0Au, 0x78u}, - {0x0Eu, 0x08u}, - {0x12u, 0x21u}, - {0x14u, 0x04u}, - {0x18u, 0xB9u}, - {0x1Au, 0x06u}, - {0x1Cu, 0x89u}, - {0x1Eu, 0x72u}, - {0x20u, 0x04u}, - {0x24u, 0x8Eu}, - {0x26u, 0x51u}, - {0x2Au, 0x04u}, - {0x2Eu, 0x01u}, - {0x30u, 0x80u}, - {0x34u, 0x7Fu}, - {0x3Au, 0x20u}, - {0x3Cu, 0x20u}, - {0x3Eu, 0x01u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x44u, 0x01u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x77u}, - {0x5Cu, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x80u, 0x40u}, - {0x84u, 0x8Eu}, - {0x86u, 0x71u}, - {0x88u, 0x40u}, - {0x8Eu, 0x21u}, - {0x90u, 0x40u}, - {0x92u, 0x02u}, - {0x96u, 0x18u}, - {0x98u, 0x03u}, - {0x9Au, 0x04u}, - {0x9Cu, 0xCCu}, - {0x9Eu, 0x33u}, - {0xA0u, 0x08u}, - {0xA4u, 0x40u}, - {0xA8u, 0x46u}, - {0xAAu, 0xB1u}, - {0xACu, 0x10u}, - {0xAEu, 0x08u}, - {0xB2u, 0xF8u}, - {0xB4u, 0x07u}, - {0xB6u, 0x07u}, - {0xBAu, 0xA8u}, - {0xBCu, 0xA8u}, - {0xC0u, 0x43u}, - {0xC1u, 0x02u}, - {0xC4u, 0x01u}, - {0xC5u, 0x40u}, - {0xC6u, 0xB0u}, - {0xC8u, 0x0Au}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x00u, 0x40u}, - {0x01u, 0x14u}, - {0x03u, 0x20u}, - {0x04u, 0x33u}, - {0x05u, 0x3Cu}, - {0x06u, 0x44u}, - {0x08u, 0x97u}, - {0x09u, 0x3Cu}, - {0x0Au, 0x48u}, - {0x0Du, 0x01u}, - {0x11u, 0x03u}, - {0x12u, 0x91u}, - {0x15u, 0x03u}, - {0x16u, 0x08u}, - {0x1Bu, 0x03u}, - {0x1Cu, 0x13u}, - {0x1Eu, 0xECu}, - {0x1Fu, 0x03u}, - {0x20u, 0xADu}, - {0x21u, 0x04u}, - {0x22u, 0x52u}, - {0x27u, 0x2Cu}, - {0x29u, 0x02u}, - {0x2Eu, 0x12u}, - {0x2Fu, 0x04u}, - {0x30u, 0x07u}, - {0x31u, 0x18u}, - {0x33u, 0x07u}, - {0x34u, 0xF8u}, - {0x35u, 0x20u}, - {0x39u, 0x02u}, - {0x3Au, 0x22u}, - {0x3Cu, 0x22u}, - {0x3Fu, 0x15u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x01u, 0x20u}, - {0x0Bu, 0x40u}, - {0x0Du, 0x10u}, - {0x11u, 0x32u}, - {0x13u, 0x09u}, - {0x15u, 0x0Au}, - {0x17u, 0x31u}, - {0x23u, 0x34u}, - {0x29u, 0x33u}, - {0x2Bu, 0x08u}, - {0x2Du, 0x0Cu}, - {0x31u, 0x0Cu}, - {0x33u, 0x01u}, - {0x35u, 0x02u}, - {0x37u, 0x70u}, - {0x39u, 0x02u}, - {0x3Fu, 0x55u}, - {0x40u, 0x16u}, - {0x41u, 0x02u}, - {0x44u, 0x04u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x76u}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0xE8u, 0x63u}, - {0xECu, 0x53u}, - {0xF0u, 0x54u}, - {0xF4u, 0x01u}, - {0x00u, 0x01u}, - {0x10u, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x01u}, + { 0x00u, 0xFFu }, + { 0x09u, 0x01u }, + { 0x09u, 0x01u }, + { 0x0Du, 0x02u }, + { 0x10u, 0x10u }, + { 0x14u, 0x88u }, + { 0x18u, 0x10u }, + { 0x1Cu, 0x88u }, + { 0x20u, 0x10u }, + { 0x24u, 0x88u }, + { 0x28u, 0x10u }, + { 0x2Cu, 0x88u }, + { 0x19u, 0x40u }, + { 0x10u, 0x07u }, + { 0x18u, 0x47u }, + { 0x24u, 0x03u }, + { 0x28u, 0x0Fu }, + { 0x2Cu, 0x2Fu }, + { 0x00u, 0x01u }, + { 0x0Eu, 0x0Eu }, + { 0x10u, 0x08u }, + { 0x18u, 0x01u }, + { 0x1Au, 0x08u }, + { 0x1Cu, 0x01u }, + { 0x1Eu, 0x02u }, + { 0x22u, 0x01u }, + { 0x28u, 0x01u }, + { 0x2Au, 0x04u }, + { 0x2Eu, 0x01u }, + { 0x30u, 0x0Fu }, + { 0x3Cu, 0x02u }, + { 0x40u, 0x63u }, + { 0x41u, 0x04u }, + { 0x42u, 0x10u }, + { 0x44u, 0x02u }, + { 0x45u, 0x0Fu }, + { 0x46u, 0xECu }, + { 0x47u, 0xB0u }, + { 0x48u, 0x2Du }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x02u }, + { 0x4Fu, 0x0Cu }, + { 0x50u, 0x08u }, + { 0x51u, 0x10u }, + { 0x5Cu, 0x0Cu }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x65u, 0x08u }, + { 0x68u, 0xC0u }, + { 0x6Cu, 0x10u }, + { 0x6Du, 0x11u }, + { 0x6Eu, 0x40u }, + { 0x6Fu, 0x01u }, + { 0x71u, 0x10u }, + { 0x72u, 0x50u }, + { 0x73u, 0xA8u }, + { 0x81u, 0x01u }, + { 0x83u, 0x02u }, + { 0x85u, 0x02u }, + { 0x89u, 0x02u }, + { 0x8Du, 0x02u }, + { 0x91u, 0x30u }, + { 0x93u, 0x04u }, + { 0x95u, 0x06u }, + { 0x97u, 0x38u }, + { 0x99u, 0x20u }, + { 0x9Au, 0x01u }, + { 0x9Bu, 0x10u }, + { 0x9Du, 0x06u }, + { 0x9Fu, 0x38u }, + { 0xA3u, 0x02u }, + { 0xA5u, 0x02u }, + { 0xA6u, 0x01u }, + { 0xABu, 0x01u }, + { 0xB1u, 0x01u }, + { 0xB2u, 0x01u }, + { 0xB3u, 0x20u }, + { 0xB5u, 0x10u }, + { 0xB7u, 0x0Eu }, + { 0xBDu, 0x80u }, + { 0xBEu, 0x04u }, + { 0xBFu, 0x14u }, + { 0xC0u, 0x54u }, + { 0xC1u, 0x06u }, + { 0xC2u, 0x32u }, + { 0xC6u, 0xF0u }, + { 0xC7u, 0x0Eu }, + { 0xC8u, 0x18u }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCFu, 0x2Fu }, + { 0xD0u, 0x08u }, + { 0xD1u, 0x10u }, + { 0xDCu, 0x04u }, + { 0xDDu, 0x0Cu }, + { 0xDEu, 0x0Cu }, + { 0xDFu, 0x04u }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE6u, 0x08u }, + { 0xE7u, 0x03u }, + { 0xE8u, 0x08u }, + { 0xEAu, 0x18u }, + { 0xEBu, 0x03u }, + { 0xF0u, 0x58u }, + { 0xF1u, 0xECu }, + { 0x00u, 0x18u }, + { 0x01u, 0x15u }, + { 0x03u, 0x20u }, + { 0x04u, 0x43u }, + { 0x06u, 0x34u }, + { 0x07u, 0x35u }, + { 0x08u, 0x40u }, + { 0x0Cu, 0x5Au }, + { 0x0Eu, 0x25u }, + { 0x0Fu, 0x4Au }, + { 0x11u, 0x20u }, + { 0x13u, 0x15u }, + { 0x14u, 0x40u }, + { 0x15u, 0x40u }, + { 0x17u, 0x0Au }, + { 0x18u, 0x20u }, + { 0x19u, 0x10u }, + { 0x1Bu, 0x25u }, + { 0x1Cu, 0x40u }, + { 0x1Du, 0x0Au }, + { 0x1Fu, 0x40u }, + { 0x20u, 0x20u }, + { 0x21u, 0x0Cu }, + { 0x23u, 0x03u }, + { 0x24u, 0x40u }, + { 0x2Au, 0x20u }, + { 0x2Cu, 0x45u }, + { 0x2Eu, 0x3Au }, + { 0x30u, 0x40u }, + { 0x32u, 0x0Eu }, + { 0x33u, 0x70u }, + { 0x34u, 0x01u }, + { 0x35u, 0x0Cu }, + { 0x36u, 0x31u }, + { 0x37u, 0x03u }, + { 0x3Au, 0xA8u }, + { 0x3Cu, 0xA8u }, + { 0x3Eu, 0x01u }, + { 0x3Fu, 0x54u }, + { 0x40u, 0x42u }, + { 0x41u, 0x05u }, + { 0x45u, 0x20u }, + { 0x46u, 0x06u }, + { 0x48u, 0x06u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Du, 0xA0u }, + { 0x5Cu, 0x0Cu }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x66u, 0x40u }, + { 0x67u, 0x40u }, + { 0x68u, 0x10u }, + { 0x69u, 0x50u }, + { 0x02u, 0x60u }, + { 0x08u, 0x87u }, + { 0x0Au, 0x78u }, + { 0x0Eu, 0x08u }, + { 0x12u, 0x21u }, + { 0x14u, 0x04u }, + { 0x18u, 0xB9u }, + { 0x1Au, 0x06u }, + { 0x1Cu, 0x89u }, + { 0x1Eu, 0x72u }, + { 0x20u, 0x04u }, + { 0x24u, 0x8Eu }, + { 0x26u, 0x51u }, + { 0x2Au, 0x04u }, + { 0x2Eu, 0x01u }, + { 0x30u, 0x80u }, + { 0x34u, 0x7Fu }, + { 0x3Au, 0x20u }, + { 0x3Cu, 0x20u }, + { 0x3Eu, 0x01u }, + { 0x40u, 0x43u }, + { 0x41u, 0x02u }, + { 0x44u, 0x01u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x57u, 0x02u }, + { 0x58u, 0x77u }, + { 0x5Cu, 0x0Cu }, + { 0x5Eu, 0x0Cu }, + { 0x5Fu, 0x0Cu }, + { 0x62u, 0x08u }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0x80u, 0x40u }, + { 0x84u, 0x8Eu }, + { 0x86u, 0x71u }, + { 0x88u, 0x40u }, + { 0x8Eu, 0x21u }, + { 0x90u, 0x40u }, + { 0x92u, 0x02u }, + { 0x96u, 0x18u }, + { 0x98u, 0x03u }, + { 0x9Au, 0x04u }, + { 0x9Cu, 0xCCu }, + { 0x9Eu, 0x33u }, + { 0xA0u, 0x08u }, + { 0xA4u, 0x40u }, + { 0xA8u, 0x46u }, + { 0xAAu, 0xB1u }, + { 0xACu, 0x10u }, + { 0xAEu, 0x08u }, + { 0xB2u, 0xF8u }, + { 0xB4u, 0x07u }, + { 0xB6u, 0x07u }, + { 0xBAu, 0xA8u }, + { 0xBCu, 0xA8u }, + { 0xC0u, 0x43u }, + { 0xC1u, 0x02u }, + { 0xC4u, 0x01u }, + { 0xC5u, 0x40u }, + { 0xC6u, 0xB0u }, + { 0xC8u, 0x0Au }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCCu, 0x13u }, + { 0xCDu, 0x5Cu }, + { 0xCEu, 0x77u }, + { 0xDCu, 0x0Cu }, + { 0xDEu, 0x0Cu }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE9u, 0x1Cu }, + { 0xEAu, 0x58u }, + { 0xEBu, 0xA1u }, + { 0xEDu, 0x10u }, + { 0xF0u, 0x10u }, + { 0xF1u, 0x1Du }, + { 0x00u, 0x40u }, + { 0x01u, 0x14u }, + { 0x03u, 0x20u }, + { 0x04u, 0x33u }, + { 0x05u, 0x3Cu }, + { 0x06u, 0x44u }, + { 0x08u, 0x97u }, + { 0x09u, 0x3Cu }, + { 0x0Au, 0x48u }, + { 0x0Du, 0x01u }, + { 0x11u, 0x03u }, + { 0x12u, 0x91u }, + { 0x15u, 0x03u }, + { 0x16u, 0x08u }, + { 0x1Bu, 0x03u }, + { 0x1Cu, 0x13u }, + { 0x1Eu, 0xECu }, + { 0x1Fu, 0x03u }, + { 0x20u, 0xADu }, + { 0x21u, 0x04u }, + { 0x22u, 0x52u }, + { 0x27u, 0x2Cu }, + { 0x29u, 0x02u }, + { 0x2Eu, 0x12u }, + { 0x2Fu, 0x04u }, + { 0x30u, 0x07u }, + { 0x31u, 0x18u }, + { 0x33u, 0x07u }, + { 0x34u, 0xF8u }, + { 0x35u, 0x20u }, + { 0x39u, 0x02u }, + { 0x3Au, 0x22u }, + { 0x3Cu, 0x22u }, + { 0x3Fu, 0x15u }, + { 0x40u, 0x43u }, + { 0x41u, 0x02u }, + { 0x44u, 0x06u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x5Cu, 0x0Cu }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0x01u, 0x20u }, + { 0x0Bu, 0x40u }, + { 0x0Du, 0x10u }, + { 0x11u, 0x32u }, + { 0x13u, 0x09u }, + { 0x15u, 0x0Au }, + { 0x17u, 0x31u }, + { 0x23u, 0x34u }, + { 0x29u, 0x33u }, + { 0x2Bu, 0x08u }, + { 0x2Du, 0x0Cu }, + { 0x31u, 0x0Cu }, + { 0x33u, 0x01u }, + { 0x35u, 0x02u }, + { 0x37u, 0x70u }, + { 0x39u, 0x02u }, + { 0x3Fu, 0x55u }, + { 0x40u, 0x16u }, + { 0x41u, 0x02u }, + { 0x44u, 0x04u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x57u, 0x02u }, + { 0x58u, 0x76u }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x5Fu, 0x0Cu }, + { 0x62u, 0x08u }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0xE8u, 0x63u }, + { 0xECu, 0x53u }, + { 0xF0u, 0x54u }, + { 0xF4u, 0x01u }, + { 0x00u, 0x01u }, + { 0x10u, 0x01u }, + { 0x14u, 0x01u }, + { 0x18u, 0x01u }, }; -CYPACKED typedef struct +CYPACKED typedef struct { -void *address; -uint16 size; + void* address; + uint16 size; } CYPACKED_ATTR cfg_memset_t; -CYPACKED typedef struct +CYPACKED typedef struct { - void *dest; - const void *src; - size_t size; + void* dest; + const void* src; + size_t size; } CYPACKED_ATTR cfg_memcpy_t; -static const cfg_memset_t CYCODE cfg_memset_list[] = +static const cfg_memset_t CYCODE cfg_memset_list[] = { - /* address, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, + // address, size + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u }, }; -/* UDB_UDBPAIR5_UDBSNG1 Address: CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_UDBSNG1_VAL[] = { - 0x08u, 0x00u, 0x00u, 0x00u, 0x42u, 0x00u, 0x2Du, 0x00u, 0x08u, 0x24u, 0x00u, 0x00u, 0x22u, 0x24u, 0x45u, 0x00u, - 0x00u, 0x10u, 0x10u, 0x08u, 0x00u, 0x70u, 0x00u, 0x83u, 0x08u, 0x24u, 0x00u, 0x00u, 0x00u, 0x4Eu, 0x00u, 0xB0u, - 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x8Fu, 0x3Cu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, - 0x00u, 0xC0u, 0x00u, 0x1Fu, 0x60u, 0x00u, 0x1Fu, 0x20u, 0x80u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x10u, 0x41u, - 0x46u, 0x02u, 0x00u, 0x00u, 0x05u, 0x00u, 0x04u, 0x0Bu, 0x14u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = { - 0x08u, 0x0Au, 0x00u, 0xD0u, 0x02u, 0xB9u, 0x00u, 0x42u, 0x2Bu, 0x02u, 0x00u, 0x00u, 0x2Bu, 0x00u, 0x54u, 0x80u, - 0x2Au, 0x00u, 0x01u, 0x20u, 0x40u, 0x33u, 0x00u, 0xCCu, 0x04u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0xA0u, - 0x2Au, 0x00u, 0x00u, 0x00u, 0x01u, 0x8Au, 0x2Au, 0x71u, 0x20u, 0x7Bu, 0x00u, 0x80u, 0x00u, 0x04u, 0x00u, 0x00u, - 0x19u, 0xF8u, 0x07u, 0xF8u, 0x00u, 0x00u, 0x61u, 0x07u, 0x8Au, 0x80u, 0x00u, 0x0Au, 0x00u, 0x0Au, 0x45u, 0x40u, - 0x52u, 0x06u, 0x00u, 0x00u, 0x04u, 0x4Cu, 0x0Eu, 0x00u, 0x07u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, - 0x40u, 0x03u, 0x00u, 0x10u}; - -/* UDB_UDBPAIR4_UDBSNG1 Address: CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x00u, 0x19u, 0x00u, 0x12u, 0x00u, 0x2Du, 0x00u, 0x04u, 0x00u, 0x00u, 0x11u, - 0x02u, 0x08u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x05u, 0x00u, 0x03u, 0x10u, 0x08u, - 0x15u, 0x00u, 0x2Au, 0x10u, 0x00u, 0x00u, 0x04u, 0x00u, 0x0Eu, 0x0Fu, 0x31u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x07u, 0x00u, 0x10u, 0x3Fu, 0x00u, 0x3Fu, 0x0Cu, 0x00u, 0x00u, 0xA0u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x04u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x06u, 0x40u, 0xB0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR3_UDBSNG0 Address: CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG0_VAL[] = { - 0x3Cu, 0x00u, 0x00u, 0xC0u, 0x00u, 0x80u, 0x10u, 0x40u, 0x0Cu, 0x80u, 0x60u, 0x40u, 0x02u, 0x10u, 0x00u, 0x25u, - 0x04u, 0x80u, 0x08u, 0x40u, 0x00u, 0x19u, 0x10u, 0x22u, 0x04u, 0x00u, 0x0Bu, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x80u, - 0x10u, 0x00u, 0x00u, 0x24u, 0x00u, 0x40u, 0x00u, 0x80u, 0x7Cu, 0x25u, 0x00u, 0x1Au, 0x00u, 0x08u, 0x10u, 0x80u, - 0x01u, 0xC0u, 0x02u, 0x00u, 0x70u, 0x07u, 0x0Cu, 0x38u, 0x00u, 0x00u, 0x80u, 0x82u, 0x00u, 0xA2u, 0x04u, 0x00u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xDEu, 0x40u, 0x4Bu, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR2_UDBSNG1 Address: CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x80u, 0x03u, 0x00u, 0xC9u, 0x00u, 0x12u, 0x00u, 0x00u, 0x00u, 0x01u, 0x70u, 0x01u, 0x00u, 0x80u, - 0x40u, 0x00u, 0x00u, 0x40u, 0x40u, 0xB3u, 0xAAu, 0x4Cu, 0xEAu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x40u, - 0x40u, 0xB1u, 0xAAu, 0x04u, 0x43u, 0x00u, 0x00u, 0x01u, 0x4Cu, 0x05u, 0x00u, 0xBAu, 0x00u, 0x20u, 0x40u, 0x80u, - 0x03u, 0x7Fu, 0xC0u, 0x80u, 0x0Cu, 0x7Fu, 0x30u, 0x00u, 0xA2u, 0x00u, 0x08u, 0x22u, 0x08u, 0x22u, 0x51u, 0x04u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x05u, 0xB0u, 0x40u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = { - 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF5u, 0x7Fu, 0xF3u, 0x11u, - 0xF3u, 0x11u, 0xFFu, 0xF2u, 0xFFu, 0x2Fu, 0xFFu, 0xFFu, 0x00u, 0x11u, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF7u, 0x5Fu, 0xFFu, 0x2Fu, 0x10u, 0x22u, 0x62u, 0x00u, 0x34u, - 0x2Fu, 0x62u, 0x73u, 0x00u, 0x11u, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x0Fu, 0x0Fu, 0x27u, - 0x20u, 0x22u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x11u, 0x40u, 0x1Du, 0x11u, 0x00u, 0xDDu, 0x11u, 0x10u, 0x10u, 0x11u, 0x00u, 0xD1u, 0x63u, 0x03u, 0x01u, - 0x13u, 0x37u, 0x00u, 0x13u, 0x11u, 0x00u, 0x13u, 0x16u, 0x11u, 0x11u, 0x16u, 0x19u, 0x11u, 0x01u, 0x11u, 0x11u, - 0x19u, 0x11u, 0x11u, 0x91u, 0x41u, 0x11u, 0x21u, 0x11u, 0x16u, 0x11u, 0x11u, 0x13u, 0x81u, 0x11u, 0x11u, 0x11u}; - -/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = { - 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x42u, 0x36u, - 0x26u, 0x33u, 0x35u, 0xF5u, 0xF0u, 0x54u, 0x14u, 0x62u, 0x5Fu, 0x0Fu, 0x04u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x24u, 0x45u, 0x7Fu, 0x50u, 0x26u, 0x64u, 0xFFu, 0x3Fu, 0x32u, 0x42u, 0xF3u, 0x32u, - 0x3Fu, 0x7Fu, 0x37u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x02u, 0x05u, - 0xF6u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x13u, 0xF0u, 0x10u, 0x14u, 0x00u, 0x01u, 0x01u, 0x10u, 0x0Du, 0x63u, 0x00u, 0x70u, 0x10u, 0x08u, 0x30u, - 0x13u, 0x11u, 0x30u, 0x10u, 0x50u, 0x30u, 0x1Fu, 0xC1u, 0x33u, 0x10u, 0x0Fu, 0x01u, 0x31u, 0x0Du, 0x1Cu, 0x25u, - 0x11u, 0x01u, 0x12u, 0xFBu, 0x02u, 0x12u, 0x15u, 0x1Cu, 0x11u, 0x11u, 0x11u, 0x15u, 0x11u, 0x61u, 0x16u, 0x11u}; - -/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = { - 0x06u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, 0x33u, 0x35u, 0x44u, - 0x77u, 0x57u, 0xF2u, 0xFFu, 0xF4u, 0xFFu, 0x40u, 0xFFu, 0x32u, 0x63u, 0xFFu, 0xFFu, 0x3Fu, 0x5Fu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x34u, 0x13u, 0x46u, 0x56u, 0x35u, 0x41u, 0x40u, 0x57u, 0x67u, 0x55u, - 0x3Fu, 0x63u, 0xF6u, 0xFFu, 0x4Fu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x00u, 0x00u, - 0x40u, 0x22u, 0x00u, 0xF0u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x11u, 0xF3u, 0x10u, 0x12u, 0x02u, 0x96u, 0x01u, 0x00u, 0x74u, 0xD1u, 0x00u, 0xF7u, 0x03u, 0x03u, 0x16u, - 0x1Fu, 0x31u, 0x10u, 0x00u, 0x03u, 0x10u, 0x41u, 0x35u, 0x10u, 0x16u, 0x0Fu, 0x76u, 0x11u, 0xB0u, 0xD1u, 0xDFu, - 0x09u, 0x00u, 0x0Fu, 0xFBu, 0x01u, 0x11u, 0x17u, 0x11u, 0x11u, 0x15u, 0xD5u, 0x1Du, 0x27u, 0x15u, 0x1Fu, 0x11u}; - -/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x41u, 0x53u, 0x15u, - 0x45u, 0x11u, 0xF4u, 0xF3u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0x33u, 0x63u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x31u, 0x02u, 0x14u, 0x56u, 0xF1u, 0x77u, 0x77u, 0x37u, 0xF0u, 0x56u, 0x73u, 0x45u, - 0x33u, 0x63u, 0xFFu, 0x03u, 0x15u, 0xF2u, 0xF2u, 0xF2u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xB0u, 0x00u, 0xF0u, 0x17u, 0x1Fu, 0x02u, 0x1Fu, 0x60u, 0xA3u, 0xF4u, 0x15u, 0xA0u, 0xF1u, 0x0Fu, 0x00u, 0x31u, - 0x0Fu, 0xF3u, 0x3Au, 0x20u, 0x51u, 0x3Au, 0x13u, 0xF3u, 0xC0u, 0x10u, 0x4Au, 0x11u, 0x20u, 0x10u, 0x01u, 0xF1u, - 0x0Fu, 0x00u, 0x0Fu, 0xFFu, 0x41u, 0x11u, 0x41u, 0x4Du, 0x11u, 0x71u, 0x11u, 0x1Fu, 0xFCu, 0x11u, 0x1Fu, 0x1Cu}; - -/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = { - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, 0xF4u, 0x55u, 0x4Fu, - 0xF3u, 0x5Fu, 0x55u, 0x27u, 0x31u, 0x63u, 0x71u, 0x61u, 0x3Fu, 0x63u, 0x0Fu, 0x5Fu, 0xFFu, 0xFFu, 0xFFu, 0x12u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x64u, 0x31u, 0x70u, 0x77u, 0xF6u, 0x2Fu, 0x1Fu, 0x25u, 0x4Fu, 0xF7u, 0x3Fu, - 0x32u, 0x63u, 0x3Fu, 0x75u, 0xF4u, 0x1Fu, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, - 0x04u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x70u, 0x30u, 0x26u, 0x14u, 0x2Fu, 0x0Cu, 0xA5u, 0x10u, 0x18u, 0x11u, 0x0Fu, 0xF0u, 0xF7u, 0x3Fu, 0x00u, 0x11u, - 0x0Fu, 0xFFu, 0xF8u, 0x16u, 0xF7u, 0x1Fu, 0x10u, 0x11u, 0xF4u, 0x13u, 0xFFu, 0x67u, 0x13u, 0x15u, 0x07u, 0xF1u, - 0x3Fu, 0xCDu, 0x2Fu, 0x4Fu, 0xF6u, 0x12u, 0x12u, 0x11u, 0x11u, 0x19u, 0x11u, 0x21u, 0xFFu, 0x11u, 0x1Fu, 0x11u}; - -/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x32u, 0xF3u, 0xF4u, - 0xFFu, 0x45u, 0xFFu, 0x43u, 0x12u, 0x35u, 0x33u, 0xFFu, 0x3Fu, 0x5Fu, 0x34u, 0xF0u, 0xFFu, 0x2Fu, 0xFFu, 0x12u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0xF3u, 0xFFu, 0x44u, 0x1Fu, 0xF2u, 0x04u, 0x01u, 0x2Fu, - 0x30u, 0x2Fu, 0x3Fu, 0xFFu, 0xF0u, 0x10u, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xF5u, 0x17u, 0x11u, 0x16u, 0x11u, 0x2Cu, 0x1Fu, 0x17u, 0x9Fu, 0x41u, 0x6Fu, 0xF4u, 0x1Fu, 0x33u, 0xCCu, 0x11u, - 0x63u, 0x1Fu, 0x29u, 0x71u, 0xF5u, 0x2Fu, 0x73u, 0x13u, 0xF1u, 0x13u, 0x11u, 0x1Au, 0x11u, 0x31u, 0x6Fu, 0x11u, - 0x11u, 0x1Fu, 0x11u, 0x1Au, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI0_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI2_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI3_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x15u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI4_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI5_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI6_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x09u, 0x1Fu, - 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0x03u, 0xFFu, 0xF0u, 0xFFu, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x01u, 0x11u, - 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x10u, 0xD1u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI7_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x04u, 0x12u, 0x10u, 0x0Du, 0x1Fu, 0x1Fu, 0x10u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0xFFu, 0x0Fu, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x0Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x21u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI8_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x20u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI9_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI10_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI11_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), BS_UDB_UDBPAIR5_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), BS_UDB_UDBPAIR4_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), BS_UDB_UDBPAIR3_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), BS_UDB_UDBPAIR2_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, +// UDB_UDBPAIR5_UDBSNG1 Address: CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR5_UDBSNG1_VAL[] = +{ + 0x08u, 0x00u, 0x00u, 0x00u, 0x42u, 0x00u, 0x2Du, 0x00u, 0x08u, 0x24u, 0x00u, 0x00u, 0x22u, + 0x24u, 0x45u, 0x00u, 0x00u, 0x10u, 0x10u, 0x08u, 0x00u, 0x70u, 0x00u, 0x83u, 0x08u, 0x24u, + 0x00u, 0x00u, 0x00u, 0x4Eu, 0x00u, 0xB0u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, + 0x8Fu, 0x3Cu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x1Fu, + 0x60u, 0x00u, 0x1Fu, 0x20u, 0x80u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x10u, 0x41u, 0x46u, + 0x02u, 0x00u, 0x00u, 0x05u, 0x00u, 0x04u, 0x0Bu, 0x14u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u }; +// UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = +{ + 0x08u, 0x0Au, 0x00u, 0xD0u, 0x02u, 0xB9u, 0x00u, 0x42u, 0x2Bu, 0x02u, 0x00u, 0x00u, 0x2Bu, + 0x00u, 0x54u, 0x80u, 0x2Au, 0x00u, 0x01u, 0x20u, 0x40u, 0x33u, 0x00u, 0xCCu, 0x04u, 0x00u, + 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0xA0u, 0x2Au, 0x00u, 0x00u, 0x00u, 0x01u, 0x8Au, 0x2Au, + 0x71u, 0x20u, 0x7Bu, 0x00u, 0x80u, 0x00u, 0x04u, 0x00u, 0x00u, 0x19u, 0xF8u, 0x07u, 0xF8u, + 0x00u, 0x00u, 0x61u, 0x07u, 0x8Au, 0x80u, 0x00u, 0x0Au, 0x00u, 0x0Au, 0x45u, 0x40u, 0x52u, + 0x06u, 0x00u, 0x00u, 0x04u, 0x4Cu, 0x0Eu, 0x00u, 0x07u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, + 0x00u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, + 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, 0x40u, 0x03u, 0x00u, 0x10u +}; + +// UDB_UDBPAIR4_UDBSNG1 Address: CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x00u, 0x19u, 0x00u, 0x12u, 0x00u, 0x2Du, 0x00u, 0x04u, + 0x00u, 0x00u, 0x11u, 0x02u, 0x08u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x05u, 0x00u, 0x03u, 0x10u, 0x08u, 0x15u, 0x00u, 0x2Au, 0x10u, 0x00u, 0x00u, 0x04u, + 0x00u, 0x0Eu, 0x0Fu, 0x31u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, 0x00u, 0x10u, + 0x3Fu, 0x00u, 0x3Fu, 0x0Cu, 0x00u, 0x00u, 0xA0u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x04u, 0x43u, + 0x02u, 0x00u, 0x00u, 0x06u, 0x40u, 0xB0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u +}; + +// UDB_UDBPAIR3_UDBSNG0 Address: CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG0_VAL[] = +{ + 0x3Cu, 0x00u, 0x00u, 0xC0u, 0x00u, 0x80u, 0x10u, 0x40u, 0x0Cu, 0x80u, 0x60u, 0x40u, 0x02u, + 0x10u, 0x00u, 0x25u, 0x04u, 0x80u, 0x08u, 0x40u, 0x00u, 0x19u, 0x10u, 0x22u, 0x04u, 0x00u, + 0x0Bu, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x80u, 0x10u, 0x00u, 0x00u, 0x24u, 0x00u, 0x40u, 0x00u, + 0x80u, 0x7Cu, 0x25u, 0x00u, 0x1Au, 0x00u, 0x08u, 0x10u, 0x80u, 0x01u, 0xC0u, 0x02u, 0x00u, + 0x70u, 0x07u, 0x0Cu, 0x38u, 0x00u, 0x00u, 0x80u, 0x82u, 0x00u, 0xA2u, 0x04u, 0x00u, 0x43u, + 0x02u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, + 0x78u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xDEu, 0x40u, 0x4Bu, 0x04u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u +}; + +// UDB_UDBPAIR2_UDBSNG1 Address: CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR2_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x80u, 0x03u, 0x00u, 0xC9u, 0x00u, 0x12u, 0x00u, 0x00u, 0x00u, 0x01u, 0x70u, + 0x01u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x40u, 0x40u, 0xB3u, 0xAAu, 0x4Cu, 0xEAu, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x40u, 0x40u, 0xB1u, 0xAAu, 0x04u, 0x43u, 0x00u, 0x00u, + 0x01u, 0x4Cu, 0x05u, 0x00u, 0xBAu, 0x00u, 0x20u, 0x40u, 0x80u, 0x03u, 0x7Fu, 0xC0u, 0x80u, + 0x0Cu, 0x7Fu, 0x30u, 0x00u, 0xA2u, 0x00u, 0x08u, 0x22u, 0x08u, 0x22u, 0x51u, 0x04u, 0x43u, + 0x02u, 0x00u, 0x00u, 0x05u, 0xB0u, 0x40u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u +}; + +// UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = +{ + 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF5u, + 0x7Fu, 0xF3u, 0x11u, 0xF3u, 0x11u, 0xFFu, 0xF2u, 0xFFu, 0x2Fu, 0xFFu, 0xFFu, 0x00u, 0x11u, + 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, + 0xF7u, 0x5Fu, 0xFFu, 0x2Fu, 0x10u, 0x22u, 0x62u, 0x00u, 0x34u, 0x2Fu, 0x62u, 0x73u, 0x00u, + 0x11u, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x0Fu, + 0x0Fu, 0x27u, 0x20u, 0x22u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x40u, 0x1Du, 0x11u, 0x00u, 0xDDu, 0x11u, + 0x10u, 0x10u, 0x11u, 0x00u, 0xD1u, 0x63u, 0x03u, 0x01u, 0x13u, 0x37u, 0x00u, 0x13u, 0x11u, + 0x00u, 0x13u, 0x16u, 0x11u, 0x11u, 0x16u, 0x19u, 0x11u, 0x01u, 0x11u, 0x11u, 0x19u, 0x11u, + 0x11u, 0x91u, 0x41u, 0x11u, 0x21u, 0x11u, 0x16u, 0x11u, 0x11u, 0x13u, 0x81u, 0x11u, 0x11u, + 0x11u +}; + +// UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = +{ + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, + 0x13u, 0x42u, 0x36u, 0x26u, 0x33u, 0x35u, 0xF5u, 0xF0u, 0x54u, 0x14u, 0x62u, 0x5Fu, 0x0Fu, + 0x04u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x24u, 0x45u, 0x7Fu, + 0x50u, 0x26u, 0x64u, 0xFFu, 0x3Fu, 0x32u, 0x42u, 0xF3u, 0x32u, 0x3Fu, 0x7Fu, 0x37u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, + 0x02u, 0x05u, 0xF6u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x13u, 0xF0u, 0x10u, 0x14u, 0x00u, 0x01u, 0x01u, + 0x10u, 0x0Du, 0x63u, 0x00u, 0x70u, 0x10u, 0x08u, 0x30u, 0x13u, 0x11u, 0x30u, 0x10u, 0x50u, + 0x30u, 0x1Fu, 0xC1u, 0x33u, 0x10u, 0x0Fu, 0x01u, 0x31u, 0x0Du, 0x1Cu, 0x25u, 0x11u, 0x01u, + 0x12u, 0xFBu, 0x02u, 0x12u, 0x15u, 0x1Cu, 0x11u, 0x11u, 0x11u, 0x15u, 0x11u, 0x61u, 0x16u, + 0x11u +}; + +// UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = +{ + 0x06u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, + 0x33u, 0x35u, 0x44u, 0x77u, 0x57u, 0xF2u, 0xFFu, 0xF4u, 0xFFu, 0x40u, 0xFFu, 0x32u, 0x63u, + 0xFFu, 0xFFu, 0x3Fu, 0x5Fu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x34u, + 0x13u, 0x46u, 0x56u, 0x35u, 0x41u, 0x40u, 0x57u, 0x67u, 0x55u, 0x3Fu, 0x63u, 0xF6u, 0xFFu, + 0x4Fu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, + 0x00u, 0x00u, 0x40u, 0x22u, 0x00u, 0xF0u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0xF3u, 0x10u, 0x12u, 0x02u, 0x96u, 0x01u, + 0x00u, 0x74u, 0xD1u, 0x00u, 0xF7u, 0x03u, 0x03u, 0x16u, 0x1Fu, 0x31u, 0x10u, 0x00u, 0x03u, + 0x10u, 0x41u, 0x35u, 0x10u, 0x16u, 0x0Fu, 0x76u, 0x11u, 0xB0u, 0xD1u, 0xDFu, 0x09u, 0x00u, + 0x0Fu, 0xFBu, 0x01u, 0x11u, 0x17u, 0x11u, 0x11u, 0x15u, 0xD5u, 0x1Du, 0x27u, 0x15u, 0x1Fu, + 0x11u +}; + +// UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, + 0x41u, 0x53u, 0x15u, 0x45u, 0x11u, 0xF4u, 0xF3u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0x33u, 0x63u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x31u, 0x02u, 0x14u, + 0x56u, 0xF1u, 0x77u, 0x77u, 0x37u, 0xF0u, 0x56u, 0x73u, 0x45u, 0x33u, 0x63u, 0xFFu, 0x03u, + 0x15u, 0xF2u, 0xF2u, 0xF2u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xB0u, 0x00u, 0xF0u, 0x17u, 0x1Fu, 0x02u, 0x1Fu, 0x60u, + 0xA3u, 0xF4u, 0x15u, 0xA0u, 0xF1u, 0x0Fu, 0x00u, 0x31u, 0x0Fu, 0xF3u, 0x3Au, 0x20u, 0x51u, + 0x3Au, 0x13u, 0xF3u, 0xC0u, 0x10u, 0x4Au, 0x11u, 0x20u, 0x10u, 0x01u, 0xF1u, 0x0Fu, 0x00u, + 0x0Fu, 0xFFu, 0x41u, 0x11u, 0x41u, 0x4Du, 0x11u, 0x71u, 0x11u, 0x1Fu, 0xFCu, 0x11u, 0x1Fu, + 0x1Cu +}; + +// UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = +{ + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, + 0xF4u, 0x55u, 0x4Fu, 0xF3u, 0x5Fu, 0x55u, 0x27u, 0x31u, 0x63u, 0x71u, 0x61u, 0x3Fu, 0x63u, + 0x0Fu, 0x5Fu, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x64u, 0x31u, + 0x70u, 0x77u, 0xF6u, 0x2Fu, 0x1Fu, 0x25u, 0x4Fu, 0xF7u, 0x3Fu, 0x32u, 0x63u, 0x3Fu, 0x75u, + 0xF4u, 0x1Fu, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, + 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x70u, 0x30u, 0x26u, 0x14u, 0x2Fu, 0x0Cu, 0xA5u, 0x10u, + 0x18u, 0x11u, 0x0Fu, 0xF0u, 0xF7u, 0x3Fu, 0x00u, 0x11u, 0x0Fu, 0xFFu, 0xF8u, 0x16u, 0xF7u, + 0x1Fu, 0x10u, 0x11u, 0xF4u, 0x13u, 0xFFu, 0x67u, 0x13u, 0x15u, 0x07u, 0xF1u, 0x3Fu, 0xCDu, + 0x2Fu, 0x4Fu, 0xF6u, 0x12u, 0x12u, 0x11u, 0x11u, 0x19u, 0x11u, 0x21u, 0xFFu, 0x11u, 0x1Fu, + 0x11u +}; + +// UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, + 0x32u, 0xF3u, 0xF4u, 0xFFu, 0x45u, 0xFFu, 0x43u, 0x12u, 0x35u, 0x33u, 0xFFu, 0x3Fu, 0x5Fu, + 0x34u, 0xF0u, 0xFFu, 0x2Fu, 0xFFu, 0x12u, 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, + 0xF3u, 0xF3u, 0xFFu, 0x44u, 0x1Fu, 0xF2u, 0x04u, 0x01u, 0x2Fu, 0x30u, 0x2Fu, 0x3Fu, 0xFFu, + 0xF0u, 0x10u, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF5u, 0x17u, 0x11u, 0x16u, 0x11u, 0x2Cu, 0x1Fu, 0x17u, + 0x9Fu, 0x41u, 0x6Fu, 0xF4u, 0x1Fu, 0x33u, 0xCCu, 0x11u, 0x63u, 0x1Fu, 0x29u, 0x71u, 0xF5u, + 0x2Fu, 0x73u, 0x13u, 0xF1u, 0x13u, 0x11u, 0x1Au, 0x11u, 0x31u, 0x6Fu, 0x11u, 0x11u, 0x1Fu, + 0x11u, 0x1Au, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u +}; + +// UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI0_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI1_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI2_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI3_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x15u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI4_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI5_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI6_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x00u, 0x09u, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0x03u, 0xFFu, 0xF0u, 0xFFu, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, + 0x01u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0xD1u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI7_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x04u, + 0x12u, 0x10u, 0x0Du, 0x1Fu, 0x1Fu, 0x10u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0xFFu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x0Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x21u, 0xF1u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI8_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x20u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0xF1u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI9_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI10_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI11_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + + +static const cfg_memcpy_t CYCODE cfg_memcpy_list[] = +{ + // dest, src, size + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), BS_UDB_UDBPAIR5_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), BS_UDB_UDBPAIR4_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), BS_UDB_UDBPAIR3_UDBSNG0_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), BS_UDB_UDBPAIR2_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u }, +}; + +//-------------------------------------------------------------------------------------------------- +// SDIO_Host_Config_TriggerMuxes +//-------------------------------------------------------------------------------------------------- void SDIO_Host_Config_TriggerMuxes(void) { - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB10, TRIG14_OUT_TR_GROUP0_INPUT49, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT6, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB14, TRIG14_OUT_TR_GROUP0_INPUT48, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB9, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + // Connect UDB to DMA + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB10, TRIG14_OUT_TR_GROUP0_INPUT49, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT6, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB14, TRIG14_OUT_TR_GROUP0_INPUT48, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB9, TRIG14_OUT_TR_GROUP0_INPUT46, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, + TRIGGER_TYPE_LEVEL); } + +//-------------------------------------------------------------------------------------------------- +// SDIO_Host_Config_UDBs +//-------------------------------------------------------------------------------------------------- void SDIO_Host_Config_UDBs(void) { - - size_t i; + size_t i; - /* Power on the UDB array */ - CY_SET_REG32(0x402101F0u, 0x05FA0003u); + // Power on the UDB array + CY_SET_REG32(0x402101F0u, 0x05FA0003u); - /* Zero out critical memory blocks before beginning configuration */ - for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - { - const cfg_memset_t *ms = &cfg_memset_list[i]; - CYMEMZERO(ms->address, ms->size); - } + // Zero out critical memory blocks before beginning configuration + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t* ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, ms->size); + } - /* Copy device configuration data into registers */ - for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) - { - const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; - CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); - } + // Copy device configuration data into registers + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t* mc = &cfg_memcpy_list[i]; + CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); + } - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ - CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); + // UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL + CY_SET_REG32((void*)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); - /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C404Cu); + // UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C404Cu); - /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x044C4C44u); + // UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x044C4C44u); - /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x004C444Cu); + // UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x004C444Cu); - /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C44u); + // UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C44u); - /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x4C4C404Cu); + // UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x4C4C404Cu); - /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x004C4C4Cu); + // UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x004C4C4Cu); - /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x0C8C8C8Cu); + // UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x0C8C8C8Cu); - /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x004C404Cu); + // UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x004C404Cu); - /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x004C444Cu); + // UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x004C444Cu); - /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + // UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x4C4C0400u); + // UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x4C4C0400u); - /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + // UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + + // Enable UDB array and digital routing + CY_SET_REG32((void*)0x40347900u, CY_GET_REG32((void*)0x40347900u) | 0x106u); +} - /* Enable UDB array and digital routing */ - CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); - } #if defined(__cplusplus) } #endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h old mode 100644 new mode 100755 index 60ab730b5d..7a12ef0652 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h @@ -1,29 +1,28 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.h -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file COMPONENT_UDB_SDIO_P12/SDIO_HOST_cfg.h + * + * \brief + * This file provides the configuration of the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ -#if !defined(CY_SDIO_CFG_H) -#define CY_SDIO_CFG_H +#pragma once #include @@ -95,10 +94,10 @@ extern "C" { #define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u -/*************Defines for UDBs from Creator*****************************/ -/***********These come for cyfitter.h**********************************/ +// *************Defines for UDBs from Creator***************************** +// ***********These come for cyfitter.h********************************** -/* SDIO_HOST_bSDIO */ +// SDIO_HOST_bSDIO #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x40341008u #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x40341108u #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x40341208u @@ -764,79 +763,80 @@ extern "C" { #define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 -/***************************CMD DMA***************************************/ +// **************************CMD DMA*************************************** #define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) #define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) #define SDIO_HOST_CMD_DMA_HW (DW0) #define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_CMD_DMA_PRIORITY (1u) #define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) #define SDIO_HOST_CMD_DMA_BUFFERABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; -/***************************Read DMA***************************************/ +// **************************Read DMA*************************************** #define SDIO_HOST_Read_DMA_DW_BLOCK (1u) #define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) #define SDIO_HOST_Read_DMA_HW (DW1) #define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Read_DMA_PRIORITY (0u) #define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Read_DMA_PREEMPTABLE (false) #define SDIO_HOST_Read_DMA_BUFFERABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; -/***************************Resp DMA***************************************/ +// **************************Resp DMA*************************************** #define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) #define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) #define SDIO_HOST_Resp_DMA_HW (DW0) #define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Resp_DMA_PRIORITY (1u) #define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) #define SDIO_HOST_Resp_DMA_BUFFERABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; -/***************************Write DMA***************************************/ +// **************************Write DMA*************************************** #define SDIO_HOST_Write_DMA_DW_BLOCK (1u) #define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) #define SDIO_HOST_Write_DMA_HW (DW1) #define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Write_DMA_PRIORITY (0u) #define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Write_DMA_PREEMPTABLE (false) #define SDIO_HOST_Write_DMA_BUFFERABLE (true) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; -/***************************SDIO Clock**************************************/ +// **************************SDIO Clock************************************** /** The peripheral clock divider number */ #define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)SDIO_HOST_Internal_Clock__DIV_NUM) /** The peripheral clock divider type */ -#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE) +#define SDIO_HOST_Internal_Clock_DIV_TYPE \ + ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE) -/*Function for configuring TriggerMuxes*/ +// Function for configuring TriggerMuxes void SDIO_Host_Config_TriggerMuxes(void); -/*Function for configuring UDBs*/ +// Function for configuring UDBs void SDIO_Host_Config_UDBs(void); -/* SDIO_HOST_Read_Int */ +// SDIO_HOST_Read_Int #define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Read_Int__INTC_NUMBER 69u @@ -844,7 +844,7 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Read_Int_INTC_NUMBER 69u -/* SDIO_HOST_sdio_int */ +// SDIO_HOST_sdio_int #define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_sdio_int__INTC_NUMBER 122u @@ -852,7 +852,7 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_sdio_int_INTC_NUMBER 122u -/* SDIO_HOST_Write_Int */ +// SDIO_HOST_Write_Int #define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Write_Int__INTC_NUMBER 67u @@ -860,10 +860,9 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Write_Int_INTC_NUMBER 67u +// ****************************SDIO Port************************************** +#define SDIO_HOST_GPIO_PORT GPIO_PRT12 + #if defined(__cplusplus) } #endif - -#endif /* !defined(CY_SDIO_CFG_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c old mode 100644 new mode 100755 index a2808d37c0..ff2492240d --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c @@ -1,26 +1,26 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.c -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.c + * + * \brief + * This file provides the configuration of the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #include "SDIO_HOST_cfg.h" @@ -53,11 +53,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -86,11 +86,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -119,11 +119,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -152,11 +152,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -180,9 +180,9 @@ cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") -#else +#else // if defined(__GNUC__) || defined(__ARMCC_VERSION) #error Unsupported toolchain -#endif +#endif // if defined(__GNUC__) || defined(__ARMCC_VERSION) #ifndef CYCODE @@ -194,27 +194,41 @@ cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); +static void CYMEMZERO(void* s, size_t n); CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYMEMZERO +//-------------------------------------------------------------------------------------------------- +static void CYMEMZERO(void* s, size_t n) { (void)memset(s, 0, n); } + + CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); +static void CYCONFIGCPY(void* dest, const void* src, size_t n); CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYCONFIGCPY +//-------------------------------------------------------------------------------------------------- +static void CYCONFIGCPY(void* dest, const void* src, size_t n) { (void)memcpy(dest, src, n); } + + CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +static void CYCONFIGCPYCODE(void* dest, const void* src, size_t n); CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYCONFIGCPYCODE +//-------------------------------------------------------------------------------------------------- +static void CYCONFIGCPYCODE(void* dest, const void* src, size_t n) { (void)memcpy(dest, src, n); } + CYPACKED typedef struct { uint8 offset; @@ -238,819 +252,887 @@ CYPACKED typedef struct *******************************************************************************/ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +//-------------------------------------------------------------------------------------------------- +// cfg_write_bytes32 +//-------------------------------------------------------------------------------------------------- static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) { - /* For 32-bit little-endian architectures */ + // For 32-bit little-endian architectures uint32 i, j = 0u; for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) { uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; + uint8 count = (uint8)baseAddr; baseAddr &= 0xFFFFFF00u; while (count != 0u) { - CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + CY_SET_REG8((void*)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } } } -static const uint32 CYCODE cy_cfg_addr_table[] = + +static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40340002u, /* Base address: 0x40340000 Count: 2 */ - 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ - 0x40340301u, /* Base address: 0x40340300 Count: 1 */ - 0x40340405u, /* Base address: 0x40340400 Count: 5 */ - 0x40342466u, /* Base address: 0x40342400 Count: 102 */ - 0x40342632u, /* Base address: 0x40342600 Count: 50 */ - 0x4034282Bu, /* Base address: 0x40342800 Count: 43 */ - 0x40342A5Eu, /* Base address: 0x40342A00 Count: 94 */ - 0x40347005u, /* Base address: 0x40347000 Count: 5 */ - 0x40347102u, /* Base address: 0x40347100 Count: 2 */ - 0x40347202u, /* Base address: 0x40347200 Count: 2 */ - 0x40347804u, /* Base address: 0x40347800 Count: 4 */ + 0x40340002u, // Base address: 0x40340000 Count: 2 + 0x4034010Au, // Base address: 0x40340100 Count: 10 + 0x40340301u, // Base address: 0x40340300 Count: 1 + 0x40340405u, // Base address: 0x40340400 Count: 5 + 0x40342466u, // Base address: 0x40342400 Count: 102 + 0x40342632u, // Base address: 0x40342600 Count: 50 + 0x4034282Bu, // Base address: 0x40342800 Count: 43 + 0x40342A5Eu, // Base address: 0x40342A00 Count: 94 + 0x40347005u, // Base address: 0x40347000 Count: 5 + 0x40347102u, // Base address: 0x40347100 Count: 2 + 0x40347202u, // Base address: 0x40347200 Count: 2 + 0x40347804u, // Base address: 0x40347800 Count: 4 }; -static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = +static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - {0x18u, 0xFFu}, - {0x1Du, 0x01u}, - {0x00u, 0x10u}, - {0x04u, 0x88u}, - {0x09u, 0x02u}, - {0x10u, 0x10u}, - {0x14u, 0x88u}, - {0x1Du, 0x01u}, - {0x20u, 0x10u}, - {0x24u, 0x88u}, - {0x28u, 0x10u}, - {0x2Cu, 0x88u}, - {0x15u, 0x40u}, - {0x04u, 0x07u}, - {0x14u, 0x47u}, - {0x1Cu, 0x2Fu}, - {0x20u, 0x03u}, - {0x28u, 0x0Fu}, - {0x01u, 0x8Eu}, - {0x03u, 0x70u}, - {0x05u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Du, 0x04u}, - {0x11u, 0x60u}, - {0x13u, 0x80u}, - {0x15u, 0x04u}, - {0x18u, 0x02u}, - {0x19u, 0xD0u}, - {0x1Bu, 0x23u}, - {0x21u, 0x01u}, - {0x23u, 0x20u}, - {0x25u, 0xD0u}, - {0x27u, 0x2Fu}, - {0x2Du, 0x10u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x48u}, - {0x30u, 0x01u}, - {0x31u, 0xE0u}, - {0x34u, 0x02u}, - {0x35u, 0x1Fu}, - {0x3Bu, 0x02u}, - {0x3Du, 0x22u}, - {0x3Eu, 0x11u}, - {0x40u, 0x52u}, - {0x41u, 0x01u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x5Cu, 0x04u}, - {0x5Du, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x86u, 0x20u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x20u}, - {0x90u, 0xBAu}, - {0x92u, 0x04u}, - {0x94u, 0x08u}, - {0x96u, 0x11u}, - {0x98u, 0x78u}, - {0x9Au, 0x02u}, - {0x9Cu, 0x18u}, - {0x9Eu, 0xC4u}, - {0xA3u, 0x01u}, - {0xA4u, 0x08u}, - {0xA6u, 0x10u}, - {0xA8u, 0xFEu}, - {0xABu, 0x01u}, - {0xADu, 0x02u}, - {0xAEu, 0x20u}, - {0xB0u, 0x01u}, - {0xB2u, 0x18u}, - {0xB3u, 0x01u}, - {0xB4u, 0x06u}, - {0xB5u, 0x02u}, - {0xB6u, 0xE0u}, - {0xBAu, 0x08u}, - {0xBFu, 0x14u}, - {0xC0u, 0x52u}, - {0xC1u, 0x01u}, - {0xC4u, 0x06u}, - {0xC5u, 0xB0u}, - {0xC7u, 0x40u}, - {0xC8u, 0x22u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xD4u, 0xDEu}, - {0xD5u, 0x40u}, - {0xD6u, 0x4Bu}, - {0xD7u, 0x04u}, - {0xDCu, 0x0Cu}, - {0xDDu, 0x04u}, - {0xDEu, 0x0Cu}, - {0xDFu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x00u, 0x08u}, - {0x04u, 0x01u}, - {0x05u, 0x07u}, - {0x08u, 0x01u}, - {0x0Au, 0x08u}, - {0x0Fu, 0x05u}, - {0x12u, 0x01u}, - {0x14u, 0x10u}, - {0x16u, 0x01u}, - {0x18u, 0x01u}, - {0x1Au, 0x04u}, - {0x1Eu, 0x0Eu}, - {0x1Fu, 0x06u}, - {0x20u, 0x01u}, - {0x22u, 0x02u}, - {0x25u, 0x03u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x01u}, - {0x32u, 0x10u}, - {0x36u, 0x0Fu}, - {0x37u, 0x07u}, - {0x3Cu, 0x80u}, - {0x40u, 0x36u}, - {0x41u, 0x01u}, - {0x42u, 0x20u}, - {0x44u, 0x05u}, - {0x45u, 0xFBu}, - {0x46u, 0xC0u}, - {0x47u, 0xE0u}, - {0x48u, 0x2Bu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x02u}, - {0x4Fu, 0x0Cu}, - {0x50u, 0x08u}, - {0x51u, 0x10u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x65u, 0x08u}, - {0x68u, 0xC0u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x71u, 0x10u}, - {0x72u, 0x50u}, - {0x73u, 0xA8u}, - {0x82u, 0x08u}, - {0x84u, 0x07u}, - {0x86u, 0xF8u}, - {0x8Cu, 0x0Eu}, - {0x8Eu, 0xD1u}, - {0x92u, 0x21u}, - {0x96u, 0x01u}, - {0x98u, 0x04u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x04u}, - {0xA4u, 0xB9u}, - {0xA6u, 0x06u}, - {0xA8u, 0x89u}, - {0xAAu, 0x72u}, - {0xAEu, 0x60u}, - {0xB0u, 0x80u}, - {0xB2u, 0x7Fu}, - {0xBAu, 0x08u}, - {0xBCu, 0x08u}, - {0xBEu, 0x01u}, - {0xC0u, 0x42u}, - {0xC1u, 0x05u}, - {0xC4u, 0x06u}, - {0xC6u, 0x40u}, - {0xC7u, 0xB0u}, - {0xC8u, 0x28u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x03u, 0x40u}, - {0x09u, 0x10u}, - {0x0Cu, 0x2Au}, - {0x0Du, 0x30u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x0Au}, - {0x15u, 0x30u}, - {0x17u, 0x0Au}, - {0x1Du, 0x0Cu}, - {0x1Eu, 0x14u}, - {0x20u, 0x02u}, - {0x22u, 0x29u}, - {0x23u, 0x35u}, - {0x24u, 0x30u}, - {0x25u, 0x03u}, - {0x28u, 0x03u}, - {0x29u, 0x20u}, - {0x2Au, 0x28u}, - {0x2Cu, 0x0Cu}, - {0x2Du, 0x0Au}, - {0x2Fu, 0x30u}, - {0x30u, 0x01u}, - {0x31u, 0x70u}, - {0x32u, 0x30u}, - {0x33u, 0x0Cu}, - {0x34u, 0x0Cu}, - {0x35u, 0x03u}, - {0x36u, 0x02u}, - {0x38u, 0x28u}, - {0x39u, 0x28u}, - {0x3Eu, 0x55u}, - {0x3Fu, 0x15u}, - {0x40u, 0x42u}, - {0x41u, 0x05u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x7Fu}, - {0x5Cu, 0x04u}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x82u, 0x01u}, - {0x86u, 0x01u}, - {0x8Au, 0x02u}, - {0x8Cu, 0x01u}, - {0x98u, 0x01u}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x01u}, - {0xA8u, 0x01u}, - {0xACu, 0x03u}, - {0xAEu, 0x04u}, - {0xB4u, 0x07u}, - {0xB6u, 0x07u}, - {0xBCu, 0xA0u}, - {0xC0u, 0x42u}, - {0xC1u, 0x05u}, - {0xC4u, 0x06u}, - {0xC7u, 0xB4u}, - {0xC8u, 0x30u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Fu}, - {0xDEu, 0x0Fu}, - {0xDFu, 0x04u}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x28u, 0x10u}, - {0xA8u, 0xE1u}, - {0xACu, 0x52u}, - {0xB0u, 0xAAu}, - {0xB4u, 0x01u}, - {0xA8u, 0xA1u}, - {0xE8u, 0x02u}, - {0xA8u, 0x87u}, - {0xACu, 0x53u}, - {0x00u, 0x01u}, - {0x10u, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x01u}, + { 0x18u, 0xFFu }, + { 0x1Du, 0x01u }, + { 0x00u, 0x10u }, + { 0x04u, 0x88u }, + { 0x09u, 0x02u }, + { 0x10u, 0x10u }, + { 0x14u, 0x88u }, + { 0x1Du, 0x01u }, + { 0x20u, 0x10u }, + { 0x24u, 0x88u }, + { 0x28u, 0x10u }, + { 0x2Cu, 0x88u }, + { 0x15u, 0x40u }, + { 0x04u, 0x07u }, + { 0x14u, 0x47u }, + { 0x1Cu, 0x2Fu }, + { 0x20u, 0x03u }, + { 0x28u, 0x0Fu }, + { 0x01u, 0x8Eu }, + { 0x03u, 0x70u }, + { 0x05u, 0x04u }, + { 0x0Au, 0x01u }, + { 0x0Du, 0x04u }, + { 0x11u, 0x60u }, + { 0x13u, 0x80u }, + { 0x15u, 0x04u }, + { 0x18u, 0x02u }, + { 0x19u, 0xD0u }, + { 0x1Bu, 0x23u }, + { 0x21u, 0x01u }, + { 0x23u, 0x20u }, + { 0x25u, 0xD0u }, + { 0x27u, 0x2Fu }, + { 0x2Du, 0x10u }, + { 0x2Eu, 0x01u }, + { 0x2Fu, 0x48u }, + { 0x30u, 0x01u }, + { 0x31u, 0xE0u }, + { 0x34u, 0x02u }, + { 0x35u, 0x1Fu }, + { 0x3Bu, 0x02u }, + { 0x3Du, 0x22u }, + { 0x3Eu, 0x11u }, + { 0x40u, 0x52u }, + { 0x41u, 0x01u }, + { 0x44u, 0x06u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x5Cu, 0x04u }, + { 0x5Du, 0x0Cu }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0x86u, 0x20u }, + { 0x8Au, 0x20u }, + { 0x8Bu, 0x02u }, + { 0x8Cu, 0x20u }, + { 0x90u, 0xBAu }, + { 0x92u, 0x04u }, + { 0x94u, 0x08u }, + { 0x96u, 0x11u }, + { 0x98u, 0x78u }, + { 0x9Au, 0x02u }, + { 0x9Cu, 0x18u }, + { 0x9Eu, 0xC4u }, + { 0xA3u, 0x01u }, + { 0xA4u, 0x08u }, + { 0xA6u, 0x10u }, + { 0xA8u, 0xFEu }, + { 0xABu, 0x01u }, + { 0xADu, 0x02u }, + { 0xAEu, 0x20u }, + { 0xB0u, 0x01u }, + { 0xB2u, 0x18u }, + { 0xB3u, 0x01u }, + { 0xB4u, 0x06u }, + { 0xB5u, 0x02u }, + { 0xB6u, 0xE0u }, + { 0xBAu, 0x08u }, + { 0xBFu, 0x14u }, + { 0xC0u, 0x52u }, + { 0xC1u, 0x01u }, + { 0xC4u, 0x06u }, + { 0xC5u, 0xB0u }, + { 0xC7u, 0x40u }, + { 0xC8u, 0x22u }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCCu, 0x13u }, + { 0xCDu, 0x5Cu }, + { 0xCEu, 0x77u }, + { 0xD4u, 0xDEu }, + { 0xD5u, 0x40u }, + { 0xD6u, 0x4Bu }, + { 0xD7u, 0x04u }, + { 0xDCu, 0x0Cu }, + { 0xDDu, 0x04u }, + { 0xDEu, 0x0Cu }, + { 0xDFu, 0x0Cu }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE9u, 0x1Cu }, + { 0xEAu, 0x58u }, + { 0xEBu, 0xA1u }, + { 0xEDu, 0x10u }, + { 0xF0u, 0x10u }, + { 0xF1u, 0x1Du }, + { 0x00u, 0x08u }, + { 0x04u, 0x01u }, + { 0x05u, 0x07u }, + { 0x08u, 0x01u }, + { 0x0Au, 0x08u }, + { 0x0Fu, 0x05u }, + { 0x12u, 0x01u }, + { 0x14u, 0x10u }, + { 0x16u, 0x01u }, + { 0x18u, 0x01u }, + { 0x1Au, 0x04u }, + { 0x1Eu, 0x0Eu }, + { 0x1Fu, 0x06u }, + { 0x20u, 0x01u }, + { 0x22u, 0x02u }, + { 0x25u, 0x03u }, + { 0x2Au, 0x10u }, + { 0x2Bu, 0x01u }, + { 0x32u, 0x10u }, + { 0x36u, 0x0Fu }, + { 0x37u, 0x07u }, + { 0x3Cu, 0x80u }, + { 0x40u, 0x36u }, + { 0x41u, 0x01u }, + { 0x42u, 0x20u }, + { 0x44u, 0x05u }, + { 0x45u, 0xFBu }, + { 0x46u, 0xC0u }, + { 0x47u, 0xE0u }, + { 0x48u, 0x2Bu }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x02u }, + { 0x4Fu, 0x0Cu }, + { 0x50u, 0x08u }, + { 0x51u, 0x10u }, + { 0x5Cu, 0x0Cu }, + { 0x5Du, 0x0Cu }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x65u, 0x08u }, + { 0x68u, 0xC0u }, + { 0x6Cu, 0x10u }, + { 0x6Du, 0x11u }, + { 0x6Eu, 0x40u }, + { 0x6Fu, 0x01u }, + { 0x71u, 0x10u }, + { 0x72u, 0x50u }, + { 0x73u, 0xA8u }, + { 0x82u, 0x08u }, + { 0x84u, 0x07u }, + { 0x86u, 0xF8u }, + { 0x8Cu, 0x0Eu }, + { 0x8Eu, 0xD1u }, + { 0x92u, 0x21u }, + { 0x96u, 0x01u }, + { 0x98u, 0x04u }, + { 0x9Eu, 0x04u }, + { 0xA0u, 0x04u }, + { 0xA4u, 0xB9u }, + { 0xA6u, 0x06u }, + { 0xA8u, 0x89u }, + { 0xAAu, 0x72u }, + { 0xAEu, 0x60u }, + { 0xB0u, 0x80u }, + { 0xB2u, 0x7Fu }, + { 0xBAu, 0x08u }, + { 0xBCu, 0x08u }, + { 0xBEu, 0x01u }, + { 0xC0u, 0x42u }, + { 0xC1u, 0x05u }, + { 0xC4u, 0x06u }, + { 0xC6u, 0x40u }, + { 0xC7u, 0xB0u }, + { 0xC8u, 0x28u }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCCu, 0x13u }, + { 0xCDu, 0x5Cu }, + { 0xCEu, 0x77u }, + { 0xDCu, 0x0Cu }, + { 0xDEu, 0x0Cu }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE9u, 0x1Cu }, + { 0xEAu, 0x58u }, + { 0xEBu, 0xA1u }, + { 0xEDu, 0x10u }, + { 0xF0u, 0x10u }, + { 0xF1u, 0x1Du }, + { 0x03u, 0x40u }, + { 0x09u, 0x10u }, + { 0x0Cu, 0x2Au }, + { 0x0Du, 0x30u }, + { 0x0Eu, 0x01u }, + { 0x0Fu, 0x0Au }, + { 0x15u, 0x30u }, + { 0x17u, 0x0Au }, + { 0x1Du, 0x0Cu }, + { 0x1Eu, 0x14u }, + { 0x20u, 0x02u }, + { 0x22u, 0x29u }, + { 0x23u, 0x35u }, + { 0x24u, 0x30u }, + { 0x25u, 0x03u }, + { 0x28u, 0x03u }, + { 0x29u, 0x20u }, + { 0x2Au, 0x28u }, + { 0x2Cu, 0x0Cu }, + { 0x2Du, 0x0Au }, + { 0x2Fu, 0x30u }, + { 0x30u, 0x01u }, + { 0x31u, 0x70u }, + { 0x32u, 0x30u }, + { 0x33u, 0x0Cu }, + { 0x34u, 0x0Cu }, + { 0x35u, 0x03u }, + { 0x36u, 0x02u }, + { 0x38u, 0x28u }, + { 0x39u, 0x28u }, + { 0x3Eu, 0x55u }, + { 0x3Fu, 0x15u }, + { 0x40u, 0x42u }, + { 0x41u, 0x05u }, + { 0x44u, 0x06u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x57u, 0x02u }, + { 0x58u, 0x7Fu }, + { 0x5Cu, 0x04u }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x5Fu, 0x0Cu }, + { 0x62u, 0x08u }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0x82u, 0x01u }, + { 0x86u, 0x01u }, + { 0x8Au, 0x02u }, + { 0x8Cu, 0x01u }, + { 0x98u, 0x01u }, + { 0x9Cu, 0x03u }, + { 0x9Eu, 0x04u }, + { 0xA0u, 0x01u }, + { 0xA8u, 0x01u }, + { 0xACu, 0x03u }, + { 0xAEu, 0x04u }, + { 0xB4u, 0x07u }, + { 0xB6u, 0x07u }, + { 0xBCu, 0xA0u }, + { 0xC0u, 0x42u }, + { 0xC1u, 0x05u }, + { 0xC4u, 0x06u }, + { 0xC7u, 0xB4u }, + { 0xC8u, 0x30u }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCCu, 0x13u }, + { 0xCDu, 0x5Cu }, + { 0xCEu, 0x77u }, + { 0xDCu, 0x0Fu }, + { 0xDEu, 0x0Fu }, + { 0xDFu, 0x04u }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE9u, 0x1Cu }, + { 0xEAu, 0x58u }, + { 0xEBu, 0xA1u }, + { 0xEDu, 0x10u }, + { 0xF0u, 0x10u }, + { 0xF1u, 0x1Du }, + { 0x28u, 0x10u }, + { 0xA8u, 0xE1u }, + { 0xACu, 0x52u }, + { 0xB0u, 0xAAu }, + { 0xB4u, 0x01u }, + { 0xA8u, 0xA1u }, + { 0xE8u, 0x02u }, + { 0xA8u, 0x87u }, + { 0xACu, 0x53u }, + { 0x00u, 0x01u }, + { 0x10u, 0x01u }, + { 0x14u, 0x01u }, + { 0x18u, 0x01u }, }; -CYPACKED typedef struct +CYPACKED typedef struct { -void *address; -uint16 size; + void* address; + uint16 size; } CYPACKED_ATTR cfg_memset_t; -CYPACKED typedef struct +CYPACKED typedef struct { - void *dest; - const void *src; - size_t size; + void* dest; + const void* src; + size_t size; } CYPACKED_ATTR cfg_memcpy_t; -static const cfg_memset_t CYCODE cfg_memset_list[] = +static const cfg_memset_t CYCODE cfg_memset_list[] = { - /* address, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), 116u}, + // address, size + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), 116u }, }; -/* UDB_UDBPAIR4_UDBSNG0 Address: CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG0_VAL[] = +// UDB_UDBPAIR4_UDBSNG0 Address: CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG0_VAL[] = { - 0x42u, 0x00u, 0x25u, 0x0Au, 0x50u, 0x00u, 0x08u, 0x00u, 0x48u, 0x00u, 0x10u, 0x05u, 0x04u, 0x00u, 0x00u, 0x00u, - 0x61u, 0x00u, 0x06u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x00u, 0x41u, 0x0Cu, 0x26u, 0x03u, 0x00u, 0x00u, 0x04u, 0x0Au, - 0x48u, 0x05u, 0x10u, 0x00u, 0x40u, 0x00u, 0x18u, 0x05u, 0x04u, 0x00u, 0x00u, 0x05u, 0x02u, 0x00u, 0x00u, 0x00u, - 0x07u, 0x0Cu, 0x40u, 0x03u, 0x07u, 0x00u, 0x38u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x22u, 0x00u, 0x44u, 0x05u, - 0x42u, 0x05u, 0x00u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x71u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u + 0x42u, 0x00u, 0x25u, 0x0Au, 0x50u, 0x00u, 0x08u, 0x00u, 0x48u, 0x00u, 0x10u, 0x05u, 0x04u, + 0x00u, 0x00u, 0x00u, 0x61u, 0x00u, 0x06u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x00u, 0x41u, 0x0Cu, + 0x26u, 0x03u, 0x00u, 0x00u, 0x04u, 0x0Au, 0x48u, 0x05u, 0x10u, 0x00u, 0x40u, 0x00u, 0x18u, + 0x05u, 0x04u, 0x00u, 0x00u, 0x05u, 0x02u, 0x00u, 0x00u, 0x00u, 0x07u, 0x0Cu, 0x40u, 0x03u, + 0x07u, 0x00u, 0x38u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x22u, 0x00u, 0x44u, 0x05u, 0x42u, + 0x05u, 0x00u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, + 0x78u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x71u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u }; -/* UDB_UDBPAIR3_UDBSNG1 Address: CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG1_VAL[] = +// UDB_UDBPAIR3_UDBSNG1 Address: CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x88u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x02u, 0x88u, 0x01u, 0x00u, - 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x88u, 0x03u, 0x00u, 0x01u, 0xBCu, 0x00u, 0x40u, 0x39u, 0x22u, 0x46u, 0xC5u, - 0x00u, 0x00u, 0x04u, 0x01u, 0x28u, 0xA2u, 0x56u, 0x4Du, 0x51u, 0x00u, 0x2Eu, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, - 0x00u, 0x60u, 0x00u, 0x80u, 0x1Fu, 0x00u, 0x60u, 0x1Fu, 0x00u, 0x80u, 0x20u, 0x00u, 0x20u, 0x80u, 0x40u, 0x05u, - 0x64u, 0x03u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x06u, 0x11u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0xA0u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x73u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x00u, 0x00u, 0x40u, 0x40u, 0x10u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u + 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x88u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x02u, + 0x88u, 0x01u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x88u, 0x03u, 0x00u, 0x01u, 0xBCu, + 0x00u, 0x40u, 0x39u, 0x22u, 0x46u, 0xC5u, 0x00u, 0x00u, 0x04u, 0x01u, 0x28u, 0xA2u, 0x56u, + 0x4Du, 0x51u, 0x00u, 0x2Eu, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x00u, 0x60u, 0x00u, 0x80u, + 0x1Fu, 0x00u, 0x60u, 0x1Fu, 0x00u, 0x80u, 0x20u, 0x00u, 0x20u, 0x80u, 0x40u, 0x05u, 0x64u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x06u, 0x11u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0xA0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x73u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x00u, 0x00u, 0x40u, 0x40u, + 0x10u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u }; -/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = +// UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = { - 0x04u, 0x20u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x79u, 0x00u, 0x82u, 0x11u, 0x48u, 0x2Eu, 0x95u, - 0x09u, 0x08u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x8Du, 0x00u, 0x72u, 0x20u, 0x08u, 0x00u, 0x00u, - 0x2Eu, 0x00u, 0x11u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, - 0x38u, 0xE0u, 0x02u, 0x07u, 0x04u, 0x18u, 0x01u, 0x07u, 0x00u, 0x00u, 0x82u, 0x22u, 0x82u, 0xAAu, 0x14u, 0x00u, - 0x41u, 0x05u, 0x63u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0xF0u, 0x21u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x08u, 0x03u, 0x08u, 0x00u, 0x18u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x58u, 0xECu, 0x00u, 0x00u + 0x04u, 0x20u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x79u, 0x00u, 0x82u, 0x11u, + 0x48u, 0x2Eu, 0x95u, 0x09u, 0x08u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x8Du, + 0x00u, 0x72u, 0x20u, 0x08u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0x11u, 0x00u, 0x00u, 0x08u, 0x00u, + 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, 0x38u, 0xE0u, 0x02u, 0x07u, + 0x04u, 0x18u, 0x01u, 0x07u, 0x00u, 0x00u, 0x82u, 0x22u, 0x82u, 0xAAu, 0x14u, 0x00u, 0x41u, + 0x05u, 0x63u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0xF0u, 0x21u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, + 0x00u, 0x2Fu, 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x08u, 0x03u, + 0x08u, 0x00u, 0x18u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x58u, 0xECu, 0x00u, 0x00u }; -/* UDB_UDBPAIR0_UDBSNG0 Address: CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG0_VAL[] = +// UDB_UDBPAIR0_UDBSNG0 Address: CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG0_VAL[] = { - 0x95u, 0x08u, 0x6Au, 0x00u, 0x26u, 0x62u, 0xD9u, 0x9Du, 0x82u, 0x00u, 0x40u, 0x42u, 0x00u, 0x00u, 0x80u, 0x00u, - 0x00u, 0x00u, 0x90u, 0x32u, 0x4Eu, 0x00u, 0xB1u, 0x01u, 0x92u, 0x00u, 0x6Du, 0x00u, 0x00u, 0xB5u, 0x04u, 0x4Au, - 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0xF2u, 0x00u, 0x09u, 0x00u, 0x66u, 0x01u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x3Fu, 0xE0u, 0xC0u, 0x1Fu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x2Au, 0x0Au, 0x2Au, 0x0Au, 0x00u, 0x00u, - 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u + 0x95u, 0x08u, 0x6Au, 0x00u, 0x26u, 0x62u, 0xD9u, 0x9Du, 0x82u, 0x00u, 0x40u, 0x42u, 0x00u, + 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x90u, 0x32u, 0x4Eu, 0x00u, 0xB1u, 0x01u, 0x92u, 0x00u, + 0x6Du, 0x00u, 0x00u, 0xB5u, 0x04u, 0x4Au, 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0xF2u, 0x00u, + 0x09u, 0x00u, 0x66u, 0x01u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xE0u, 0xC0u, 0x1Fu, + 0x3Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x2Au, 0x0Au, 0x2Au, 0x0Au, 0x00u, 0x00u, 0x43u, + 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, + 0x78u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u }; -/* UDB_UDBPAIR1_UDBSNG0 Address: CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG0_VAL[] = +// UDB_UDBPAIR1_UDBSNG0 Address: CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG0_VAL[] = { - 0x00u, 0x01u, 0x00u, 0x00u, 0xABu, 0x00u, 0x00u, 0x03u, 0x2Bu, 0xC9u, 0x54u, 0x12u, 0x02u, 0x00u, 0x00u, 0x40u, - 0xAAu, 0x00u, 0x01u, 0x01u, 0x81u, 0x05u, 0x2Au, 0xBAu, 0xAAu, 0x00u, 0x00u, 0x40u, 0x08u, 0xB3u, 0x00u, 0x4Cu, - 0x04u, 0x20u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x01u, 0x10u, 0x01u, 0x00u, 0x80u, 0x20u, 0xB1u, 0x00u, 0x04u, - 0x19u, 0x00u, 0x07u, 0x80u, 0x61u, 0x00u, 0x80u, 0x7Fu, 0x2Au, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x55u, 0x04u, - 0x24u, 0x06u, 0x00u, 0x00u, 0x01u, 0x0Eu, 0x00u, 0xC4u, 0x31u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, - 0x40u, 0x03u, 0x00u, 0x10u + 0x00u, 0x01u, 0x00u, 0x00u, 0xABu, 0x00u, 0x00u, 0x03u, 0x2Bu, 0xC9u, 0x54u, 0x12u, 0x02u, + 0x00u, 0x00u, 0x40u, 0xAAu, 0x00u, 0x01u, 0x01u, 0x81u, 0x05u, 0x2Au, 0xBAu, 0xAAu, 0x00u, + 0x00u, 0x40u, 0x08u, 0xB3u, 0x00u, 0x4Cu, 0x04u, 0x20u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, + 0x01u, 0x10u, 0x01u, 0x00u, 0x80u, 0x20u, 0xB1u, 0x00u, 0x04u, 0x19u, 0x00u, 0x07u, 0x80u, + 0x61u, 0x00u, 0x80u, 0x7Fu, 0x2Au, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x55u, 0x04u, 0x24u, + 0x06u, 0x00u, 0x00u, 0x01u, 0x0Eu, 0x00u, 0xC4u, 0x31u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, + 0x00u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, + 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, 0x40u, 0x03u, 0x00u, 0x10u }; -/* UDB_UDBPAIR0_UDBSNG1 Address: CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG1_VAL[] = +// UDB_UDBPAIR0_UDBSNG1 Address: CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x80u, 0x03u, 0x7Bu, 0x04u, 0x80u, 0x00u, 0x33u, 0x1Cu, 0xCCu, 0x00u, 0x04u, 0x03u, 0x00u, 0x00u, - 0x8Au, 0x00u, 0x71u, 0x04u, 0xB9u, 0x00u, 0x42u, 0x0Cu, 0x00u, 0x03u, 0x20u, 0x00u, 0x00u, 0x14u, 0x00u, 0x00u, - 0x00u, 0x00u, 0xA0u, 0x03u, 0x0Au, 0x1Cu, 0xD0u, 0x00u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, - 0x00u, 0x07u, 0x00u, 0x18u, 0xF8u, 0x00u, 0x07u, 0x00u, 0x80u, 0x08u, 0x20u, 0x00u, 0x20u, 0x00u, 0x40u, 0x05u, - 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x0Bu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u + 0x00u, 0x00u, 0x80u, 0x03u, 0x7Bu, 0x04u, 0x80u, 0x00u, 0x33u, 0x1Cu, 0xCCu, 0x00u, 0x04u, + 0x03u, 0x00u, 0x00u, 0x8Au, 0x00u, 0x71u, 0x04u, 0xB9u, 0x00u, 0x42u, 0x0Cu, 0x00u, 0x03u, + 0x20u, 0x00u, 0x00u, 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0xA0u, 0x03u, 0x0Au, 0x1Cu, 0xD0u, + 0x00u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x07u, 0x00u, 0x18u, + 0xF8u, 0x00u, 0x07u, 0x00u, 0x80u, 0x08u, 0x20u, 0x00u, 0x20u, 0x00u, 0x40u, 0x05u, 0x43u, + 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x0Bu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x7Fu, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u }; -/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = +// UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x25u, 0x40u, 0x13u, 0x30u, - 0x54u, 0xF1u, 0x1Fu, 0xF6u, 0xF5u, 0x33u, 0x05u, 0x12u, 0x33u, 0x51u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x21u, 0x32u, 0x75u, 0x37u, 0x23u, 0xF5u, 0x51u, 0x14u, 0x54u, 0x32u, 0x11u, 0x41u, - 0x33u, 0x51u, 0xFFu, 0x0Fu, 0x5Fu, 0xFFu, 0x2Fu, 0x22u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x14u, 0x01u, 0x01u, 0x11u, 0x10u, 0x44u, 0x53u, 0x33u, 0x14u, 0x11u, 0x40u, 0x01u, 0x01u, 0x33u, 0x4Cu, 0x04u, - 0x11u, 0x01u, 0x3Bu, 0x01u, 0x01u, 0x10u, 0x11u, 0x00u, 0x62u, 0x10u, 0x11u, 0x13u, 0x11u, 0x19u, 0x11u, 0x16u, - 0x09u, 0x73u, 0x10u, 0x66u, 0x11u, 0x11u, 0x11u, 0x11u, 0x12u, 0x11u, 0x11u, 0x14u, 0x11u, 0x14u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x25u, + 0x40u, 0x13u, 0x30u, 0x54u, 0xF1u, 0x1Fu, 0xF6u, 0xF5u, 0x33u, 0x05u, 0x12u, 0x33u, 0x51u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x21u, 0x32u, 0x75u, + 0x37u, 0x23u, 0xF5u, 0x51u, 0x14u, 0x54u, 0x32u, 0x11u, 0x41u, 0x33u, 0x51u, 0xFFu, 0x0Fu, + 0x5Fu, 0xFFu, 0x2Fu, 0x22u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x14u, 0x01u, 0x01u, 0x11u, 0x10u, 0x44u, 0x53u, 0x33u, + 0x14u, 0x11u, 0x40u, 0x01u, 0x01u, 0x33u, 0x4Cu, 0x04u, 0x11u, 0x01u, 0x3Bu, 0x01u, 0x01u, + 0x10u, 0x11u, 0x00u, 0x62u, 0x10u, 0x11u, 0x13u, 0x11u, 0x19u, 0x11u, 0x16u, 0x09u, 0x73u, + 0x10u, 0x66u, 0x11u, 0x11u, 0x11u, 0x11u, 0x12u, 0x11u, 0x11u, 0x14u, 0x11u, 0x14u, 0x11u, + 0x11u }; -/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = +// UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0xF5u, 0x5Fu, - 0x22u, 0xFFu, 0x04u, 0xF1u, 0x56u, 0x63u, 0x61u, 0x12u, 0xF7u, 0x04u, 0x37u, 0x16u, 0x63u, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, 0x52u, 0x75u, 0x60u, 0x45u, 0x04u, 0x14u, 0x31u, 0x44u, 0x12u, 0x76u, 0x13u, - 0x51u, 0x73u, 0x70u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x25u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x00u, 0xF5u, - 0x4Fu, 0x06u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x03u, 0x06u, 0x00u, 0xA1u, 0x06u, 0x0Cu, 0x36u, 0xF5u, 0x0Du, 0x10u, 0xF3u, 0x01u, 0x00u, 0xFFu, 0x3Fu, 0x0Fu, - 0x15u, 0x00u, 0xFBu, 0x01u, 0x03u, 0x10u, 0x11u, 0x4Cu, 0x11u, 0x52u, 0x90u, 0xC1u, 0xD2u, 0x15u, 0xC3u, 0x5Fu, - 0x36u, 0x0Fu, 0x23u, 0x3Cu, 0x00u, 0x11u, 0x15u, 0x11u, 0x11u, 0x31u, 0x14u, 0x1Fu, 0x11u, 0x8Fu, 0x11u, 0xC1u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, + 0x0Fu, 0xF5u, 0x5Fu, 0x22u, 0xFFu, 0x04u, 0xF1u, 0x56u, 0x63u, 0x61u, 0x12u, 0xF7u, 0x04u, + 0x37u, 0x16u, 0x63u, 0xFFu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, 0x52u, 0x75u, + 0x60u, 0x45u, 0x04u, 0x14u, 0x31u, 0x44u, 0x12u, 0x76u, 0x13u, 0x51u, 0x73u, 0x70u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x25u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, + 0x00u, 0xF5u, 0x4Fu, 0x06u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x03u, 0x06u, 0x00u, 0xA1u, 0x06u, 0x0Cu, 0x36u, 0xF5u, + 0x0Du, 0x10u, 0xF3u, 0x01u, 0x00u, 0xFFu, 0x3Fu, 0x0Fu, 0x15u, 0x00u, 0xFBu, 0x01u, 0x03u, + 0x10u, 0x11u, 0x4Cu, 0x11u, 0x52u, 0x90u, 0xC1u, 0xD2u, 0x15u, 0xC3u, 0x5Fu, 0x36u, 0x0Fu, + 0x23u, 0x3Cu, 0x00u, 0x11u, 0x15u, 0x11u, 0x11u, 0x31u, 0x14u, 0x1Fu, 0x11u, 0x8Fu, 0x11u, + 0xC1u }; -/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = +// UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x11u, 0xFFu, 0x45u, - 0xFFu, 0x5Fu, 0xF5u, 0x44u, 0x4Fu, 0x36u, 0x43u, 0x73u, 0x13u, 0xFFu, 0x23u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x6Fu, 0x24u, 0x45u, 0x44u, 0x1Fu, 0x63u, 0x17u, 0x1Fu, 0xFFu, 0xFFu, 0x4Fu, 0xFFu, - 0x13u, 0x14u, 0x63u, 0x07u, 0x55u, 0xF7u, 0xF7u, 0x72u, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x05u, 0x2Fu, 0x10u, - 0xF0u, 0xF3u, 0xF0u, 0x10u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x01u, 0x00u, 0x8Du, 0x16u, 0x21u, 0x0Fu, 0x1Fu, 0x1Fu, 0xAFu, 0xB0u, 0x0Fu, 0xADu, 0x00u, 0xFFu, 0x4Fu, 0x00u, - 0x05u, 0x0Du, 0x0Au, 0x41u, 0x00u, 0xAAu, 0x01u, 0xF1u, 0xC4u, 0x10u, 0xF0u, 0x04u, 0xF3u, 0x1Fu, 0xC4u, 0x3Fu, - 0x1Fu, 0x03u, 0xF0u, 0xF0u, 0x88u, 0x01u, 0x3Fu, 0x01u, 0x11u, 0xB1u, 0x57u, 0x81u, 0x11u, 0xC1u, 0x1Du, 0x14u + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0x11u, 0xFFu, 0x45u, 0xFFu, 0x5Fu, 0xF5u, 0x44u, 0x4Fu, 0x36u, 0x43u, 0x73u, 0x13u, 0xFFu, + 0x23u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x6Fu, 0x24u, 0x45u, + 0x44u, 0x1Fu, 0x63u, 0x17u, 0x1Fu, 0xFFu, 0xFFu, 0x4Fu, 0xFFu, 0x13u, 0x14u, 0x63u, 0x07u, + 0x55u, 0xF7u, 0xF7u, 0x72u, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x05u, + 0x2Fu, 0x10u, 0xF0u, 0xF3u, 0xF0u, 0x10u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x01u, 0x00u, 0x8Du, 0x16u, 0x21u, 0x0Fu, 0x1Fu, 0x1Fu, + 0xAFu, 0xB0u, 0x0Fu, 0xADu, 0x00u, 0xFFu, 0x4Fu, 0x00u, 0x05u, 0x0Du, 0x0Au, 0x41u, 0x00u, + 0xAAu, 0x01u, 0xF1u, 0xC4u, 0x10u, 0xF0u, 0x04u, 0xF3u, 0x1Fu, 0xC4u, 0x3Fu, 0x1Fu, 0x03u, + 0xF0u, 0xF0u, 0x88u, 0x01u, 0x3Fu, 0x01u, 0x11u, 0xB1u, 0x57u, 0x81u, 0x11u, 0xC1u, 0x1Du, + 0x14u }; -/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = +// UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x36u, 0x34u, 0x32u, - 0x06u, 0x14u, 0xF5u, 0x46u, 0x43u, 0xF6u, 0xF3u, 0x43u, 0xFFu, 0x37u, 0x5Fu, 0xFFu, 0x5Fu, 0xF2u, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x45u, 0xF4u, 0x37u, 0x40u, 0xF0u, 0xF2u, 0x7Fu, 0xF4u, 0xF4u, 0xFFu, 0xF3u, 0x03u, - 0x73u, 0xF0u, 0x77u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF2u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x00u, 0x06u, 0xBFu, 0x17u, 0x11u, 0x7Fu, 0x71u, 0x11u, 0x5Fu, 0x70u, 0x5Fu, 0xFFu, 0x06u, 0xFFu, 0x0Fu, 0x07u, - 0x7Fu, 0x3Fu, 0x0Fu, 0xF6u, 0x00u, 0x2Fu, 0x7Fu, 0x48u, 0xF4u, 0x30u, 0xB0u, 0x5Fu, 0x11u, 0x0Fu, 0x91u, 0xFFu, - 0x1Fu, 0x0Au, 0xF3u, 0xFBu, 0x15u, 0x11u, 0x1Fu, 0xA1u, 0x11u, 0x81u, 0x11u, 0x12u, 0x14u, 0x11u, 0x1Fu, 0x31u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, + 0x36u, 0x34u, 0x32u, 0x06u, 0x14u, 0xF5u, 0x46u, 0x43u, 0xF6u, 0xF3u, 0x43u, 0xFFu, 0x37u, + 0x5Fu, 0xFFu, 0x5Fu, 0xF2u, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x45u, 0xF4u, 0x37u, + 0x40u, 0xF0u, 0xF2u, 0x7Fu, 0xF4u, 0xF4u, 0xFFu, 0xF3u, 0x03u, 0x73u, 0xF0u, 0x77u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xF2u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x06u, 0xBFu, 0x17u, 0x11u, 0x7Fu, 0x71u, 0x11u, + 0x5Fu, 0x70u, 0x5Fu, 0xFFu, 0x06u, 0xFFu, 0x0Fu, 0x07u, 0x7Fu, 0x3Fu, 0x0Fu, 0xF6u, 0x00u, + 0x2Fu, 0x7Fu, 0x48u, 0xF4u, 0x30u, 0xB0u, 0x5Fu, 0x11u, 0x0Fu, 0x91u, 0xFFu, 0x1Fu, 0x0Au, + 0xF3u, 0xFBu, 0x15u, 0x11u, 0x1Fu, 0xA1u, 0x11u, 0x81u, 0x11u, 0x12u, 0x14u, 0x11u, 0x1Fu, + 0x31u }; -/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = +// UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x17u, 0xF5u, 0x65u, - 0x77u, 0x77u, 0x7Fu, 0x05u, 0x14u, 0xF4u, 0x5Fu, 0x0Fu, 0x1Fu, 0x5Fu, 0x43u, 0x5Fu, 0xFFu, 0xF2u, 0xFFu, 0x05u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x23u, 0x7Fu, 0x52u, 0x64u, 0x55u, 0x75u, 0xFFu, 0xFFu, 0xF5u, 0xFFu, 0x11u, 0xFFu, - 0x1Fu, 0x52u, 0x13u, 0x40u, 0xFFu, 0xF3u, 0xFFu, 0xF5u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x25u, 0x00u, 0x30u, - 0x00u, 0x00u, 0x00u, 0x13u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x00u, 0x81u, 0x1Fu, 0x11u, 0x11u, 0x5Fu, 0x91u, 0x10u, 0xFFu, 0x33u, 0x0Fu, 0xFFu, 0x30u, 0xFFu, 0x4Fu, 0x31u, - 0x1Fu, 0xFFu, 0x06u, 0x06u, 0x0Au, 0x28u, 0x08u, 0x66u, 0x11u, 0x10u, 0xF9u, 0x17u, 0x20u, 0x3Fu, 0x10u, 0x2Fu, - 0x1Fu, 0x00u, 0xF1u, 0xF6u, 0x1Bu, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x33u, 0x31u, 0x11u, 0x17u, 0x11u, 0x11u, 0x1Bu + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, + 0x17u, 0xF5u, 0x65u, 0x77u, 0x77u, 0x7Fu, 0x05u, 0x14u, 0xF4u, 0x5Fu, 0x0Fu, 0x1Fu, 0x5Fu, + 0x43u, 0x5Fu, 0xFFu, 0xF2u, 0xFFu, 0x05u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x23u, 0x7Fu, 0x52u, + 0x64u, 0x55u, 0x75u, 0xFFu, 0xFFu, 0xF5u, 0xFFu, 0x11u, 0xFFu, 0x1Fu, 0x52u, 0x13u, 0x40u, + 0xFFu, 0xF3u, 0xFFu, 0xF5u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x25u, + 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x13u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x81u, 0x1Fu, 0x11u, 0x11u, 0x5Fu, 0x91u, 0x10u, + 0xFFu, 0x33u, 0x0Fu, 0xFFu, 0x30u, 0xFFu, 0x4Fu, 0x31u, 0x1Fu, 0xFFu, 0x06u, 0x06u, 0x0Au, + 0x28u, 0x08u, 0x66u, 0x11u, 0x10u, 0xF9u, 0x17u, 0x20u, 0x3Fu, 0x10u, 0x2Fu, 0x1Fu, 0x00u, + 0xF1u, 0xF6u, 0x1Bu, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x33u, 0x31u, 0x11u, 0x17u, 0x11u, 0x11u, + 0x1Bu }; -/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = +// UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, 0x43u, 0xFFu, 0x30u, - 0xF0u, 0x22u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Fu, 0x5Fu, 0x53u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x42u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0xF3u, 0x1Fu, 0x15u, 0x11u, 0x13u, 0x13u, 0x41u, 0xF1u, 0x31u, 0x3Fu, - 0x1Fu, 0x53u, 0x03u, 0xF0u, 0x4Fu, 0xFFu, 0x2Fu, 0x13u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x01u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x23u, 0x11u, 0x1Fu, 0x11u, 0x31u, 0x7Fu, 0x61u, 0x17u, 0xBFu, 0x8Cu, 0x8Fu, 0xFFu, 0x39u, 0x1Fu, 0x95u, 0x1Cu, - 0x1Fu, 0xFFu, 0x6Cu, 0x7Fu, 0x33u, 0x1Fu, 0x7Fu, 0xFFu, 0x44u, 0x13u, 0x11u, 0x11u, 0x13u, 0x81u, 0x7Cu, 0x12u, - 0x11u, 0xCCu, 0x16u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, + 0x43u, 0xFFu, 0x30u, 0xF0u, 0x22u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Fu, 0x5Fu, + 0x53u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x42u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0xF3u, + 0x1Fu, 0x15u, 0x11u, 0x13u, 0x13u, 0x41u, 0xF1u, 0x31u, 0x3Fu, 0x1Fu, 0x53u, 0x03u, 0xF0u, + 0x4Fu, 0xFFu, 0x2Fu, 0x13u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x23u, 0x11u, 0x1Fu, 0x11u, 0x31u, 0x7Fu, 0x61u, 0x17u, + 0xBFu, 0x8Cu, 0x8Fu, 0xFFu, 0x39u, 0x1Fu, 0x95u, 0x1Cu, 0x1Fu, 0xFFu, 0x6Cu, 0x7Fu, 0x33u, + 0x1Fu, 0x7Fu, 0xFFu, 0x44u, 0x13u, 0x11u, 0x11u, 0x13u, 0x81u, 0x7Cu, 0x12u, 0x11u, 0xCCu, + 0x16u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u }; -/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI0_VAL[] = +// UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI0_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI1_VAL[] = +// UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI1_VAL[] = { - 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x20u, 0xF1u, 0x0Fu, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x10u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x20u, 0xF1u, 0x0Fu, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, + 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Fu, + 0x11u, 0x11u, 0xD1u, 0x11u, 0x10u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI2_VAL[] = +// UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI2_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x0Au, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Au, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x13u, 0x0Au, 0x00u, 0x0Du, 0x16u, 0x1Fu, 0x11u, 0x1Fu, - 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0xF4u, 0xF0u, 0x10u, 0x10u, 0x50u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x01u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x12u, 0x11u, 0xBFu, 0x11u, 0x11u, 0x1Du, 0x01u, 0x11u, 0x12u, 0x11u, 0x11u, 0x01u, 0xF1u, 0x10u, - 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, - 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x0Au, 0x0Au, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x13u, 0x0Au, + 0x00u, 0x0Du, 0x16u, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0xF4u, 0xF0u, 0x10u, 0x10u, 0x50u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x01u, + 0x11u, 0x11u, 0x11u, 0xF1u, 0x12u, 0x11u, 0xBFu, 0x11u, 0x11u, 0x1Du, 0x01u, 0x11u, 0x12u, + 0x11u, 0x11u, 0x01u, 0xF1u, 0x10u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI3_VAL[] = +// UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI3_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x03u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x03u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI4_VAL[] = +// UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI4_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI5_VAL[] = +// UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI5_VAL[] = { - 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI6_VAL[] = +// UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI6_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, 0x03u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, 0x03u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI7_VAL[] = +// UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI7_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x0Au, 0x1Fu, 0x08u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x02u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, 0x10u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, + 0x0Au, 0x1Fu, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x02u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x10u, 0x11u, 0x10u, 0x11u, 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u }; -/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ +// UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 static const uint8 CYCODE BS_UDB_DSI8_VAL[] = { - 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0xF0u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x1Du, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0xF0u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x1Du, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI9_VAL[] = +// UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI9_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI10_VAL[] = +// UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI10_VAL[] = { - 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x0Cu, 0x1Fu, 0x03u, 0x06u, 0x1Fu, 0x1Fu, 0x05u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, 0x00u, 0xF0u, 0x00u, 0x00u, 0x00u, 0xFFu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0xD1u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x0Cu, + 0x1Fu, 0x03u, 0x06u, 0x1Fu, 0x1Fu, 0x05u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, 0x00u, 0xF0u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0xD1u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI11_VAL[] = +// UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI11_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u }; -static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), BS_UDB_UDBPAIR4_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), BS_UDB_UDBPAIR3_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), BS_UDB_UDBPAIR0_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), BS_UDB_UDBPAIR1_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), BS_UDB_UDBPAIR0_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, + +static const cfg_memcpy_t CYCODE cfg_memcpy_list[] = +{ + // dest, src, size + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), BS_UDB_UDBPAIR4_UDBSNG0_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), BS_UDB_UDBPAIR3_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), BS_UDB_UDBPAIR0_UDBSNG0_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), BS_UDB_UDBPAIR1_UDBSNG0_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), BS_UDB_UDBPAIR0_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u }, }; +//-------------------------------------------------------------------------------------------------- +// SDIO_Host_Config_TriggerMuxes +//-------------------------------------------------------------------------------------------------- void SDIO_Host_Config_TriggerMuxes(void) { - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + // Connect UDB to DMA + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, + TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, + TRIGGER_TYPE_LEVEL); } + +//-------------------------------------------------------------------------------------------------- +// SDIO_Host_Config_UDBs +//-------------------------------------------------------------------------------------------------- void SDIO_Host_Config_UDBs(void) { - size_t i; + size_t i; - /* Power on the UDB array */ - CY_SET_REG32(0x402101F0u, 0x05FA0003u); + // Power on the UDB array + CY_SET_REG32(0x402101F0u, 0x05FA0003u); - /* Zero out critical memory blocks before beginning configuration */ - for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - { - const cfg_memset_t *ms = &cfg_memset_list[i]; - CYMEMZERO(ms->address, ms->size); - } + // Zero out critical memory blocks before beginning configuration + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t* ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, ms->size); + } - /* Copy device configuration data into registers */ - for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) - { - const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; - CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); - } + // Copy device configuration data into registers + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t* mc = &cfg_memcpy_list[i]; + CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); + } - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ - CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); + // UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL + CY_SET_REG32((void*)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); - /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C4C4Cu); + // UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C4C4Cu); - /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x4C4C444Cu); + // UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x4C4C444Cu); - /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x044C4C44u); + // UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x044C4C44u); - /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C4Cu); + // UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C4Cu); - /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x004C4C44u); + // UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x004C4C44u); - /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x0C4C040Cu); + // UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x0C4C040Cu); - /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x008C8C8Cu); + // UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x008C8C8Cu); - /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + // UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x4C4C444Cu); + // UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x4C4C444Cu); - /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x008C808Cu); + // UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x008C808Cu); - /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x8C8C0404u); + // UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x8C8C0404u); - /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x048F808Fu); + // UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x048F808Fu); - /* Enable UDB array and digital routing */ - CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); + // Enable UDB array and digital routing + CY_SET_REG32((void*)0x40347900u, CY_GET_REG32((void*)0x40347900u) | 0x106u); } + #if defined(__cplusplus) } #endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h old mode 100644 new mode 100755 index 39febda573..63db9e4c1c --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h @@ -1,29 +1,28 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.h -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file COMPONENT_UDB_SDIO_P2/SDIO_HOST_cfg.h + * + * \brief + * This file provides the configuration of the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ -#if !defined(CY_SDIO_CFG_H) -#define CY_SDIO_CFG_H +#pragma once #include @@ -95,10 +94,10 @@ extern "C" { #define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u -/*************Defines for UDBs from Creator*****************************/ -/***********These come for cyfitter.h**********************************/ +// *************Defines for UDBs from Creator***************************** +// ***********These come for cyfitter.h********************************** -/* TFT_DMA */ +// TFT_DMA #define TFT_DMA_DW__BLOCK_HW DW0 #define TFT_DMA_DW__BLOCK_NUMBER 0u #define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2 @@ -106,7 +105,7 @@ extern "C" { #define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2 #define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2 -/* TFT_CTRL */ +// TFT_CTRL #define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u #define TFT_CTRL_Sync_ctrl_reg__0__POS 0 #define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u @@ -137,7 +136,7 @@ extern "C" { #define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u #define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u -/* SDIO_HOST */ +// SDIO_HOST #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu @@ -830,75 +829,75 @@ extern "C" { #define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 -/***************************CMD DMA***************************************/ +// ***************************CMD DMA*************************************** #define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) #define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) #define SDIO_HOST_CMD_DMA_HW (DW0) #define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_CMD_DMA_PRIORITY (1u) #define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; -/***************************Read DMA***************************************/ +// ***************************Read DMA*************************************** #define SDIO_HOST_Read_DMA_DW_BLOCK (1u) #define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) #define SDIO_HOST_Read_DMA_HW (DW1) #define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Read_DMA_PRIORITY (0u) #define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Read_DMA_PREEMPTABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; -/***************************Resp DMA***************************************/ +// ***************************Resp DMA*************************************** #define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) #define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) #define SDIO_HOST_Resp_DMA_HW (DW0) #define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Resp_DMA_PRIORITY (1u) #define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; -/***************************Write DMA***************************************/ +// ***************************Write DMA*************************************** #define SDIO_HOST_Write_DMA_DW_BLOCK (1u) #define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) #define SDIO_HOST_Write_DMA_HW (DW1) #define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Write_DMA_PRIORITY (0u) #define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Write_DMA_PREEMPTABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; -/***************************SDIO Clock**************************************/ -/* The peripheral clock divider number */ +// ***************************SDIO Clock************************************** +// The peripheral clock divider number #define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0) -/* The peripheral clock divider type */ +// The peripheral clock divider type #define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) -/*Function for configuring TriggerMuxes*/ +// Function for configuring TriggerMuxes void SDIO_Host_Config_TriggerMuxes(void); -/*Function for configuring UDBs*/ +// Function for configuring UDBs void SDIO_Host_Config_UDBs(void); -/* SDIO_HOST_Read_Int */ +// SDIO_HOST_Read_Int #define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Read_Int__INTC_NUMBER 69u @@ -906,7 +905,7 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Read_Int_INTC_NUMBER 69u -/* SDIO_HOST_sdio_int */ +// SDIO_HOST_sdio_int #define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_sdio_int__INTC_NUMBER 122u @@ -914,7 +913,7 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_sdio_int_INTC_NUMBER 122u -/* SDIO_HOST_Write_Int */ +// SDIO_HOST_Write_Int #define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Write_Int__INTC_NUMBER 67u @@ -922,10 +921,9 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Write_Int_INTC_NUMBER 67u +// ****************************SDIO Port************************************** +#define SDIO_HOST_GPIO_PORT GPIO_PRT2 + #if defined(__cplusplus) } #endif - -#endif /* !defined(CY_SDIO_CFG_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c old mode 100644 new mode 100755 index bd16a5fff7..c3b4ec4f59 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c @@ -1,26 +1,26 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.c -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.c + * + * \brief + * This file provides the configuration of the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #include "SDIO_HOST_cfg.h" @@ -53,11 +53,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -86,11 +86,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -119,11 +119,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -152,11 +152,11 @@ cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = { - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, .nextPtr = 0UL }; @@ -180,9 +180,9 @@ cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") -#else +#else // if defined(__GNUC__) || defined(__ARMCC_VERSION) #error Unsupported toolchain -#endif +#endif // if defined(__GNUC__) || defined(__ARMCC_VERSION) #ifndef CYCODE @@ -194,27 +194,41 @@ cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); +static void CYMEMZERO(void* s, size_t n); CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYMEMZERO +//-------------------------------------------------------------------------------------------------- +static void CYMEMZERO(void* s, size_t n) { (void)memset(s, 0, n); } + + CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); +static void CYCONFIGCPY(void* dest, const void* src, size_t n); CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYCONFIGCPY +//-------------------------------------------------------------------------------------------------- +static void CYCONFIGCPY(void* dest, const void* src, size_t n) { (void)memcpy(dest, src, n); } + + CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +static void CYCONFIGCPYCODE(void* dest, const void* src, size_t n); CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +//-------------------------------------------------------------------------------------------------- +// CYCONFIGCPYCODE +//-------------------------------------------------------------------------------------------------- +static void CYCONFIGCPYCODE(void* dest, const void* src, size_t n) { (void)memcpy(dest, src, n); } + CYPACKED typedef struct { uint8 offset; @@ -238,799 +252,912 @@ CYPACKED typedef struct *******************************************************************************/ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +//-------------------------------------------------------------------------------------------------- +// cfg_write_bytes32 +//-------------------------------------------------------------------------------------------------- static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) { - /* For 32-bit little-endian architectures */ + // For 32-bit little-endian architectures uint32 i, j = 0u; for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) { uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; + uint8 count = (uint8)baseAddr; baseAddr &= 0xFFFFFF00u; while (count != 0u) { - CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + CY_SET_REG8((void*)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } } } -static const uint32 CYCODE cy_cfg_addr_table[] = + +static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40340002u, /* Base address: 0x40340000 Count: 2 */ - 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ - 0x40340301u, /* Base address: 0x40340300 Count: 1 */ - 0x40340405u, /* Base address: 0x40340400 Count: 5 */ - 0x4034205Cu, /* Base address: 0x40342000 Count: 92 */ - 0x40342238u, /* Base address: 0x40342200 Count: 56 */ - 0x4034242Cu, /* Base address: 0x40342400 Count: 44 */ - 0x4034262Eu, /* Base address: 0x40342600 Count: 46 */ - 0x40342837u, /* Base address: 0x40342800 Count: 55 */ - 0x40342A29u, /* Base address: 0x40342A00 Count: 41 */ - 0x40347104u, /* Base address: 0x40347100 Count: 4 */ - 0x40347804u, /* Base address: 0x40347800 Count: 4 */ + 0x40340002u, // Base address: 0x40340000 Count: 2 + 0x4034010Au, // Base address: 0x40340100 Count: 10 + 0x40340301u, // Base address: 0x40340300 Count: 1 + 0x40340405u, // Base address: 0x40340400 Count: 5 + 0x4034205Cu, // Base address: 0x40342000 Count: 92 + 0x40342238u, // Base address: 0x40342200 Count: 56 + 0x4034242Cu, // Base address: 0x40342400 Count: 44 + 0x4034262Eu, // Base address: 0x40342600 Count: 46 + 0x40342837u, // Base address: 0x40342800 Count: 55 + 0x40342A29u, // Base address: 0x40342A00 Count: 41 + 0x40347104u, // Base address: 0x40347100 Count: 4 + 0x40347804u, // Base address: 0x40347800 Count: 4 }; -static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = +static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - {0x00u, 0xFFu}, - {0x09u, 0x01u}, - {0x09u, 0x01u}, - {0x0Du, 0x02u}, - {0x10u, 0x10u}, - {0x14u, 0x88u}, - {0x18u, 0x10u}, - {0x1Cu, 0x88u}, - {0x20u, 0x10u}, - {0x24u, 0x88u}, - {0x28u, 0x10u}, - {0x2Cu, 0x88u}, - {0x19u, 0x40u}, - {0x10u, 0x07u}, - {0x18u, 0x47u}, - {0x24u, 0x03u}, - {0x28u, 0x0Fu}, - {0x2Cu, 0x2Fu}, - {0x00u, 0x01u}, - {0x0Eu, 0x0Eu}, - {0x10u, 0x08u}, - {0x18u, 0x01u}, - {0x1Au, 0x08u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x22u, 0x01u}, - {0x28u, 0x01u}, - {0x2Au, 0x04u}, - {0x2Eu, 0x01u}, - {0x30u, 0x0Fu}, - {0x3Cu, 0x02u}, - {0x40u, 0x63u}, - {0x41u, 0x04u}, - {0x42u, 0x10u}, - {0x44u, 0x02u}, - {0x45u, 0x0Fu}, - {0x46u, 0xECu}, - {0x47u, 0xB0u}, - {0x48u, 0x2Du}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x02u}, - {0x4Fu, 0x0Cu}, - {0x50u, 0x08u}, - {0x51u, 0x10u}, - {0x5Cu, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x65u, 0x08u}, - {0x68u, 0xC0u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x71u, 0x10u}, - {0x72u, 0x50u}, - {0x73u, 0xA8u}, - {0x81u, 0x01u}, - {0x83u, 0x02u}, - {0x85u, 0x02u}, - {0x89u, 0x02u}, - {0x8Du, 0x02u}, - {0x91u, 0x30u}, - {0x93u, 0x04u}, - {0x95u, 0x06u}, - {0x97u, 0x38u}, - {0x99u, 0x20u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x10u}, - {0x9Du, 0x06u}, - {0x9Fu, 0x38u}, - {0xA3u, 0x02u}, - {0xA5u, 0x02u}, - {0xA6u, 0x01u}, - {0xABu, 0x01u}, - {0xB1u, 0x01u}, - {0xB2u, 0x01u}, - {0xB3u, 0x20u}, - {0xB5u, 0x10u}, - {0xB7u, 0x0Eu}, - {0xBDu, 0x80u}, - {0xBEu, 0x04u}, - {0xBFu, 0x14u}, - {0xC0u, 0x54u}, - {0xC1u, 0x06u}, - {0xC2u, 0x32u}, - {0xC6u, 0xF0u}, - {0xC7u, 0x0Eu}, - {0xC8u, 0x18u}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCFu, 0x2Fu}, - {0xD0u, 0x08u}, - {0xD1u, 0x10u}, - {0xDCu, 0x04u}, - {0xDDu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xDFu, 0x04u}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE6u, 0x08u}, - {0xE7u, 0x03u}, - {0xE8u, 0x08u}, - {0xEAu, 0x18u}, - {0xEBu, 0x03u}, - {0xF0u, 0x58u}, - {0xF1u, 0xECu}, - {0x00u, 0x18u}, - {0x01u, 0x15u}, - {0x03u, 0x20u}, - {0x04u, 0x43u}, - {0x06u, 0x34u}, - {0x07u, 0x35u}, - {0x08u, 0x40u}, - {0x0Cu, 0x5Au}, - {0x0Eu, 0x25u}, - {0x0Fu, 0x4Au}, - {0x11u, 0x20u}, - {0x13u, 0x15u}, - {0x14u, 0x40u}, - {0x15u, 0x40u}, - {0x17u, 0x0Au}, - {0x18u, 0x20u}, - {0x19u, 0x10u}, - {0x1Bu, 0x25u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x0Au}, - {0x1Fu, 0x40u}, - {0x20u, 0x20u}, - {0x21u, 0x0Cu}, - {0x23u, 0x03u}, - {0x24u, 0x40u}, - {0x2Au, 0x20u}, - {0x2Cu, 0x45u}, - {0x2Eu, 0x3Au}, - {0x30u, 0x40u}, - {0x32u, 0x0Eu}, - {0x33u, 0x70u}, - {0x34u, 0x01u}, - {0x35u, 0x0Cu}, - {0x36u, 0x31u}, - {0x37u, 0x03u}, - {0x3Au, 0xA8u}, - {0x3Cu, 0xA8u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x54u}, - {0x40u, 0x42u}, - {0x41u, 0x05u}, - {0x45u, 0x20u}, - {0x46u, 0x06u}, - {0x48u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Du, 0xA0u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x66u, 0x40u}, - {0x67u, 0x40u}, - {0x68u, 0x10u}, - {0x69u, 0x50u}, - {0x02u, 0x60u}, - {0x08u, 0x87u}, - {0x0Au, 0x78u}, - {0x0Eu, 0x08u}, - {0x12u, 0x21u}, - {0x14u, 0x04u}, - {0x18u, 0xB9u}, - {0x1Au, 0x06u}, - {0x1Cu, 0x89u}, - {0x1Eu, 0x72u}, - {0x20u, 0x04u}, - {0x24u, 0x8Eu}, - {0x26u, 0x51u}, - {0x2Au, 0x04u}, - {0x2Eu, 0x01u}, - {0x30u, 0x80u}, - {0x34u, 0x7Fu}, - {0x3Au, 0x20u}, - {0x3Cu, 0x20u}, - {0x3Eu, 0x01u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x44u, 0x01u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x77u}, - {0x5Cu, 0x0Cu}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x80u, 0x40u}, - {0x84u, 0x8Eu}, - {0x86u, 0x71u}, - {0x88u, 0x40u}, - {0x8Eu, 0x21u}, - {0x90u, 0x40u}, - {0x92u, 0x02u}, - {0x96u, 0x18u}, - {0x98u, 0x03u}, - {0x9Au, 0x04u}, - {0x9Cu, 0xCCu}, - {0x9Eu, 0x33u}, - {0xA0u, 0x08u}, - {0xA4u, 0x40u}, - {0xA8u, 0x46u}, - {0xAAu, 0xB1u}, - {0xACu, 0x10u}, - {0xAEu, 0x08u}, - {0xB2u, 0xF8u}, - {0xB4u, 0x07u}, - {0xB6u, 0x07u}, - {0xBAu, 0xA8u}, - {0xBCu, 0xA8u}, - {0xC0u, 0x43u}, - {0xC1u, 0x02u}, - {0xC4u, 0x01u}, - {0xC5u, 0x40u}, - {0xC6u, 0xB0u}, - {0xC8u, 0x0Au}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x13u}, - {0xCDu, 0x5Cu}, - {0xCEu, 0x77u}, - {0xDCu, 0x0Cu}, - {0xDEu, 0x0Cu}, - {0xE3u, 0x09u}, - {0xE4u, 0x50u}, - {0xE5u, 0xA8u}, - {0xE9u, 0x1Cu}, - {0xEAu, 0x58u}, - {0xEBu, 0xA1u}, - {0xEDu, 0x10u}, - {0xF0u, 0x10u}, - {0xF1u, 0x1Du}, - {0x00u, 0x40u}, - {0x01u, 0x14u}, - {0x03u, 0x20u}, - {0x04u, 0x33u}, - {0x05u, 0x3Cu}, - {0x06u, 0x44u}, - {0x08u, 0x97u}, - {0x09u, 0x3Cu}, - {0x0Au, 0x48u}, - {0x0Du, 0x01u}, - {0x11u, 0x03u}, - {0x12u, 0x91u}, - {0x15u, 0x03u}, - {0x16u, 0x08u}, - {0x1Bu, 0x03u}, - {0x1Cu, 0x13u}, - {0x1Eu, 0xECu}, - {0x1Fu, 0x03u}, - {0x20u, 0xADu}, - {0x21u, 0x04u}, - {0x22u, 0x52u}, - {0x27u, 0x2Cu}, - {0x29u, 0x02u}, - {0x2Eu, 0x12u}, - {0x2Fu, 0x04u}, - {0x30u, 0x07u}, - {0x31u, 0x18u}, - {0x33u, 0x07u}, - {0x34u, 0xF8u}, - {0x35u, 0x20u}, - {0x39u, 0x02u}, - {0x3Au, 0x22u}, - {0x3Cu, 0x22u}, - {0x3Fu, 0x15u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x44u, 0x06u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x5Cu, 0x0Cu}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0x01u, 0x20u}, - {0x0Bu, 0x40u}, - {0x0Du, 0x10u}, - {0x11u, 0x32u}, - {0x13u, 0x09u}, - {0x15u, 0x0Au}, - {0x17u, 0x31u}, - {0x23u, 0x34u}, - {0x29u, 0x33u}, - {0x2Bu, 0x08u}, - {0x2Du, 0x0Cu}, - {0x31u, 0x0Cu}, - {0x33u, 0x01u}, - {0x35u, 0x02u}, - {0x37u, 0x70u}, - {0x39u, 0x02u}, - {0x3Fu, 0x55u}, - {0x40u, 0x16u}, - {0x41u, 0x02u}, - {0x44u, 0x04u}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x12u}, - {0x4Du, 0x5Cu}, - {0x4Eu, 0x78u}, - {0x57u, 0x02u}, - {0x58u, 0x76u}, - {0x5Du, 0x04u}, - {0x5Eu, 0x0Cu}, - {0x5Fu, 0x0Cu}, - {0x62u, 0x08u}, - {0x63u, 0x09u}, - {0x64u, 0x50u}, - {0x65u, 0xA8u}, - {0x69u, 0x1Cu}, - {0x6Au, 0x58u}, - {0x6Bu, 0xA1u}, - {0x6Du, 0x10u}, - {0x70u, 0x10u}, - {0x71u, 0x1Du}, - {0xE8u, 0x63u}, - {0xECu, 0x53u}, - {0xF0u, 0x54u}, - {0xF4u, 0x01u}, - {0x00u, 0x01u}, - {0x10u, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x01u}, + { 0x00u, 0xFFu }, + { 0x09u, 0x01u }, + { 0x09u, 0x01u }, + { 0x0Du, 0x02u }, + { 0x10u, 0x10u }, + { 0x14u, 0x88u }, + { 0x18u, 0x10u }, + { 0x1Cu, 0x88u }, + { 0x20u, 0x10u }, + { 0x24u, 0x88u }, + { 0x28u, 0x10u }, + { 0x2Cu, 0x88u }, + { 0x19u, 0x40u }, + { 0x10u, 0x07u }, + { 0x18u, 0x47u }, + { 0x24u, 0x03u }, + { 0x28u, 0x0Fu }, + { 0x2Cu, 0x2Fu }, + { 0x00u, 0x01u }, + { 0x0Eu, 0x0Eu }, + { 0x10u, 0x08u }, + { 0x18u, 0x01u }, + { 0x1Au, 0x08u }, + { 0x1Cu, 0x01u }, + { 0x1Eu, 0x02u }, + { 0x22u, 0x01u }, + { 0x28u, 0x01u }, + { 0x2Au, 0x04u }, + { 0x2Eu, 0x01u }, + { 0x30u, 0x0Fu }, + { 0x3Cu, 0x02u }, + { 0x40u, 0x63u }, + { 0x41u, 0x04u }, + { 0x42u, 0x10u }, + { 0x44u, 0x02u }, + { 0x45u, 0x0Fu }, + { 0x46u, 0xECu }, + { 0x47u, 0xB0u }, + { 0x48u, 0x2Du }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x02u }, + { 0x4Fu, 0x0Cu }, + { 0x50u, 0x08u }, + { 0x51u, 0x10u }, + { 0x5Cu, 0x0Cu }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x65u, 0x08u }, + { 0x68u, 0xC0u }, + { 0x6Cu, 0x10u }, + { 0x6Du, 0x11u }, + { 0x6Eu, 0x40u }, + { 0x6Fu, 0x01u }, + { 0x71u, 0x10u }, + { 0x72u, 0x50u }, + { 0x73u, 0xA8u }, + { 0x81u, 0x01u }, + { 0x83u, 0x02u }, + { 0x85u, 0x02u }, + { 0x89u, 0x02u }, + { 0x8Du, 0x02u }, + { 0x91u, 0x30u }, + { 0x93u, 0x04u }, + { 0x95u, 0x06u }, + { 0x97u, 0x38u }, + { 0x99u, 0x20u }, + { 0x9Au, 0x01u }, + { 0x9Bu, 0x10u }, + { 0x9Du, 0x06u }, + { 0x9Fu, 0x38u }, + { 0xA3u, 0x02u }, + { 0xA5u, 0x02u }, + { 0xA6u, 0x01u }, + { 0xABu, 0x01u }, + { 0xB1u, 0x01u }, + { 0xB2u, 0x01u }, + { 0xB3u, 0x20u }, + { 0xB5u, 0x10u }, + { 0xB7u, 0x0Eu }, + { 0xBDu, 0x80u }, + { 0xBEu, 0x04u }, + { 0xBFu, 0x14u }, + { 0xC0u, 0x54u }, + { 0xC1u, 0x06u }, + { 0xC2u, 0x32u }, + { 0xC6u, 0xF0u }, + { 0xC7u, 0x0Eu }, + { 0xC8u, 0x18u }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCFu, 0x2Fu }, + { 0xD0u, 0x08u }, + { 0xD1u, 0x10u }, + { 0xDCu, 0x04u }, + { 0xDDu, 0x0Cu }, + { 0xDEu, 0x0Cu }, + { 0xDFu, 0x04u }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE6u, 0x08u }, + { 0xE7u, 0x03u }, + { 0xE8u, 0x08u }, + { 0xEAu, 0x18u }, + { 0xEBu, 0x03u }, + { 0xF0u, 0x58u }, + { 0xF1u, 0xECu }, + { 0x00u, 0x18u }, + { 0x01u, 0x15u }, + { 0x03u, 0x20u }, + { 0x04u, 0x43u }, + { 0x06u, 0x34u }, + { 0x07u, 0x35u }, + { 0x08u, 0x40u }, + { 0x0Cu, 0x5Au }, + { 0x0Eu, 0x25u }, + { 0x0Fu, 0x4Au }, + { 0x11u, 0x20u }, + { 0x13u, 0x15u }, + { 0x14u, 0x40u }, + { 0x15u, 0x40u }, + { 0x17u, 0x0Au }, + { 0x18u, 0x20u }, + { 0x19u, 0x10u }, + { 0x1Bu, 0x25u }, + { 0x1Cu, 0x40u }, + { 0x1Du, 0x0Au }, + { 0x1Fu, 0x40u }, + { 0x20u, 0x20u }, + { 0x21u, 0x0Cu }, + { 0x23u, 0x03u }, + { 0x24u, 0x40u }, + { 0x2Au, 0x20u }, + { 0x2Cu, 0x45u }, + { 0x2Eu, 0x3Au }, + { 0x30u, 0x40u }, + { 0x32u, 0x0Eu }, + { 0x33u, 0x70u }, + { 0x34u, 0x01u }, + { 0x35u, 0x0Cu }, + { 0x36u, 0x31u }, + { 0x37u, 0x03u }, + { 0x3Au, 0xA8u }, + { 0x3Cu, 0xA8u }, + { 0x3Eu, 0x01u }, + { 0x3Fu, 0x54u }, + { 0x40u, 0x42u }, + { 0x41u, 0x05u }, + { 0x45u, 0x20u }, + { 0x46u, 0x06u }, + { 0x48u, 0x06u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Du, 0xA0u }, + { 0x5Cu, 0x0Cu }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x66u, 0x40u }, + { 0x67u, 0x40u }, + { 0x68u, 0x10u }, + { 0x69u, 0x50u }, + { 0x02u, 0x60u }, + { 0x08u, 0x87u }, + { 0x0Au, 0x78u }, + { 0x0Eu, 0x08u }, + { 0x12u, 0x21u }, + { 0x14u, 0x04u }, + { 0x18u, 0xB9u }, + { 0x1Au, 0x06u }, + { 0x1Cu, 0x89u }, + { 0x1Eu, 0x72u }, + { 0x20u, 0x04u }, + { 0x24u, 0x8Eu }, + { 0x26u, 0x51u }, + { 0x2Au, 0x04u }, + { 0x2Eu, 0x01u }, + { 0x30u, 0x80u }, + { 0x34u, 0x7Fu }, + { 0x3Au, 0x20u }, + { 0x3Cu, 0x20u }, + { 0x3Eu, 0x01u }, + { 0x40u, 0x43u }, + { 0x41u, 0x02u }, + { 0x44u, 0x01u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x57u, 0x02u }, + { 0x58u, 0x77u }, + { 0x5Cu, 0x0Cu }, + { 0x5Eu, 0x0Cu }, + { 0x5Fu, 0x0Cu }, + { 0x62u, 0x08u }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0x80u, 0x40u }, + { 0x84u, 0x8Eu }, + { 0x86u, 0x71u }, + { 0x88u, 0x40u }, + { 0x8Eu, 0x21u }, + { 0x90u, 0x40u }, + { 0x92u, 0x02u }, + { 0x96u, 0x18u }, + { 0x98u, 0x03u }, + { 0x9Au, 0x04u }, + { 0x9Cu, 0xCCu }, + { 0x9Eu, 0x33u }, + { 0xA0u, 0x08u }, + { 0xA4u, 0x40u }, + { 0xA8u, 0x46u }, + { 0xAAu, 0xB1u }, + { 0xACu, 0x10u }, + { 0xAEu, 0x08u }, + { 0xB2u, 0xF8u }, + { 0xB4u, 0x07u }, + { 0xB6u, 0x07u }, + { 0xBAu, 0xA8u }, + { 0xBCu, 0xA8u }, + { 0xC0u, 0x43u }, + { 0xC1u, 0x02u }, + { 0xC4u, 0x01u }, + { 0xC5u, 0x40u }, + { 0xC6u, 0xB0u }, + { 0xC8u, 0x0Au }, + { 0xC9u, 0xFFu }, + { 0xCAu, 0xFFu }, + { 0xCBu, 0xFFu }, + { 0xCCu, 0x13u }, + { 0xCDu, 0x5Cu }, + { 0xCEu, 0x77u }, + { 0xDCu, 0x0Cu }, + { 0xDEu, 0x0Cu }, + { 0xE3u, 0x09u }, + { 0xE4u, 0x50u }, + { 0xE5u, 0xA8u }, + { 0xE9u, 0x1Cu }, + { 0xEAu, 0x58u }, + { 0xEBu, 0xA1u }, + { 0xEDu, 0x10u }, + { 0xF0u, 0x10u }, + { 0xF1u, 0x1Du }, + { 0x00u, 0x40u }, + { 0x01u, 0x14u }, + { 0x03u, 0x20u }, + { 0x04u, 0x33u }, + { 0x05u, 0x3Cu }, + { 0x06u, 0x44u }, + { 0x08u, 0x97u }, + { 0x09u, 0x3Cu }, + { 0x0Au, 0x48u }, + { 0x0Du, 0x01u }, + { 0x11u, 0x03u }, + { 0x12u, 0x91u }, + { 0x15u, 0x03u }, + { 0x16u, 0x08u }, + { 0x1Bu, 0x03u }, + { 0x1Cu, 0x13u }, + { 0x1Eu, 0xECu }, + { 0x1Fu, 0x03u }, + { 0x20u, 0xADu }, + { 0x21u, 0x04u }, + { 0x22u, 0x52u }, + { 0x27u, 0x2Cu }, + { 0x29u, 0x02u }, + { 0x2Eu, 0x12u }, + { 0x2Fu, 0x04u }, + { 0x30u, 0x07u }, + { 0x31u, 0x18u }, + { 0x33u, 0x07u }, + { 0x34u, 0xF8u }, + { 0x35u, 0x20u }, + { 0x39u, 0x02u }, + { 0x3Au, 0x22u }, + { 0x3Cu, 0x22u }, + { 0x3Fu, 0x15u }, + { 0x40u, 0x43u }, + { 0x41u, 0x02u }, + { 0x44u, 0x06u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x5Cu, 0x0Cu }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0x01u, 0x20u }, + { 0x0Bu, 0x40u }, + { 0x0Du, 0x10u }, + { 0x11u, 0x32u }, + { 0x13u, 0x09u }, + { 0x15u, 0x0Au }, + { 0x17u, 0x31u }, + { 0x23u, 0x34u }, + { 0x29u, 0x33u }, + { 0x2Bu, 0x08u }, + { 0x2Du, 0x0Cu }, + { 0x31u, 0x0Cu }, + { 0x33u, 0x01u }, + { 0x35u, 0x02u }, + { 0x37u, 0x70u }, + { 0x39u, 0x02u }, + { 0x3Fu, 0x55u }, + { 0x40u, 0x16u }, + { 0x41u, 0x02u }, + { 0x44u, 0x04u }, + { 0x49u, 0xFFu }, + { 0x4Au, 0xFFu }, + { 0x4Bu, 0xFFu }, + { 0x4Cu, 0x12u }, + { 0x4Du, 0x5Cu }, + { 0x4Eu, 0x78u }, + { 0x57u, 0x02u }, + { 0x58u, 0x76u }, + { 0x5Du, 0x04u }, + { 0x5Eu, 0x0Cu }, + { 0x5Fu, 0x0Cu }, + { 0x62u, 0x08u }, + { 0x63u, 0x09u }, + { 0x64u, 0x50u }, + { 0x65u, 0xA8u }, + { 0x69u, 0x1Cu }, + { 0x6Au, 0x58u }, + { 0x6Bu, 0xA1u }, + { 0x6Du, 0x10u }, + { 0x70u, 0x10u }, + { 0x71u, 0x1Du }, + { 0xE8u, 0x63u }, + { 0xECu, 0x53u }, + { 0xF0u, 0x54u }, + { 0xF4u, 0x01u }, + { 0x00u, 0x01u }, + { 0x10u, 0x01u }, + { 0x14u, 0x01u }, + { 0x18u, 0x01u }, }; -CYPACKED typedef struct +CYPACKED typedef struct { - void *address; + void* address; uint16 size; } CYPACKED_ATTR cfg_memset_t; -CYPACKED typedef struct +CYPACKED typedef struct { - void *dest; - const void *src; - size_t size; + void* dest; + const void* src; + size_t size; } CYPACKED_ATTR cfg_memcpy_t; -static const cfg_memset_t CYCODE cfg_memset_list[] = +static const cfg_memset_t CYCODE cfg_memset_list[] = { - /* address, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, + // address, size + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u }, }; -/* UDB_UDBPAIR5_UDBSNG1 Address: CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_UDBSNG1_VAL[] = { - 0x08u, 0x00u, 0x00u, 0x00u, 0x42u, 0x00u, 0x2Du, 0x00u, 0x08u, 0x24u, 0x00u, 0x00u, 0x22u, 0x24u, 0x45u, 0x00u, - 0x00u, 0x10u, 0x10u, 0x08u, 0x00u, 0x70u, 0x00u, 0x83u, 0x08u, 0x24u, 0x00u, 0x00u, 0x00u, 0x4Eu, 0x00u, 0xB0u, - 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x8Fu, 0x3Cu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, - 0x00u, 0xC0u, 0x00u, 0x1Fu, 0x60u, 0x00u, 0x1Fu, 0x20u, 0x80u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x10u, 0x41u, - 0x46u, 0x02u, 0x00u, 0x00u, 0x05u, 0x00u, 0x04u, 0x0Bu, 0x14u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = { - 0x08u, 0x0Au, 0x00u, 0xD0u, 0x02u, 0xB9u, 0x00u, 0x42u, 0x2Bu, 0x02u, 0x00u, 0x00u, 0x2Bu, 0x00u, 0x54u, 0x80u, - 0x2Au, 0x00u, 0x01u, 0x20u, 0x40u, 0x33u, 0x00u, 0xCCu, 0x04u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0xA0u, - 0x2Au, 0x00u, 0x00u, 0x00u, 0x01u, 0x8Au, 0x2Au, 0x71u, 0x20u, 0x7Bu, 0x00u, 0x80u, 0x00u, 0x04u, 0x00u, 0x00u, - 0x19u, 0xF8u, 0x07u, 0xF8u, 0x00u, 0x00u, 0x61u, 0x07u, 0x8Au, 0x80u, 0x00u, 0x0Au, 0x00u, 0x0Au, 0x45u, 0x40u, - 0x52u, 0x06u, 0x00u, 0x00u, 0x04u, 0x4Cu, 0x0Eu, 0x00u, 0x07u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, - 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, - 0x40u, 0x03u, 0x00u, 0x10u}; - -/* UDB_UDBPAIR4_UDBSNG1 Address: CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x00u, 0x19u, 0x00u, 0x12u, 0x00u, 0x2Du, 0x00u, 0x04u, 0x00u, 0x00u, 0x11u, - 0x02u, 0x08u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x05u, 0x00u, 0x03u, 0x10u, 0x08u, - 0x15u, 0x00u, 0x2Au, 0x10u, 0x00u, 0x00u, 0x04u, 0x00u, 0x0Eu, 0x0Fu, 0x31u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x07u, 0x00u, 0x10u, 0x3Fu, 0x00u, 0x3Fu, 0x0Cu, 0x00u, 0x00u, 0xA0u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x04u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x06u, 0x40u, 0xB0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR3_UDBSNG0 Address: CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG0_VAL[] = { - 0x3Cu, 0x00u, 0x00u, 0xC0u, 0x00u, 0x80u, 0x10u, 0x40u, 0x0Cu, 0x80u, 0x60u, 0x40u, 0x02u, 0x10u, 0x00u, 0x25u, - 0x04u, 0x80u, 0x08u, 0x40u, 0x00u, 0x19u, 0x10u, 0x22u, 0x04u, 0x00u, 0x0Bu, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x80u, - 0x10u, 0x00u, 0x00u, 0x24u, 0x00u, 0x40u, 0x00u, 0x80u, 0x7Cu, 0x25u, 0x00u, 0x1Au, 0x00u, 0x08u, 0x10u, 0x80u, - 0x01u, 0xC0u, 0x02u, 0x00u, 0x70u, 0x07u, 0x0Cu, 0x38u, 0x00u, 0x00u, 0x80u, 0x82u, 0x00u, 0xA2u, 0x04u, 0x00u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xDEu, 0x40u, 0x4Bu, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR2_UDBSNG1 Address: CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE Size (bytes): 116 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_UDBSNG1_VAL[] = { - 0x00u, 0x00u, 0x80u, 0x03u, 0x00u, 0xC9u, 0x00u, 0x12u, 0x00u, 0x00u, 0x00u, 0x01u, 0x70u, 0x01u, 0x00u, 0x80u, - 0x40u, 0x00u, 0x00u, 0x40u, 0x40u, 0xB3u, 0xAAu, 0x4Cu, 0xEAu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x40u, - 0x40u, 0xB1u, 0xAAu, 0x04u, 0x43u, 0x00u, 0x00u, 0x01u, 0x4Cu, 0x05u, 0x00u, 0xBAu, 0x00u, 0x20u, 0x40u, 0x80u, - 0x03u, 0x7Fu, 0xC0u, 0x80u, 0x0Cu, 0x7Fu, 0x30u, 0x00u, 0xA2u, 0x00u, 0x08u, 0x22u, 0x08u, 0x22u, 0x51u, 0x04u, - 0x43u, 0x02u, 0x00u, 0x00u, 0x05u, 0xB0u, 0x40u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, - 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, - 0x10u, 0x1Du, 0x00u, 0x00u}; - -/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = { - 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF5u, 0x7Fu, 0xF3u, 0x11u, - 0xF3u, 0x11u, 0xFFu, 0xF2u, 0xFFu, 0x2Fu, 0xFFu, 0xFFu, 0x00u, 0x11u, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF7u, 0x5Fu, 0xFFu, 0x2Fu, 0x10u, 0x22u, 0x62u, 0x00u, 0x34u, - 0x2Fu, 0x62u, 0x73u, 0x00u, 0x11u, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x0Fu, 0x0Fu, 0x27u, - 0x20u, 0x22u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x11u, 0x40u, 0x1Du, 0x11u, 0x00u, 0xDDu, 0x11u, 0x10u, 0x10u, 0x11u, 0x00u, 0xD1u, 0x63u, 0x03u, 0x01u, - 0x13u, 0x37u, 0x00u, 0x13u, 0x11u, 0x00u, 0x13u, 0x16u, 0x11u, 0x11u, 0x16u, 0x19u, 0x11u, 0x01u, 0x11u, 0x11u, - 0x19u, 0x11u, 0x11u, 0x91u, 0x41u, 0x11u, 0x21u, 0x11u, 0x16u, 0x11u, 0x11u, 0x13u, 0x81u, 0x11u, 0x11u, 0x11u}; - -/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = { - 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x42u, 0x36u, - 0x26u, 0x33u, 0x35u, 0xF5u, 0xF0u, 0x54u, 0x14u, 0x62u, 0x5Fu, 0x0Fu, 0x04u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x24u, 0x45u, 0x7Fu, 0x50u, 0x26u, 0x64u, 0xFFu, 0x3Fu, 0x32u, 0x42u, 0xF3u, 0x32u, - 0x3Fu, 0x7Fu, 0x37u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x02u, 0x05u, - 0xF6u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x13u, 0xF0u, 0x10u, 0x14u, 0x00u, 0x01u, 0x01u, 0x10u, 0x0Du, 0x63u, 0x00u, 0x70u, 0x10u, 0x08u, 0x30u, - 0x13u, 0x11u, 0x30u, 0x10u, 0x50u, 0x30u, 0x1Fu, 0xC1u, 0x33u, 0x10u, 0x0Fu, 0x01u, 0x31u, 0x0Du, 0x1Cu, 0x25u, - 0x11u, 0x01u, 0x12u, 0xFBu, 0x02u, 0x12u, 0x15u, 0x1Cu, 0x11u, 0x11u, 0x11u, 0x15u, 0x11u, 0x61u, 0x16u, 0x11u}; - -/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = { - 0x06u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, 0x33u, 0x35u, 0x44u, - 0x77u, 0x57u, 0xF2u, 0xFFu, 0xF4u, 0xFFu, 0x40u, 0xFFu, 0x32u, 0x63u, 0xFFu, 0xFFu, 0x3Fu, 0x5Fu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x34u, 0x13u, 0x46u, 0x56u, 0x35u, 0x41u, 0x40u, 0x57u, 0x67u, 0x55u, - 0x3Fu, 0x63u, 0xF6u, 0xFFu, 0x4Fu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x00u, 0x00u, - 0x40u, 0x22u, 0x00u, 0xF0u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x10u, 0x11u, 0xF3u, 0x10u, 0x12u, 0x02u, 0x96u, 0x01u, 0x00u, 0x74u, 0xD1u, 0x00u, 0xF7u, 0x03u, 0x03u, 0x16u, - 0x1Fu, 0x31u, 0x10u, 0x00u, 0x03u, 0x10u, 0x41u, 0x35u, 0x10u, 0x16u, 0x0Fu, 0x76u, 0x11u, 0xB0u, 0xD1u, 0xDFu, - 0x09u, 0x00u, 0x0Fu, 0xFBu, 0x01u, 0x11u, 0x17u, 0x11u, 0x11u, 0x15u, 0xD5u, 0x1Du, 0x27u, 0x15u, 0x1Fu, 0x11u}; - -/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x41u, 0x53u, 0x15u, - 0x45u, 0x11u, 0xF4u, 0xF3u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0x33u, 0x63u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x31u, 0x02u, 0x14u, 0x56u, 0xF1u, 0x77u, 0x77u, 0x37u, 0xF0u, 0x56u, 0x73u, 0x45u, - 0x33u, 0x63u, 0xFFu, 0x03u, 0x15u, 0xF2u, 0xF2u, 0xF2u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xB0u, 0x00u, 0xF0u, 0x17u, 0x1Fu, 0x02u, 0x1Fu, 0x60u, 0xA3u, 0xF4u, 0x15u, 0xA0u, 0xF1u, 0x0Fu, 0x00u, 0x31u, - 0x0Fu, 0xF3u, 0x3Au, 0x20u, 0x51u, 0x3Au, 0x13u, 0xF3u, 0xC0u, 0x10u, 0x4Au, 0x11u, 0x20u, 0x10u, 0x01u, 0xF1u, - 0x0Fu, 0x00u, 0x0Fu, 0xFFu, 0x41u, 0x11u, 0x41u, 0x4Du, 0x11u, 0x71u, 0x11u, 0x1Fu, 0xFCu, 0x11u, 0x1Fu, 0x1Cu}; - -/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = { - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, 0xF4u, 0x55u, 0x4Fu, - 0xF3u, 0x5Fu, 0x55u, 0x27u, 0x31u, 0x63u, 0x71u, 0x61u, 0x3Fu, 0x63u, 0x0Fu, 0x5Fu, 0xFFu, 0xFFu, 0xFFu, 0x12u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x64u, 0x31u, 0x70u, 0x77u, 0xF6u, 0x2Fu, 0x1Fu, 0x25u, 0x4Fu, 0xF7u, 0x3Fu, - 0x32u, 0x63u, 0x3Fu, 0x75u, 0xF4u, 0x1Fu, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, - 0x04u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0x70u, 0x30u, 0x26u, 0x14u, 0x2Fu, 0x0Cu, 0xA5u, 0x10u, 0x18u, 0x11u, 0x0Fu, 0xF0u, 0xF7u, 0x3Fu, 0x00u, 0x11u, - 0x0Fu, 0xFFu, 0xF8u, 0x16u, 0xF7u, 0x1Fu, 0x10u, 0x11u, 0xF4u, 0x13u, 0xFFu, 0x67u, 0x13u, 0x15u, 0x07u, 0xF1u, - 0x3Fu, 0xCDu, 0x2Fu, 0x4Fu, 0xF6u, 0x12u, 0x12u, 0x11u, 0x11u, 0x19u, 0x11u, 0x21u, 0xFFu, 0x11u, 0x1Fu, 0x11u}; - -/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ -static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x32u, 0xF3u, 0xF4u, - 0xFFu, 0x45u, 0xFFu, 0x43u, 0x12u, 0x35u, 0x33u, 0xFFu, 0x3Fu, 0x5Fu, 0x34u, 0xF0u, 0xFFu, 0x2Fu, 0xFFu, 0x12u, - 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0xF3u, 0xFFu, 0x44u, 0x1Fu, 0xF2u, 0x04u, 0x01u, 0x2Fu, - 0x30u, 0x2Fu, 0x3Fu, 0xFFu, 0xF0u, 0x10u, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xF5u, 0x17u, 0x11u, 0x16u, 0x11u, 0x2Cu, 0x1Fu, 0x17u, 0x9Fu, 0x41u, 0x6Fu, 0xF4u, 0x1Fu, 0x33u, 0xCCu, 0x11u, - 0x63u, 0x1Fu, 0x29u, 0x71u, 0xF5u, 0x2Fu, 0x73u, 0x13u, 0xF1u, 0x13u, 0x11u, 0x1Au, 0x11u, 0x31u, 0x6Fu, 0x11u, - 0x11u, 0x1Fu, 0x11u, 0x1Au, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI0_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI1_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI2_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI3_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x15u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI4_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI5_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI6_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x09u, 0x1Fu, - 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0x03u, 0xFFu, 0xF0u, 0xFFu, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x01u, 0x11u, - 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x10u, 0xD1u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI7_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x04u, 0x12u, 0x10u, 0x0Du, 0x1Fu, 0x1Fu, 0x10u, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0xFFu, 0x0Fu, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x0Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, - 0x11u, 0xF1u, 0x11u, 0x11u, 0x21u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI8_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x20u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI9_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI10_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ -static const uint8 CYCODE BS_UDB_DSI11_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, - 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, - 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; - -static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), BS_UDB_UDBPAIR5_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), BS_UDB_UDBPAIR4_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), BS_UDB_UDBPAIR3_UDBSNG0_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), BS_UDB_UDBPAIR2_UDBSNG1_VAL, 116u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, - {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, - {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, +// UDB_UDBPAIR5_UDBSNG1 Address: CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR5_UDBSNG1_VAL[] = +{ + 0x08u, 0x00u, 0x00u, 0x00u, 0x42u, 0x00u, 0x2Du, 0x00u, 0x08u, 0x24u, 0x00u, 0x00u, 0x22u, + 0x24u, 0x45u, 0x00u, 0x00u, 0x10u, 0x10u, 0x08u, 0x00u, 0x70u, 0x00u, 0x83u, 0x08u, 0x24u, + 0x00u, 0x00u, 0x00u, 0x4Eu, 0x00u, 0xB0u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, + 0x8Fu, 0x3Cu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x1Fu, + 0x60u, 0x00u, 0x1Fu, 0x20u, 0x80u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x10u, 0x41u, 0x46u, + 0x02u, 0x00u, 0x00u, 0x05u, 0x00u, 0x04u, 0x0Bu, 0x14u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u }; +// UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = +{ + 0x08u, 0x0Au, 0x00u, 0xD0u, 0x02u, 0xB9u, 0x00u, 0x42u, 0x2Bu, 0x02u, 0x00u, 0x00u, 0x2Bu, + 0x00u, 0x54u, 0x80u, 0x2Au, 0x00u, 0x01u, 0x20u, 0x40u, 0x33u, 0x00u, 0xCCu, 0x04u, 0x00u, + 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0xA0u, 0x2Au, 0x00u, 0x00u, 0x00u, 0x01u, 0x8Au, 0x2Au, + 0x71u, 0x20u, 0x7Bu, 0x00u, 0x80u, 0x00u, 0x04u, 0x00u, 0x00u, 0x19u, 0xF8u, 0x07u, 0xF8u, + 0x00u, 0x00u, 0x61u, 0x07u, 0x8Au, 0x80u, 0x00u, 0x0Au, 0x00u, 0x0Au, 0x45u, 0x40u, 0x52u, + 0x06u, 0x00u, 0x00u, 0x04u, 0x4Cu, 0x0Eu, 0x00u, 0x07u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, + 0x00u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, + 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, 0x40u, 0x03u, 0x00u, 0x10u +}; + +// UDB_UDBPAIR4_UDBSNG1 Address: CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x00u, 0x19u, 0x00u, 0x12u, 0x00u, 0x2Du, 0x00u, 0x04u, + 0x00u, 0x00u, 0x11u, 0x02u, 0x08u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x05u, 0x00u, 0x03u, 0x10u, 0x08u, 0x15u, 0x00u, 0x2Au, 0x10u, 0x00u, 0x00u, 0x04u, + 0x00u, 0x0Eu, 0x0Fu, 0x31u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, 0x00u, 0x10u, + 0x3Fu, 0x00u, 0x3Fu, 0x0Cu, 0x00u, 0x00u, 0xA0u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x04u, 0x43u, + 0x02u, 0x00u, 0x00u, 0x06u, 0x40u, 0xB0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u +}; + +// UDB_UDBPAIR3_UDBSNG0 Address: CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG0_VAL[] = +{ + 0x3Cu, 0x00u, 0x00u, 0xC0u, 0x00u, 0x80u, 0x10u, 0x40u, 0x0Cu, 0x80u, 0x60u, 0x40u, 0x02u, + 0x10u, 0x00u, 0x25u, 0x04u, 0x80u, 0x08u, 0x40u, 0x00u, 0x19u, 0x10u, 0x22u, 0x04u, 0x00u, + 0x0Bu, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x80u, 0x10u, 0x00u, 0x00u, 0x24u, 0x00u, 0x40u, 0x00u, + 0x80u, 0x7Cu, 0x25u, 0x00u, 0x1Au, 0x00u, 0x08u, 0x10u, 0x80u, 0x01u, 0xC0u, 0x02u, 0x00u, + 0x70u, 0x07u, 0x0Cu, 0x38u, 0x00u, 0x00u, 0x80u, 0x82u, 0x00u, 0xA2u, 0x04u, 0x00u, 0x43u, + 0x02u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, + 0x78u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xDEu, 0x40u, 0x4Bu, 0x04u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u +}; + +// UDB_UDBPAIR2_UDBSNG1 Address: CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE Size (bytes): 116 +static const uint8 CYCODE BS_UDB_UDBPAIR2_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x80u, 0x03u, 0x00u, 0xC9u, 0x00u, 0x12u, 0x00u, 0x00u, 0x00u, 0x01u, 0x70u, + 0x01u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x40u, 0x40u, 0xB3u, 0xAAu, 0x4Cu, 0xEAu, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x40u, 0x40u, 0xB1u, 0xAAu, 0x04u, 0x43u, 0x00u, 0x00u, + 0x01u, 0x4Cu, 0x05u, 0x00u, 0xBAu, 0x00u, 0x20u, 0x40u, 0x80u, 0x03u, 0x7Fu, 0xC0u, 0x80u, + 0x0Cu, 0x7Fu, 0x30u, 0x00u, 0xA2u, 0x00u, 0x08u, 0x22u, 0x08u, 0x22u, 0x51u, 0x04u, 0x43u, + 0x02u, 0x00u, 0x00u, 0x05u, 0xB0u, 0x40u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, + 0x77u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, + 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, 0x10u, 0x1Du, 0x00u, 0x00u +}; + +// UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = +{ + 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF5u, + 0x7Fu, 0xF3u, 0x11u, 0xF3u, 0x11u, 0xFFu, 0xF2u, 0xFFu, 0x2Fu, 0xFFu, 0xFFu, 0x00u, 0x11u, + 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, + 0xF7u, 0x5Fu, 0xFFu, 0x2Fu, 0x10u, 0x22u, 0x62u, 0x00u, 0x34u, 0x2Fu, 0x62u, 0x73u, 0x00u, + 0x11u, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x0Fu, + 0x0Fu, 0x27u, 0x20u, 0x22u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x40u, 0x1Du, 0x11u, 0x00u, 0xDDu, 0x11u, + 0x10u, 0x10u, 0x11u, 0x00u, 0xD1u, 0x63u, 0x03u, 0x01u, 0x13u, 0x37u, 0x00u, 0x13u, 0x11u, + 0x00u, 0x13u, 0x16u, 0x11u, 0x11u, 0x16u, 0x19u, 0x11u, 0x01u, 0x11u, 0x11u, 0x19u, 0x11u, + 0x11u, 0x91u, 0x41u, 0x11u, 0x21u, 0x11u, 0x16u, 0x11u, 0x11u, 0x13u, 0x81u, 0x11u, 0x11u, + 0x11u +}; + +// UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = +{ + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, + 0x13u, 0x42u, 0x36u, 0x26u, 0x33u, 0x35u, 0xF5u, 0xF0u, 0x54u, 0x14u, 0x62u, 0x5Fu, 0x0Fu, + 0x04u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x24u, 0x45u, 0x7Fu, + 0x50u, 0x26u, 0x64u, 0xFFu, 0x3Fu, 0x32u, 0x42u, 0xF3u, 0x32u, 0x3Fu, 0x7Fu, 0x37u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, + 0x02u, 0x05u, 0xF6u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x13u, 0xF0u, 0x10u, 0x14u, 0x00u, 0x01u, 0x01u, + 0x10u, 0x0Du, 0x63u, 0x00u, 0x70u, 0x10u, 0x08u, 0x30u, 0x13u, 0x11u, 0x30u, 0x10u, 0x50u, + 0x30u, 0x1Fu, 0xC1u, 0x33u, 0x10u, 0x0Fu, 0x01u, 0x31u, 0x0Du, 0x1Cu, 0x25u, 0x11u, 0x01u, + 0x12u, 0xFBu, 0x02u, 0x12u, 0x15u, 0x1Cu, 0x11u, 0x11u, 0x11u, 0x15u, 0x11u, 0x61u, 0x16u, + 0x11u +}; + +// UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = +{ + 0x06u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, + 0x33u, 0x35u, 0x44u, 0x77u, 0x57u, 0xF2u, 0xFFu, 0xF4u, 0xFFu, 0x40u, 0xFFu, 0x32u, 0x63u, + 0xFFu, 0xFFu, 0x3Fu, 0x5Fu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x34u, + 0x13u, 0x46u, 0x56u, 0x35u, 0x41u, 0x40u, 0x57u, 0x67u, 0x55u, 0x3Fu, 0x63u, 0xF6u, 0xFFu, + 0x4Fu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, + 0x00u, 0x00u, 0x40u, 0x22u, 0x00u, 0xF0u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0xF3u, 0x10u, 0x12u, 0x02u, 0x96u, 0x01u, + 0x00u, 0x74u, 0xD1u, 0x00u, 0xF7u, 0x03u, 0x03u, 0x16u, 0x1Fu, 0x31u, 0x10u, 0x00u, 0x03u, + 0x10u, 0x41u, 0x35u, 0x10u, 0x16u, 0x0Fu, 0x76u, 0x11u, 0xB0u, 0xD1u, 0xDFu, 0x09u, 0x00u, + 0x0Fu, 0xFBu, 0x01u, 0x11u, 0x17u, 0x11u, 0x11u, 0x15u, 0xD5u, 0x1Du, 0x27u, 0x15u, 0x1Fu, + 0x11u +}; + +// UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, + 0x41u, 0x53u, 0x15u, 0x45u, 0x11u, 0xF4u, 0xF3u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0x33u, 0x63u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x31u, 0x02u, 0x14u, + 0x56u, 0xF1u, 0x77u, 0x77u, 0x37u, 0xF0u, 0x56u, 0x73u, 0x45u, 0x33u, 0x63u, 0xFFu, 0x03u, + 0x15u, 0xF2u, 0xF2u, 0xF2u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xB0u, 0x00u, 0xF0u, 0x17u, 0x1Fu, 0x02u, 0x1Fu, 0x60u, + 0xA3u, 0xF4u, 0x15u, 0xA0u, 0xF1u, 0x0Fu, 0x00u, 0x31u, 0x0Fu, 0xF3u, 0x3Au, 0x20u, 0x51u, + 0x3Au, 0x13u, 0xF3u, 0xC0u, 0x10u, 0x4Au, 0x11u, 0x20u, 0x10u, 0x01u, 0xF1u, 0x0Fu, 0x00u, + 0x0Fu, 0xFFu, 0x41u, 0x11u, 0x41u, 0x4Du, 0x11u, 0x71u, 0x11u, 0x1Fu, 0xFCu, 0x11u, 0x1Fu, + 0x1Cu +}; + +// UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = +{ + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, + 0xF4u, 0x55u, 0x4Fu, 0xF3u, 0x5Fu, 0x55u, 0x27u, 0x31u, 0x63u, 0x71u, 0x61u, 0x3Fu, 0x63u, + 0x0Fu, 0x5Fu, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x64u, 0x31u, + 0x70u, 0x77u, 0xF6u, 0x2Fu, 0x1Fu, 0x25u, 0x4Fu, 0xF7u, 0x3Fu, 0x32u, 0x63u, 0x3Fu, 0x75u, + 0xF4u, 0x1Fu, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, + 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x70u, 0x30u, 0x26u, 0x14u, 0x2Fu, 0x0Cu, 0xA5u, 0x10u, + 0x18u, 0x11u, 0x0Fu, 0xF0u, 0xF7u, 0x3Fu, 0x00u, 0x11u, 0x0Fu, 0xFFu, 0xF8u, 0x16u, 0xF7u, + 0x1Fu, 0x10u, 0x11u, 0xF4u, 0x13u, 0xFFu, 0x67u, 0x13u, 0x15u, 0x07u, 0xF1u, 0x3Fu, 0xCDu, + 0x2Fu, 0x4Fu, 0xF6u, 0x12u, 0x12u, 0x11u, 0x11u, 0x19u, 0x11u, 0x21u, 0xFFu, 0x11u, 0x1Fu, + 0x11u +}; + +// UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 +static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, + 0x32u, 0xF3u, 0xF4u, 0xFFu, 0x45u, 0xFFu, 0x43u, 0x12u, 0x35u, 0x33u, 0xFFu, 0x3Fu, 0x5Fu, + 0x34u, 0xF0u, 0xFFu, 0x2Fu, 0xFFu, 0x12u, 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, + 0xF3u, 0xF3u, 0xFFu, 0x44u, 0x1Fu, 0xF2u, 0x04u, 0x01u, 0x2Fu, 0x30u, 0x2Fu, 0x3Fu, 0xFFu, + 0xF0u, 0x10u, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF5u, 0x17u, 0x11u, 0x16u, 0x11u, 0x2Cu, 0x1Fu, 0x17u, + 0x9Fu, 0x41u, 0x6Fu, 0xF4u, 0x1Fu, 0x33u, 0xCCu, 0x11u, 0x63u, 0x1Fu, 0x29u, 0x71u, 0xF5u, + 0x2Fu, 0x73u, 0x13u, 0xF1u, 0x13u, 0x11u, 0x1Au, 0x11u, 0x31u, 0x6Fu, 0x11u, 0x11u, 0x1Fu, + 0x11u, 0x1Au, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u +}; + +// UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI0_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI1_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI2_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI3_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x15u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI4_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI5_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI6_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x00u, 0x09u, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0x03u, 0xFFu, 0xF0u, 0xFFu, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, + 0x01u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0xD1u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI7_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x04u, + 0x12u, 0x10u, 0x0Du, 0x1Fu, 0x1Fu, 0x10u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0xFFu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x0Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x21u, 0xF1u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI8_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x20u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0xF1u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI9_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI10_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +// UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 +static const uint8 CYCODE BS_UDB_DSI11_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +static const cfg_memcpy_t CYCODE cfg_memcpy_list[] = +{ + // dest, src, size + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), BS_UDB_UDBPAIR5_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), BS_UDB_UDBPAIR4_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), BS_UDB_UDBPAIR3_UDBSNG0_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), BS_UDB_UDBPAIR2_UDBSNG1_VAL, 116u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u }, + { (void CYFAR*)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u }, + { (void CYFAR*)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u }, +}; + + +//-------------------------------------------------------------------------------------------------- +// SDIO_Host_Config_TriggerMuxes +//-------------------------------------------------------------------------------------------------- void SDIO_Host_Config_TriggerMuxes(void) { - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + // Connect UDB to DMA + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, + TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, + TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, + TRIGGER_TYPE_LEVEL); } + +//-------------------------------------------------------------------------------------------------- +// SDIO_Host_Config_UDBs +//-------------------------------------------------------------------------------------------------- void SDIO_Host_Config_UDBs(void) { size_t i; - /* Power on the UDB array */ + // Power on the UDB array CY_SET_REG32(0x402101F0u, 0x05FA0003u); - /* Zero out critical memory blocks before beginning configuration */ + // Zero out critical memory blocks before beginning configuration for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { - const cfg_memset_t *ms = &cfg_memset_list[i]; + const cfg_memset_t* ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, ms->size); } - /* Copy device configuration data into registers */ + // Copy device configuration data into registers for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { - const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; + const cfg_memcpy_t* mc = &cfg_memcpy_list[i]; CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ - CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); + // UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL + CY_SET_REG32((void*)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); - /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C404Cu); + // UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C404Cu); - /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x044C4C44u); + // UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x044C4C44u); - /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x004C444Cu); + // UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x004C444Cu); - /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C44u); + // UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C44u); - /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x4C4C404Cu); + // UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x4C4C404Cu); - /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x004C4C4Cu); + // UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x004C4C4Cu); - /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x0C8C8C8Cu); + // UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x0C8C8C8Cu); - /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x004C404Cu); + // UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x004C404Cu); - /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x004C444Cu); + // UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x004C444Cu); - /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + // UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x4C4C0400u); + // UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x4C4C0400u); - /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ - CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + // UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 + CY_SET_REG32((void*)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); - /* Enable UDB array and digital routing */ - CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); + // Enable UDB array and digital routing + CY_SET_REG32((void*)0x40347900u, CY_GET_REG32((void*)0x40347900u) | 0x106u); } + #if defined(__cplusplus) } #endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h old mode 100644 new mode 100755 index 0bd0941f3e..b293f30298 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h @@ -1,29 +1,28 @@ -/***************************************************************************//** -* \file SDIO_HOST_cfg.h -* -* \brief -* This file provides the configuration of the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file COMPONENT_UDB_SDIO_P9/SDIO_HOST_cfg.h + * + * \brief + * This file provides the configuration of the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ -#if !defined(CY_SDIO_CFG_H) -#define CY_SDIO_CFG_H +#pragma once #include @@ -95,10 +94,10 @@ extern "C" { #define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u -/*************Defines for UDBs from Creator*****************************/ -/***********These come for cyfitter.h**********************************/ +// *************Defines for UDBs from Creator***************************** +// ***********These come for cyfitter.h********************************** -/* SDIO_HOST_bSDIO */ +// SDIO_HOST_bSDIO #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x40341008u #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x40341108u #define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x40341208u @@ -764,75 +763,76 @@ extern "C" { #define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 -/***************************CMD DMA***************************************/ +// ***************************CMD DMA*************************************** #define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) #define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) #define SDIO_HOST_CMD_DMA_HW (DW0) #define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_CMD_DMA_PRIORITY (1u) #define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; -/***************************Read DMA***************************************/ +// ***************************Read DMA*************************************** #define SDIO_HOST_Read_DMA_DW_BLOCK (1u) #define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) #define SDIO_HOST_Read_DMA_HW (DW1) #define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Read_DMA_PRIORITY (0u) #define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Read_DMA_PREEMPTABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; -/***************************Resp DMA***************************************/ +// ***************************Resp DMA*************************************** #define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) #define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) #define SDIO_HOST_Resp_DMA_HW (DW0) #define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Resp_DMA_PRIORITY (1u) #define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; -/***************************Write DMA***************************************/ +// ***************************Write DMA*************************************** #define SDIO_HOST_Write_DMA_DW_BLOCK (1u) #define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) #define SDIO_HOST_Write_DMA_HW (DW1) #define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) -/* Channel settings */ +// Channel settings #define SDIO_HOST_Write_DMA_PRIORITY (0u) #define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) #define SDIO_HOST_Write_DMA_PREEMPTABLE (false) extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; -extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; +extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; -/***************************SDIO Clock**************************************/ +// ***************************SDIO Clock************************************** /** The peripheral clock divider number */ #define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)SDIO_HOST_Internal_Clock__DIV_NUM) /** The peripheral clock divider type */ -#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE) +#define SDIO_HOST_Internal_Clock_DIV_TYPE \ + ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE) -/*Function for configuring TriggerMuxes*/ +// Function for configuring TriggerMuxes void SDIO_Host_Config_TriggerMuxes(void); -/*Function for configuring UDBs*/ +// Function for configuring UDBs void SDIO_Host_Config_UDBs(void); -/* SDIO_HOST_Read_Int */ +// SDIO_HOST_Read_Int #define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Read_Int__INTC_NUMBER 69u @@ -840,7 +840,7 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Read_Int_INTC_NUMBER 69u -/* SDIO_HOST_sdio_int */ +// SDIO_HOST_sdio_int #define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_sdio_int__INTC_NUMBER 122u @@ -848,7 +848,7 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_sdio_int_INTC_NUMBER 122u -/* SDIO_HOST_Write_Int */ +// SDIO_HOST_Write_Int #define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 #define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Write_Int__INTC_NUMBER 67u @@ -856,10 +856,9 @@ void SDIO_Host_Config_UDBs(void); #define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u #define SDIO_HOST_Write_Int_INTC_NUMBER 67u +// ****************************SDIO Port************************************** +#define SDIO_HOST_GPIO_PORT GPIO_PRT9 + #if defined(__cplusplus) } #endif - -#endif /* !defined(CY_SDIO_CFG_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/LICENSE b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/LICENSE new file mode 100755 index 0000000000..59cd3f8a32 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/LICENSE @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.c old mode 100644 new mode 100755 index 1477ec1043..d179fde603 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.c @@ -1,29 +1,30 @@ -/***************************************************************************//** -* \file SDIO_HOST.c -* -* \brief -* This file provides the source code to the API for the UDB based SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file SDIO_HOST.c + * + * \brief + * This file provides the source code to the API for the UDB based SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #include "SDIO_HOST.h" #include "cy_utils.h" +#include "cy_gpio.h" #if defined(CYHAL_UDB_SDIO) @@ -31,16 +32,16 @@ extern "C" { #endif -#ifdef CY_RTOS_AWARE +#if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) #include "cyabs_rtos.h" #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) - static cy_semaphore_t sdio_transfer_finished_semaphore; - static bool sema_initialized = false; +static cy_semaphore_t sdio_transfer_finished_semaphore; +static bool sema_initialized = false; #endif -/* Backup struct used to store and restore non retention UDB registers */ +// Backup struct used to store and restore non retention UDB registers typedef struct { uint32_t CY_SDIO_UDB_WRKMULT_CTL_0; @@ -49,14 +50,14 @@ typedef struct uint32_t CY_SDIO_UDB_WRKMULT_CTL_3; } stc_sdio_backup_regs_t; -/*Globals Needed for DMA */ -/*DMA channel structures*/ +// Globals Needed for DMA +// DMA channel structures cy_stc_dma_channel_config_t respChannelConfig; cy_stc_dma_channel_config_t cmdChannelConfig; cy_stc_dma_channel_config_t writeChannelConfig; cy_stc_dma_channel_config_t readChannelConfig; -/*DMA Descriptor structures*/ +// DMA Descriptor structures cy_stc_dma_descriptor_t respDesr; cy_stc_dma_descriptor_t cmdDesr; cy_stc_dma_descriptor_t readDesr0; @@ -64,51 +65,52 @@ cy_stc_dma_descriptor_t readDesr1; cy_stc_dma_descriptor_t writeDesr0; cy_stc_dma_descriptor_t writeDesr1; -/*Global structure used for data keeping*/ +// Global structure used for data keeping stc_sdio_gInternalData_t gstcInternalData; -/*Global CRC table*/ +// Global CRC table static uint8_t crcTable[256]; -/*Global values used for DMA interrupt*/ +// Global values used for DMA interrupt static uint32_t yCountRemainder; static uint32_t yCounts; -/* Global value for card interrupt */ +// Global value for card interrupt static uint8_t pfnCardInt_count = 0; -/*Global structure to store UDB registers */ +// Global structure to store UDB registers static stc_sdio_backup_regs_t regs; static uint32_t udb_initialized = 0; -cy_stc_syspm_callback_params_t sdio_pm_callback_params; -cy_stc_syspm_callback_t sdio_pm_callback_handler; +cy_stc_syspm_callback_params_t sdio_pm_callback_params; +cy_stc_syspm_callback_t sdio_pm_callback_handler; -/* Deep Sleep Mode API Support */ +// Deep Sleep Mode API Support static void SDIO_SaveConfig(void); static void SDIO_RestoreConfig(void); -/******************************************************************************* -* Function Name: SDIO_DeepSleepCallback -****************************************************************************//** -* -* Callback executed during Deep Sleep entry/exit -* -* \param params -* Pointer to structure that holds callback parameters for this driver. -* -* \param mode -* The state transition mode that is currently happening. -* -* \note -* Saves/Restores SDIO UDB registers -* -* \return -* CY_SYSPM_SUCCESS if the transition was successful, otherwise CY_SYSPM_FAIL -* -*******************************************************************************/ -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) +/*************************************************************************************************** + * Function Name: SDIO_DeepSleepCallback + ***********************************************************************************************//** + * + * Callback executed during Deep Sleep entry/exit + * + * \param params + * Pointer to structure that holds callback parameters for this driver. + * + * \param mode + * The state transition mode that is currently happening. + * + * \note + * Saves/Restores SDIO UDB registers + * + * \return + * CY_SYSPM_SUCCESS if the transition was successful, otherwise CY_SYSPM_FAIL + * + **************************************************************************************************/ +cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t* params, + cy_en_syspm_callback_mode_t mode) { CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; @@ -137,209 +139,212 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para return status; } -/******************************************************************************* -* Function Name: SDIO_Init -****************************************************************************//** -* -* Initializes the SDIO hardware -* -* \param pfuCb -* Pointer to structure that holds pointers to callback function -* see \ref stc_sdio_irq_cb_t. -* -* \note -* Sets SD Clock Frequency to 400 kHz -*******************************************************************************/ + +/*************************************************************************************************** + * Function Name: SDIO_Init + ***********************************************************************************************//** + * + * Initializes the SDIO hardware + * + * \param pfuCb + * Pointer to structure that holds pointers to callback function + * see \ref stc_sdio_irq_cb_t. + * + * \note + * Sets SD Clock Frequency to 400 kHz + **************************************************************************************************/ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) { - if ( !udb_initialized ) + if (!udb_initialized) { udb_initialized = 1; SDIO_Host_Config_TriggerMuxes(); SDIO_Host_Config_UDBs(); } - /*Set Number of Blocks to 1 initially, this will be updated later*/ + // Set Number of Blocks to 1 initially, this will be updated later SDIO_SetNumBlocks(1); - /*Enable SDIO ISR*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + // Enable SDIO ISR + NVIC_EnableIRQ((IRQn_Type)SDIO_HOST_sdio_int__INTC_NUMBER); - /*Enable the Status Reg to generate an interrupt*/ + // Enable the Status Reg to generate an interrupt SDIO_STATUS_AUX_CTL |= (0x10); - /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ - /*First clear priority of all*/ - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; + // Set the priority of DW0, DW1, M4 and M0. DW1 should have highest + // First clear priority of all + (*(reg32*)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; + (*(reg32*)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; + (*(reg32*)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; + (*(reg32*)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; - /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ - (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; - (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; - (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; + // Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3 + (*(reg32*)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; + (*(reg32*)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; + (*(reg32*)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; - /*Setup callback for card interrupt*/ + // Setup callback for card interrupt gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; - /*Setup the DMA channels*/ + // Setup the DMA channels SDIO_SetupDMA(); - /*Initialize CRC*/ + // Initialize CRC SDIO_Crc7Init(); - /*Enable all the bit counters*/ - SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + // Enable all the bit counters + SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; - /*Set block byte count to 64, this will be changed later */ + // Set block byte count to 64, this will be changed later SDIO_SetBlockSize(64); - /*Set the read and write FIFOs to use the half full status*/ - (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; - (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; + // Set the read and write FIFOs to use the half full status + (*(reg32*)SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; + (*(reg32*)SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; - /*Set clock to 400k, and enable it*/ + // Set clock to 400k, and enable it SDIO_SetSdClkFrequency(400000); SDIO_EnableIntClock(); SDIO_EnableSdClk(); } -/******************************************************************************* -* Function Name: SDIO_SendCommand -****************************************************************************//** -* -* Send an SDIO command, don't wait for it to finish. -* -* \param pstcCmdConfig -* Command configuration structure. See \ref stc_sdio_cmd_config_t. -* -*******************************************************************************/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) +/*************************************************************************************************** + * Function Name: SDIO_SendCommand + ***********************************************************************************************//** + * + * Send an SDIO command, don't wait for it to finish. + * + * \param pstcCmdConfig + * Command configuration structure. See \ref stc_sdio_cmd_config_t. + * + **************************************************************************************************/ +void SDIO_SendCommand(stc_sdio_cmd_config_t* pstcCmdConfig) { - /*buffer to hold command data*/ + // buffer to hold command data static uint8_t u8cmdBuf[6]; - /*Populate buffer*/ - /*Element 0 is the Most Significant Byte*/ + // Populate buffer + // Element 0 is the Most Significant Byte u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); - /*calculate the CRC of above data*/ + // calculate the CRC of above data u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); - /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ + // Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd u8cmdBuf[5] = u8cmdBuf[5] << 1; - /*Add on the end bit*/ + // Add on the end bit u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; - /*Load the first byte into A0*/ + // Load the first byte into A0 SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; - /*If a response is expected setup DMA to receive the response*/ + // If a response is expected setup DMA to receive the response if (pstcCmdConfig->bResponseRequired == true) { - /*Clear the flag in hardware that says skip response*/ + // Clear the flag in hardware that says skip response SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; - /*Set the destination address*/ + // Set the destination address respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); + // Initialize the channel with the descriptor + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, + &respDesr); - /*Enable the channel*/ + // Enable the channel Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); } else { - /*Set the skip flag*/ + // Set the skip flag SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; } - /*Setup the Command DMA*/ - /*Set the source address*/ + // Setup the Command DMA + // Set the source address cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); - /*Initialize the channel with the descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); + // Initialize the channel with the descriptor + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdDesr); - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + // Enable the channel + Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL); } -/******************************************************************************* -* Function Name: SDIO_GetResponse -****************************************************************************//** -* -* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks -* for index errors, CRC errors, and end bit errors. -* -* \param bCmdIndexCheck -* If True check for index errors -* -* \param bCmdCrcCheck -* If True check for CRC errors -* -* \param u8cmdIdx -* Command index, used for checking the index error -* -* \param pu32Response -* location to store 32 bit response -* -* \param pu8ResponseBuf -* buffer that holds the 6 bytes of response data -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) +/*************************************************************************************************** + * Function Name: SDIO_GetResponse + ***********************************************************************************************//** + * + * Takes a 6 byte response buffer, and extracts the 32 bit response, also checks + * for index errors, CRC errors, and end bit errors. + * + * \param bCmdIndexCheck + * If True check for index errors + * + * \param bCmdCrcCheck + * If True check for CRC errors + * + * \param u8cmdIdx + * Command index, used for checking the index error + * + * \param pu32Response + * location to store 32 bit response + * + * \param pu8ResponseBuf + * buffer that holds the 6 bytes of response data + * + * \return + * \ref en_sdio_result_t + * + **************************************************************************************************/ +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, + uint32_t* pu32Response, uint8_t* pu8ResponseBuf) { - /*Function return*/ - en_sdio_result_t enRet = Error; - /*variable to hold temporary CRC*/ + // Function return + en_sdio_result_t enRet = Error; + // variable to hold temporary CRC uint8_t u8TmpCrc; - /*temporary response*/ + // temporary response uint32_t u32TmpResponse; - /*Zero out the pu32Response*/ + // Zero out the pu32Response *pu32Response = 0; - /*Check if the CRC needs to be checked*/ + // Check if the CRC needs to be checked if (bCmdCrcCheck) { - /*Calculate the CRC*/ + // Calculate the CRC u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); - /*Shift calculated CRC up by one bit to match bit position of CRC*/ + // Shift calculated CRC up by one bit to match bit position of CRC u8TmpCrc = u8TmpCrc << 1; - /*Compare calculated CRC with received CRC*/ + // Compare calculated CRC with received CRC if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) { enRet |= CommandCrcError; } } - /*Check if the index needs to be checked*/ + // Check if the index needs to be checked if (bCmdIndexCheck) { - /*The index resides in the lower 6 bits of the 1st byte of the response*/ + // The index resides in the lower 6 bits of the 1st byte of the response if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) { enRet |= CommandIdxError; } } - /*Check the end bit*/ + // Check the end bit if (!(pu8ResponseBuf[5] & 0x01)) { enRet |= CommandEndError; @@ -347,13 +352,13 @@ en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, if (enRet == Error) { - /*If we get here then there were no errors with the command populate the response*/ - u32TmpResponse = pu8ResponseBuf[1]; - u32TmpResponse = u32TmpResponse << 8; + // If we get here then there were no errors with the command populate the response + u32TmpResponse = pu8ResponseBuf[1]; + u32TmpResponse = u32TmpResponse << 8; u32TmpResponse |= pu8ResponseBuf[2]; - u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse = u32TmpResponse << 8; u32TmpResponse |= pu8ResponseBuf[3]; - u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse = u32TmpResponse << 8; u32TmpResponse |= pu8ResponseBuf[4]; *pu32Response = u32TmpResponse; @@ -365,482 +370,507 @@ en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, } -/******************************************************************************* -* Function Name: SDIO_InitDataTransfer -****************************************************************************//** -* -* Configure the data channel for a data transfer. For a write this doesn't start -* the write, that must be done separately after the response is received. -* -* \param pstcDataConfig -* Data configuration structure. See \ref stc_sdio_data_config_t -* -* -*******************************************************************************/ -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) +/*************************************************************************************************** + * Function Name: SDIO_InitDataTransfer + ***********************************************************************************************//** + * + * Configure the data channel for a data transfer. For a write this doesn't start + * the write, that must be done separately after the response is received. + * + * \param pstcDataConfig + * Data configuration structure. See \ref stc_sdio_data_config_t + * + * + **************************************************************************************************/ +void SDIO_InitDataTransfer(stc_sdio_data_config_t* pstcDataConfig) { - /*hold size of entire transfer*/ + // hold size of entire transfer uint32_t dataSize; - /*calculate how many bytes are going to be sent*/ + // calculate how many bytes are going to be sent dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; - /*Set the block size and number of blocks*/ + // Set the block size and number of blocks SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); - /*If we are reading data setup the DMA to receive read data*/ + // If we are reading data setup the DMA to receive read data if (pstcDataConfig->bRead == true) { - /*First disable the write channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + // First disable the write channel + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - /*Clear any pending interrupts in the DMA*/ + // Clear any pending interrupts in the DMA Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + NVIC_ClearPendingIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); - /*setup the destination addresses*/ + // setup the destination addresses readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + // Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + // Remember X increment is in terms of data element size which is 16, thus why it is 1 readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); - /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the - DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility - that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA - will be SW triggered when hardware indicates all bytes have been received. - This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to - be at least 3 bytes bigger than the data size. - - Since the X loop is setup to 4, the maximum number of Y loop is 256 so one - descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. - Since we don't know the maximum number of bytes to read only two descriptors will - be used. If more than 2048 bytes need to be read then and interrupt will be enabled - The descriptor that is not currently running will be updated in the ISR to receive - more data. - - So there are three conditions to check: - 1) Are we sending less than or equal to 1024 bytes if so use one descriptor - 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors - 3) Greater than 2048, use two descriptors and the ISR - */ + // The X Loop will always transfer 4 bytes. The FIFO will only trigger the + // DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility + // that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA + // will be SW triggered when hardware indicates all bytes have been received. + // This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to + // be at least 3 bytes bigger than the data size. + // + // Since the X loop is setup to 4, the maximum number of Y loop is 256 so one + // descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. + // Since we don't know the maximum number of bytes to read only two descriptors will + // be used. If more than 2048 bytes need to be read then and interrupt will be enabled + // The descriptor that is not currently running will be updated in the ISR to receive + // more data. + // + // So there are three conditions to check: + // 1) Are we sending less than or equal to 1024 bytes if so use one descriptor + // 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors + // 3) Greater than 2048, use two descriptors and the ISR if (dataSize <= 1024) { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + // Setup one descriptor + // Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits) readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - /*Setup descriptor 0 to point to nothing and disable*/ + // Setup descriptor 0 to point to nothing and disable readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; + readDesr0.ctl |= 0x01000000; - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + // Disable Interrupt + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } - else if (dataSize <=2048) + else if (dataSize <= 2048) { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + // setup the first descriptor for 1024, then setup 2nd descriptor for remainder readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - /*Setup descriptor 0 to point to descriptor 1*/ + // Setup descriptor 0 to point to descriptor 1 readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to nothing and disable */ + // Setup descriptor 1 to point to nothing and disable readDesr1.nextPtr = 0; - /*Don't disable after first descriptor*/ + // Don't disable after first descriptor readDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ + // Disable after second descriptor readDesr1.ctl |= 0x01000000; - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + // Disable Interrupt + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } - else /*dataSize must be greater than 2048*/ + else // dataSize must be greater than 2048 { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + // These are for the ISR, Need to figure out how many "descriptors" + // need to run, and the yCount for last descriptor. + // Example: dataSize = 2080 + // yCounts = 2, yCountRemainder = 7 (send 8 more set of 4) yCounts = (dataSize / 1024); - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + // the Ycount register is a +1 register meaning 0 = 1. I However, need to know when + // there is no remainder so I increase the value to make sure there is a remainder and + // decrement in the ISR + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3) / 4); - /*Setup the Y Ctrl for both descriptors*/ + // Setup the Y Ctrl for both descriptors readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - /*Setup descriptor 0 to point to descriptor 1*/ + // Setup descriptor 0 to point to descriptor 1 readDesr0.nextPtr = (uint32_t)(&readDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ + // Setup descriptor 1 to point to descriptor 0 readDesr1.nextPtr = (uint32_t)(&readDesr0); - /*Don't disable the channel on completion of descriptor*/ + // Don't disable the channel on completion of descriptor readDesr0.ctl &= ~0x01000000; readDesr1.ctl &= ~0x01000000; - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + // Decrement yCounts by 2 since we already have 2 descriptors setup yCounts -= 2; - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + // Enable DMA interrupt + NVIC_EnableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); + // Initialize the channel with the first descriptor + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, + &readDesr0); - /*Enable the channel*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + // Enable the channel + Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - /*Set the flag in the control register to enable the read*/ + // Set the flag in the control register to enable the read SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; } - - /*Otherwise it is a write*/ + // Otherwise it is a write else { - /*First disable the Read channel*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + // First disable the Read channel + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - /*Clear any pending interrupts in the DMA*/ + // Clear any pending interrupts in the DMA Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + NVIC_ClearPendingIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); - /*setup the SRC addresses*/ + // setup the SRC addresses writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); - /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes - Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + // Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + // Remember X increment is in terms of data element size which is 16, thus why it is 1 writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); if (dataSize <= 1024) { - /*Setup one descriptor*/ - /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + // Setup one descriptor + // Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits) writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - /*Setup descriptor 0 to point to nothing and disable*/ + // Setup descriptor 0 to point to nothing and disable writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; + writeDesr0.ctl |= 0x01000000; - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + // Disable Interrupt + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } - else if (dataSize <=2048) + else if (dataSize <= 2048) { - /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + // setup the first descriptor for 1024, then setup 2nd descriptor for remainder writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - /*Setup descriptor 0 to point to descriptor 1*/ + // Setup descriptor 0 to point to descriptor 1 writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to nothing and disable */ + // Setup descriptor 1 to point to nothing and disable writeDesr1.nextPtr = 0; - /*Don't disable after first descriptor*/ + // Don't disable after first descriptor writeDesr0.ctl &= ~0x01000000; - /*Disable after second descriptor*/ + // Disable after second descriptor writeDesr1.ctl |= 0x01000000; - /*Disable Interrupt*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + // Disable Interrupt + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } - else /*dataSize must be greater than 2048*/ + else // dataSize must be greater than 2048 { - /*These are for the ISR, Need to figure out how many "descriptors" - need to run, and the yCount for last descriptor. - Example: dataSize = 2080 - yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + // These are for the ISR, Need to figure out how many "descriptors" + // need to run, and the yCount for last descriptor. + // Example: dataSize = 2080 + // yCounts = 2, yCountRemainder = 7 (send 8 more set of 4) yCounts = (dataSize / 1024); - /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is - no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ - yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + // the Ycount register is a +1 register meaning 0 = 1. I However, need to know when + // there is no remainder so I increase the value to make sure there is a remainder and + // decrement in the ISR + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3) / 4); - /*Setup the Y Ctrl for both descriptors*/ + // Setup the Y Ctrl for both descriptors writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - /*Setup descriptor 0 to point to descriptor 1*/ + // Setup descriptor 0 to point to descriptor 1 writeDesr0.nextPtr = (uint32_t)(&writeDesr1); - /*Setup descriptor 1 to point to descriptor 0*/ + // Setup descriptor 1 to point to descriptor 0 writeDesr1.nextPtr = (uint32_t)(&writeDesr0); - /*Don't disable the channel on completion of descriptor*/ + // Don't disable the channel on completion of descriptor writeDesr0.ctl &= ~0x01000000; writeDesr1.ctl &= ~0x01000000; - /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + // Decrement yCounts by 2 since we already have 2 descriptors setup yCounts -= 2; - /*Enable DMA interrupt*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + // Enable DMA interrupt + NVIC_EnableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } - /*Initialize the channel with the first descriptor*/ - Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); + // Initialize the channel with the first descriptor + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, + &writeDesr0); } } -/******************************************************************************* -* Function Name: SDIO_SendCommandAndWait -****************************************************************************//** -* -* This function sends a command on the command channel and waits for that -* command to finish before returning. If a Command 53 is issued this function -* will handle all of the data transfer and wait to return until it is done. -* -* \param pstcCmd -* Pointer command configuration structure see \ref stc_sdio_cmd_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) +/*************************************************************************************************** + * Function Name: SDIO_SendCommandAndWait + ***********************************************************************************************//** + * + * This function sends a command on the command channel and waits for that + * command to finish before returning. If a Command 53 is issued this function + * will handle all of the data transfer and wait to return until it is done. + * + * \param pstcCmd + * Pointer command configuration structure see \ref stc_sdio_cmd_t. + * + * \return + * \ref en_sdio_result_t + * + **************************************************************************************************/ +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t* pstcCmd) { - /* Store the command and data configurations*/ - stc_sdio_cmd_config_t stcCmdConfig; - stc_sdio_data_config_t stcDataConfig; + // Store the command and data configurations + stc_sdio_cmd_config_t stcCmdConfig; + stc_sdio_data_config_t stcDataConfig; uint32_t u32CmdTimeout = 0; - /*Returns from various function calls*/ - en_sdio_result_t enRet = Error; + // Returns from various function calls + en_sdio_result_t enRet = Ok; en_sdio_result_t enRetTmp = Ok; - /* Hold value of if these checks are needed */ - uint8_t bCmdIndexCheck; - uint8_t bCmdCrcCheck; - static uint8_t u8responseBuf[6]; + // Hold value of if these checks are needed + uint8_t bCmdIndexCheck; + uint8_t bCmdCrcCheck; + static uint8_t u8responseBuf[6]; - /* Clear statuses */ - gstcInternalData.stcEvents.u8CmdComplete = 0; + // Clear statuses + gstcInternalData.stcEvents.u8CmdComplete = 0; gstcInternalData.stcEvents.u8TransComplete = 0; - gstcInternalData.stcEvents.u8CRCError = 0; + gstcInternalData.stcEvents.u8CRCError = 0; - /* Setup the command configuration */ - stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; + // Setup the command configuration + stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; stcCmdConfig.u32Argument = pstcCmd->u32Arg; -#ifdef CY_RTOS_AWARE + #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) cy_rslt_t result; - /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in - * interrupt thread. - */ - if(!sema_initialized) + // Initialize the semaphore. This is not done in init because init is called * in interrupt + // thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. + if (!sema_initialized) { - cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 ); + cy_rtos_init_semaphore(&sdio_transfer_finished_semaphore, 1, 0); sema_initialized = true; } -#else + #else // if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) - /* Variable used for holding timeout value */ - uint32_t u32Timeout = 0; -#endif + // Variable used for holding timeout value + uint32_t u32Timeout = 0; + #endif // if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) - /*Determine the type of response and if we need to do any checks*/ - /*Command 0 and 8 have no response, so don't wait for one*/ - if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) + // Determine the type of response and if we need to do any checks + // Command 0 and 8 have no response, so don't wait for one + if ((pstcCmd->u32CmdIdx == 0) || (pstcCmd->u32CmdIdx == 8)) { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = false; - stcCmdConfig.pu8ResponseBuf = NULL; + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = false; + stcCmdConfig.pu8ResponseBuf = NULL; } - - /*Command 5's response doesn't have a CRC or index, so don't check*/ + // Command 5's response doesn't have a CRC or index, so don't check else if (pstcCmd->u32CmdIdx == 5) { - bCmdIndexCheck = false; - bCmdCrcCheck = false; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; } - /*Otherwise check everything*/ + // Otherwise check everything else { - bCmdIndexCheck = true; - bCmdCrcCheck = true; - stcCmdConfig.bResponseRequired = true; - stcCmdConfig.pu8ResponseBuf = u8responseBuf; + bCmdIndexCheck = true; + bCmdCrcCheck = true; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; } - /*Check if the command is 53, if it is then setup the data transfer*/ + // Check if the command is 53, if it is then setup the data transfer if (pstcCmd->u32CmdIdx == 53) { - /*Set the number of blocks in the global struct*/ + // Set the number of blocks in the global struct stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; - /*Set the size of the data transfer*/ + // Set the size of the data transfer stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; - /*Set the direction are we reading or writing*/ + // Set the direction are we reading or writing stcDataConfig.bRead = pstcCmd->bRead; - /*Set the pointer for the data*/ + // Set the pointer for the data stcDataConfig.pu8Data = pstcCmd->pu8Data; - /*Get the data Transfer Ready*/ - SDIO_InitDataTransfer(&stcDataConfig); - - /*Set bit saying this was a CMD_53*/ - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; - } - - /*Send the command*/ - SDIO_SendCommand(&stcCmdConfig); - - /*Wait for the command to finish*/ - do - { - u32CmdTimeout++; - enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); - - } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); - - - if (u32CmdTimeout == SDIO_CMD_TIMEOUT) - { - enRet |= CMDTimeout; - } - else /*CMD Passed*/ - { - /*If a response is expected check it*/ - if (stcCmdConfig.bResponseRequired == true) + // Check DAT[0] to ensure it isn't low, if it is wait + uint32_t count = 0; + while (0UL == Cy_GPIO_Read(SDIO_HOST_GPIO_PORT, 0) && count < SDIO_DAT_BUSY_TIMEOUT_MS) { - enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); - if (enRetTmp != Ok) + #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) + cy_rtos_delay_milliseconds(1); + #else + Cy_SysLib_Delay(1); + #endif + count++; + } + if (count >= SDIO_DAT_BUSY_TIMEOUT_MS) + { + enRet |= DataTimeout; + } + else + { + // Get the data Transfer Ready + SDIO_InitDataTransfer(&stcDataConfig); + + // Set bit saying this was a CMD_53 + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; + } + } + + if (enRet == Ok) + { + // Send the command + SDIO_SendCommand(&stcCmdConfig); + + // Wait for the command to finish + do + { + u32CmdTimeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); + } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); + + + if (u32CmdTimeout == SDIO_CMD_TIMEOUT) + { + enRet |= CMDTimeout; + } + else // CMD Passed + { + // If a response is expected check it + if (stcCmdConfig.bResponseRequired == true) { - enRet |= enRetTmp; - } - else /*Response good*/ - { - /*if it was command 53, check the response to ensure there was no error*/ - if ((pstcCmd->u32CmdIdx) == 53) + enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, + (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, + u8responseBuf); + if (enRetTmp != Ok) { - /*Make sure none of the error bits are set*/ - if (*(pstcCmd->pu32Response) & 0x0000cf00) + enRet |= enRetTmp; + } + else // Response good + { + // if it was command 53, check the response to ensure there was no error + if ((pstcCmd->u32CmdIdx) == 53) { - enRet |= ResponseFlagError; - } - else /*CMD53 Response good*/ - { - /*If it was command 53 and it was a write enable the write*/ - if (pstcCmd->bRead == false && enRet == Error) + // Make sure none of the error bits are set + if (*(pstcCmd->pu32Response) & 0x0000cf00) { - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - - /*Set the flag in the control register to enable the write*/ - Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); - /*Enable the channel*/ - Cy_SysLib_DelayCycles(35); - SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; + enRet |= ResponseFlagError; } - - #ifdef CY_RTOS_AWARE - /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released - * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in - * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases - * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero - * and exit. Or timeout occurs - */ - result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); - - enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - - if (result != CY_RSLT_SUCCESS) - #else - /* Wait for the transfer to finish */ - do + else // CMD53 Response good { - u32Timeout++; + // If it was command 53 and it was a write enable the write + if ((pstcCmd->bRead == false) && (enRet == Ok)) + { + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, + SDIO_HOST_Resp_DMA_DW_CHANNEL); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, + SDIO_HOST_CMD_DMA_DW_CHANNEL); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, + SDIO_HOST_Read_DMA_DW_CHANNEL); + + // Set the flag in the control register to enable the write + Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, + SDIO_HOST_Write_DMA_DW_CHANNEL); + // Enable the channel + Cy_SysLib_DelayCycles(35); + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; + } + + #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) + // Wait for the transfer to finish. + // Acquire semaphore and wait until it will be released + // in SDIO_IRQ: + // 1. sdio_transfer_finished_semaphore count is equal to + // zero. cy_rtos_get_semaphore waits until semaphore + // count is increased by cy_rtos_set_semaphore() in + // SDIO_IRQ. + // 2. The cy_rtos_set_semaphore() increases + // sdio_transfer_finished_semaphore count. + // 3. The cy_rtos_get_semaphore() function decreases + // sdio_transfer_finished_semaphore back to zero + // and exit. Or timeout occurs + result = + cy_rtos_get_semaphore(&sdio_transfer_finished_semaphore, 10, false); + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); - } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); + if (result != CY_RSLT_SUCCESS) + #else // if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) + // Wait for the transfer to finish + do + { + u32Timeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || + (u32Timeout >= SDIO_DAT_TIMEOUT))); - if (u32Timeout == SDIO_DAT_TIMEOUT) - #endif - { - enRet |= DataTimeout; - } + if (u32Timeout == SDIO_DAT_TIMEOUT) + #endif // if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) + { + enRet |= DataTimeout; + } - /* if it was a read it is possible there is still extra data hanging out, trigger the - DMA again. This can result in extra data being transfered so the read buffer should be - 3 bytes bigger than needed*/ - if (pstcCmd->bRead == true) - { - Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); - } + // if it was a read it is possible there is still extra data hanging + // out, trigger the DMA again. This can result in extra data being + // transferred so the read buffer should be 3 bytes bigger than needed + if (pstcCmd->bRead == true) + { + Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); + } - if (enRetTmp == DataCrcError) - { - enRet |= DataCrcError; - } - }/*CMD53 response good*/ - }/*Not a CMD53*/ - } /*Response Good*/ - } /*No Response Required, thus no CMD53*/ - } /*CMD Passed*/ + if (enRetTmp == DataCrcError) + { + enRet |= DataCrcError; + } + }// CMD53 response good + }// Not a CMD53 + } // Response Good + } // No Response Required, thus no CMD53 + } // CMD Passed + } // Timeout error -#ifndef CY_RTOS_AWARE + #if !defined(CY_RTOS_AWARE) && !defined(COMPONENT_RTOS_AWARE) u32Timeout = 0; -#endif + #endif - /*If there were no errors then indicate transfer was okay*/ - if (enRet == Error) + // If there were any errors then set general error flag + if (enRet != Ok) { - enRet = Ok; + enRet |= Error; } - /*reset CmdTimeout value*/ + // reset CmdTimeout value u32CmdTimeout = 0; - /*Always Reset on exit to clean up*/ - Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); - Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); - /*No longer a CMD_53*/ + // Always Reset on exit to clean up + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL); + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + // No longer a CMD_53 SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); SDIO_Reset(); @@ -848,90 +878,90 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) } -/******************************************************************************* -* Function Name: SDIO_CheckForEvent -****************************************************************************//** -* -* Checks to see if a specific event has occurred such a command complete or -* transfer complete. -* -* \param enEventType -* The type of event to check for. See \ref en_sdio_event_t. -* -* \return -* \ref en_sdio_result_t -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_CheckForEvent + ***********************************************************************************************//** + * + * Checks to see if a specific event has occurred such a command complete or + * transfer complete. + * + * \param enEventType + * The type of event to check for. See \ref en_sdio_event_t. + * + * \return + * \ref en_sdio_result_t + * + **************************************************************************************************/ en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) { - en_sdio_result_t enRet = Error; + en_sdio_result_t enRet = Error; - /*Disable Interrupts while modifying the global*/ - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + // Disable Interrupts while modifying the global + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_sdio_int__INTC_NUMBER); - /*Switch the event to check*/ - switch ( enEventType ) + // Switch the event to check + switch (enEventType) { - /*If the command is done clear the flag*/ + // If the command is done clear the flag case SdCmdEventCmdDone: if (gstcInternalData.stcEvents.u8CmdComplete > 0) { gstcInternalData.stcEvents.u8CmdComplete = 0; - enRet = Ok; + enRet = Ok; } break; - /*If the transfer is done check for CRC Error and clear the flag*/ + // If the transfer is done check for CRC Error and clear the flag case SdCmdEventTransferDone: if (gstcInternalData.stcEvents.u8TransComplete > 0) { gstcInternalData.stcEvents.u8TransComplete = 0; - enRet = Ok; + enRet = Ok; } - /*Check for CRC error and set flags*/ + // Check for CRC error and set flags if (gstcInternalData.stcEvents.u8CRCError > 0) { - enRet = DataCrcError; + enRet = DataCrcError; gstcInternalData.stcEvents.u8CRCError = 0; } break; } - /*Re-enable Interrupts*/ - NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + // Re-enable Interrupts + NVIC_EnableIRQ((IRQn_Type)SDIO_HOST_sdio_int__INTC_NUMBER); return enRet; } -/******************************************************************************* -* Function Name: SDIO_CalculateCrc7 -****************************************************************************//** -* -* Calculate the 7 bit CRC for the command channel -* -* \param pu8Data -* Data to calculate CRC on -* -* \param u8Size -* Number of bytes to calculate CRC on -* -* \return -* CRC -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_CalculateCrc7 + ***********************************************************************************************//** + * + * Calculate the 7 bit CRC for the command channel + * + * \param pu8Data + * Data to calculate CRC on + * + * \param u8Size + * Number of bytes to calculate CRC on + * + * \return + * CRC + * + * \note + * This code was copied from + * http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code + * + **************************************************************************************************/ uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) { - uint8_t data; - uint8_t remainder = 0; + uint8_t data; + uint8_t remainder = 0; uint32_t byte; - for(byte = 0; byte < u8Size; ++byte) + for (byte = 0; byte < u8Size; ++byte) { - data = pu8Data[byte] ^ remainder; + data = pu8Data[byte] ^ remainder; remainder = crcTable[data] ^ (remainder << 8); } @@ -939,28 +969,28 @@ uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) } -/******************************************************************************* -* Function Name: SDIO_Crc7Init -****************************************************************************//** -* -* Initialize 7-bit CRC Table -* -* \note -* This code was copied from -* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_Crc7Init + ***********************************************************************************************//** + * + * Initialize 7-bit CRC Table + * + * \note + * This code was copied from + * http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code + * + **************************************************************************************************/ void SDIO_Crc7Init(void) { - uint8_t remainder; - uint8_t bit; + uint8_t remainder; + uint8_t bit; uint32_t dividend; - for(dividend = 0; dividend < 256; ++dividend) + for (dividend = 0; dividend < 256; ++dividend) { remainder = dividend; - for(bit = 8; bit > 0; --bit) + for (bit = 8; bit > 0; --bit) { if (remainder & SDIO_CRC_UPPER_BIT) { @@ -977,285 +1007,293 @@ void SDIO_Crc7Init(void) } -/******************************************************************************* -* Function Name: SDIO_SetBlockSize -****************************************************************************//** -* -* Sets the size of each block -* -* \param u8ByteCount -* Size of the block -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_SetBlockSize + ***********************************************************************************************//** + * + * Sets the size of each block + * + * \param u8ByteCount + * Size of the block + * + **************************************************************************************************/ void SDIO_SetBlockSize(uint8_t u8ByteCount) { SDIO_BYTE_COUNT_REG = u8ByteCount; } -/******************************************************************************* -* Function Name: SDIO_SetNumBlocks -****************************************************************************//** -* -* Sets the number of blocks to send -* -* \param u8BlockCount -* Size of the block -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_SetNumBlocks + ***********************************************************************************************//** + * + * Sets the number of blocks to send + * + * \param u8BlockCount + * Size of the block + * + **************************************************************************************************/ void SDIO_SetNumBlocks(uint8_t u8BlockCount) { SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; - /*The one is used so that we can do 256 bytes*/ + // The one is used so that we can do 256 bytes SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; } -/******************************************************************************* -* Function Name: SDIO_EnableIntClock -****************************************************************************//** -* -* Enable Internal clock for the block -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_EnableIntClock + ***********************************************************************************************//** + * + * Enable Internal clock for the block + * + **************************************************************************************************/ void SDIO_EnableIntClock(void) { SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); + Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, + SDIO_HOST_Internal_Clock_DIV_NUM); } -/******************************************************************************* -* Function Name: SDIO_DisableIntClock -****************************************************************************//** -* -* Enable Disable clock for the block -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_DisableIntClock + ***********************************************************************************************//** + * + * Enable Disable clock for the block + * + **************************************************************************************************/ void SDIO_DisableIntClock(void) { SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; - Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); + Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, + SDIO_HOST_Internal_Clock_DIV_NUM); } -/******************************************************************************* -* Function Name: SDIO_EnableSdClk -****************************************************************************//** -* -* Enable SD Clock out to pin -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_EnableSdClk + ***********************************************************************************************//** + * + * Enable SD Clock out to pin + * + **************************************************************************************************/ void SDIO_EnableSdClk(void) { SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; } -/******************************************************************************* -* Function Name: SDIO_DisableSdClk -****************************************************************************//** -* -* Disable SD Clock out to the pin -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_DisableSdClk + ***********************************************************************************************//** + * + * Disable SD Clock out to the pin + * + **************************************************************************************************/ void SDIO_DisableSdClk(void) { SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; } -/******************************************************************************* -* Function Name: SDIO_SetSdClkFrequency -****************************************************************************//** -* -* Sets the frequency of the SD Clock -* -* \param u32SdClkFreqHz -* Frequency of SD Clock in Hz. -* -* \note -* Only an integer divider is used, so the desired frequency may not be meet -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_SetSdClkFrequency + ***********************************************************************************************//** + * + * Sets the frequency of the SD Clock + * + * \param u32SdClkFreqHz + * Frequency of SD Clock in Hz. + * + * \note + * Only an integer divider is used, so the desired frequency may not be meet + **************************************************************************************************/ void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; /* - * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB - * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the + * UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the + * required * SDIO operating frequency. */ u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); - Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); + Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, + (u16Div-1)); } -/******************************************************************************* -* Function Name: SDIO_SetupDMA -****************************************************************************//** -* -* Configures the DMA for the SDIO block -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_SetupDMA + ***********************************************************************************************//** + * + * Configures the DMA for the SDIO block + * + **************************************************************************************************/ void SDIO_SetupDMA(void) { - /*Set the number of bytes to send*/ + // Set the number of bytes to send SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); - /*Set the destination address*/ + // Set the destination address SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; - /*Initialize descriptor for cmd channel*/ + // Initialize descriptor for cmd channel Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); - /*Set flag to disable descriptor when done*/ + // Set flag to disable descriptor when done cmdDesr.ctl |= 0x01000000; - /*Configure channel*/ - /*CMD channel can be preempted, and has lower priority*/ - cmdChannelConfig.descriptor = &cmdDesr; + // Configure channel + // CMD channel can be preempted, and has lower priority + cmdChannelConfig.descriptor = &cmdDesr; cmdChannelConfig.preemptable = 1; cmdChannelConfig.priority = 1; cmdChannelConfig.enable = 0u; - /*Configure Channel with initial Settings*/ + // Configure Channel with initial Settings Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); - /*Enable DMA block*/ + // Enable DMA block Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); - /*Set the number of bytes to receive*/ + // Set the number of bytes to receive SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; - /*Set the source address*/ + // Set the source address SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; - /*Initialize descriptor for response channel*/ + // Initialize descriptor for response channel Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); - /*Set flag to disable descriptor when done*/ + // Set flag to disable descriptor when done respDesr.ctl |= 0x01000000; - /*Configure channel*/ - /*response channel can be preempted, and has lower priority*/ - respChannelConfig.descriptor = &respDesr; + // Configure channel + // response channel can be preempted, and has lower priority + respChannelConfig.descriptor = &respDesr; respChannelConfig.preemptable = 1; respChannelConfig.priority = 1; respChannelConfig.enable = 0u; - /*Configure Channel with initial Settings*/ + // Configure Channel with initial Settings Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); - /*Enable DMA block*/ + // Enable DMA block Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); - /*Set the destination address*/ + // Set the destination address SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; - /*Initialize descriptor for write channel*/ + // Initialize descriptor for write channel Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); - /*Configure channel*/ - /*write channel cannot be preempted, and has highest priority*/ - writeChannelConfig.descriptor = &writeDesr0; + // Configure channel + // write channel cannot be preempted, and has highest priority + writeChannelConfig.descriptor = &writeDesr0; writeChannelConfig.preemptable = 0; writeChannelConfig.priority = 0; writeChannelConfig.enable = 0u; - /*Configure Channel with initial Settings*/ - Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); + // Configure Channel with initial Settings + Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, + &writeChannelConfig); - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + // Enable the interrupt + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, + CY_DMA_INTR_MASK); - /*Enable DMA block*/ + // Enable DMA block Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); - /*Set the source address*/ + // Set the source address SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; - /*Initialize descriptor for read channel*/ + // Initialize descriptor for read channel Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); - /*Configure channel*/ - /*read channel cannot be preempted, and has highest priority*/ - readChannelConfig.descriptor = &readDesr0; + // Configure channel + // read channel cannot be preempted, and has highest priority + readChannelConfig.descriptor = &readDesr0; readChannelConfig.preemptable = 0; readChannelConfig.priority = 0; readChannelConfig.enable = 0u; - /*Configure Channel with initial Settings*/ + // Configure Channel with initial Settings Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); - /*Enable the interrupt*/ - Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + // Enable the interrupt + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, + CY_DMA_INTR_MASK); - /*Enable DMA block*/ + // Enable DMA block Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); } -/******************************************************************************* -* Function Name: SDIO_Reset -****************************************************************************//** -* -* Reset the SDIO interface -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_Reset + ***********************************************************************************************//** + * + * Reset the SDIO interface + * + **************************************************************************************************/ void SDIO_Reset(void) { - /*Control register is in pulse mode, so this just pulses the reset*/ + // Control register is in pulse mode, so this just pulses the reset SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); } -/******************************************************************************* -* Function Name: SDIO_EnableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_EnableChipInt + ***********************************************************************************************//** + * + * Enables the SDIO Chip Int by setting the mask bit + * + **************************************************************************************************/ void SDIO_EnableChipInt(void) { SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; } -/******************************************************************************* -* Function Name: SDIO_DisableChipInt -****************************************************************************//** -* -* Enables the SDIO Chip Int by setting the mask bit -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_DisableChipInt + ***********************************************************************************************//** + * + * Enables the SDIO Chip Int by setting the mask bit + * + **************************************************************************************************/ void SDIO_DisableChipInt(void) { SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; } -/******************************************************************************* -* Function Name: SDIO_IRQ -****************************************************************************//** -* -* SDIO interrupt, checks for events, and calls callbacks -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_IRQ + ***********************************************************************************************//** + * + * SDIO interrupt, checks for events, and calls callbacks + * + **************************************************************************************************/ void SDIO_IRQ(void) { uint8_t u8Status; - /* First read the status register */ + // First read the status register u8Status = SDIO_STATUS_REG; - /* Check card interrupt */ - if (u8Status & SDIO_STS_CARD_INT ) + // Check card interrupt + if (u8Status & SDIO_STS_CARD_INT) { pfnCardInt_count++; } - /* Execute card interrupt callback if neccesary */ + // Execute card interrupt callback if neccesary if (0 != pfnCardInt_count) { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) @@ -1265,212 +1303,217 @@ void SDIO_IRQ(void) pfnCardInt_count--; } - /* If the command is complete set the flag */ + // If the command is complete set the flag if (u8Status & SDIO_STS_CMD_DONE) { gstcInternalData.stcEvents.u8CmdComplete++; } - /* Check if a write is complete */ - if (u8Status & SDIO_STS_WRITE_DONE ) + // Check if a write is complete + if (u8Status & SDIO_STS_WRITE_DONE) { - - /* Clear the Write flag and CMD53 flag */ + // Clear the Write flag and CMD53 flag SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); - /* Check if the CRC status return was bad */ + // Check if the CRC status return was bad if (u8Status & SDIO_STS_CRC_ERR) { - /* CRC was bad, set the flag */ + // CRC was bad, set the flag gstcInternalData.stcEvents.u8CRCError++; } - /* Set the done flag */ + // Set the done flag - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else + #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, true); + #else gstcInternalData.stcEvents.u8TransComplete++; - #endif + #endif } - /* Check if a read is complete */ + // Check if a read is complete if (u8Status & SDIO_STS_READ_DONE) { - /* Clear the read flag */ + // Clear the read flag SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); - /* Check the CRC */ + // Check the CRC if (u8Status & SDIO_STS_CRC_ERR) { - /* CRC was bad, set the flag */ + // CRC was bad, set the flag gstcInternalData.stcEvents.u8CRCError++; } - /* Okay we're done so set the done flag */ - #ifdef CY_RTOS_AWARE - cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); - #else + // Okay we're done so set the done flag + #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, true); + #else gstcInternalData.stcEvents.u8TransComplete++; - #endif + #endif } - NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + NVIC_ClearPendingIRQ((IRQn_Type)SDIO_HOST_sdio_int__INTC_NUMBER); } -/******************************************************************************* -* Function Name: SDIO_READ_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Read interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ +/*************************************************************************************************** + * Function Name: SDIO_READ_DMA_IRQ + ***********************************************************************************************//** + * + * SDIO DMA Read interrupt, checks counts and toggles to other descriptor if + * needed + * + **************************************************************************************************/ void SDIO_READ_DMA_IRQ(void) { - /*Shouldn't have to change anything unless it is the last descriptor*/ + // Shouldn't have to change anything unless it is the last descriptor - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) + // If the current descriptor is 0, then change descriptor 1 + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, + SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) { - /*We need to increment the destination address every time*/ + // We need to increment the destination address every time readDesr1.dst += 2048; - /*If this is the last descriptor*/ + // If this is the last descriptor if ((yCounts == 1) && (yCountRemainder == 0)) { - /* In this case all we need to change is the next descriptor and disable*/ + // In this case all we need to change is the next descriptor and disable readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + readDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } - else if (yCounts == 0 && (yCountRemainder > 0)) + else if ((yCounts == 0) && (yCountRemainder > 0)) { - /*change next descriptor, and disable*/ + // change next descriptor, and disable readDesr1.nextPtr = 0; - readDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ + readDesr1.ctl |= 0x01000000; + // Also change the yCount readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } } - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) + // If the current descriptor is 1, then change descriptor 0 + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, + SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) { - /*We need to increment the destination address everytime*/ + // We need to increment the destination address everytime readDesr0.dst += 2048; - /*If this is the last descriptor*/ + // If this is the last descriptor if ((yCounts == 1) && (yCountRemainder == 0)) { - /* In this case all we need to change is the next descriptor and disable*/ + // In this case all we need to change is the next descriptor and disable readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + readDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } - else if (yCounts == 0 && (yCountRemainder > 0)) + else if ((yCounts == 0) && (yCountRemainder > 0)) { - /*change next descriptor, and disable*/ + // change next descriptor, and disable readDesr0.nextPtr = 0; - readDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ + readDesr0.ctl |= 0x01000000; + // Also change the yCount readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | - _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Read_Int_INTC_NUMBER); } } - /*Clear the interrupt*/ + // Clear the interrupt Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); - /*decrement y counts*/ + // decrement y counts yCounts--; } -/******************************************************************************* -* Function Name: SDIO_WRITE_DMA_IRQ -****************************************************************************//** -* -* SDIO DMA Write interrupt, checks counts and toggles to other descriptor if -* needed -* -*******************************************************************************/ + +/*************************************************************************************************** + * Function Name: SDIO_WRITE_DMA_IRQ + ***********************************************************************************************//** + * + * SDIO DMA Write interrupt, checks counts and toggles to other descriptor if + * needed + * + **************************************************************************************************/ void SDIO_WRITE_DMA_IRQ(void) { - /*We shouldn't have to change anything unless it is the last descriptor*/ + // We shouldn't have to change anything unless it is the last descriptor - /*If the current descriptor is 0, then change descriptor 1*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) + // If the current descriptor is 0, then change descriptor 1 + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, + SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) { - /*We also need to increment the destination address every-time*/ + // We also need to increment the destination address every-time writeDesr1.src += 2048; - /*If this is the last descriptor*/ + // If this is the last descriptor if ((yCounts == 1) && (yCountRemainder == 0)) { - /* In this case all we need to change is the next descriptor and disable*/ + // In this case all we need to change is the next descriptor and disable writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); - + writeDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } - else if (yCounts == 0 && (yCountRemainder > 0)) + else if ((yCounts == 0) && (yCountRemainder > 0)) { - /*change next descriptor, and disable*/ + // change next descriptor, and disable writeDesr1.nextPtr = 0; - writeDesr1.ctl |= 0x01000000; - /*Also change the yCount*/ + writeDesr1.ctl |= 0x01000000; + // Also change the yCount writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } } - /*If the current descriptor is 1, then change descriptor 0*/ - if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) + // If the current descriptor is 1, then change descriptor 0 + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, + SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) { - /*We also need to increment the destination address*/ + // We also need to increment the destination address writeDesr0.src += 2048; - /*If this is the last descriptor*/ + // If this is the last descriptor if ((yCounts == 1) && (yCountRemainder == 0)) { - /* In this case all we need to change is the next descriptor and disable*/ + // In this case all we need to change is the next descriptor and disable writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + writeDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } - else if (yCounts == 0 && (yCountRemainder > 0)) + else if ((yCounts == 0) && (yCountRemainder > 0)) { - /*change next descriptor, and disable*/ + // change next descriptor, and disable writeDesr0.nextPtr = 0; - writeDesr0.ctl |= 0x01000000; - /*Also change the yCount*/ + writeDesr0.ctl |= 0x01000000; + // Also change the yCount writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | - _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); - NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type)SDIO_HOST_Write_Int_INTC_NUMBER); } } - /*Clear the interrupt*/ + // Clear the interrupt Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); yCounts--; } -/******************************************************************************* -* Function Name: SDIO_Free -****************************************************************************//** -* -* Frees any system resources that were allocated by the SDIO driver. -* -*******************************************************************************/ + +/*************************************************************************************************** + * Function Name: SDIO_Free + ***********************************************************************************************//** + * + * Frees any system resources that were allocated by the SDIO driver. + * + **************************************************************************************************/ void SDIO_Free(void) { -#ifdef CY_RTOS_AWARE + #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); -#endif + #endif } + /******************************************************************************* * Function Name: SDIO_SaveConfig ******************************************************************************** @@ -1504,10 +1547,9 @@ static void SDIO_RestoreConfig(void) UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3; } + #if defined(__cplusplus) } #endif -#endif /* defined(CYHAL_UDB_SDIO) */ - -/* [] END OF FILE */ +#endif // defined(CYHAL_UDB_SDIO) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.h old mode 100644 new mode 100755 index 00ec45039f..d62aa4b98f --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/SDIO_HOST.h @@ -1,59 +1,58 @@ -/***************************************************************************//** -* \file SDIO_HOST.h -* -* \brief -* This file provides types definition, constants and function definition for -* the SDIO driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file SDIO_HOST.h + * + * \brief + * This file provides types definition, constants and function definition for + * the SDIO driver. + * + *************************************************************************************************** + * \copyright + * Copyright 2016-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ /** -* \defgroup group_bsp_pin_state Pin States -* \defgroup group_bsp_pins Pin Mappings -* \defgroup group_bsp_macros Macros -* \defgroup group_bsp_functions Functions -* -* \defgroup group_udb_sdio UDB_SDIO -* \{ -* SDIO - Secure Digital Input Output is a standard for communicating with various + * \defgroup group_bsp_pin_state Pin States + * \defgroup group_bsp_pins Pin Mappings + * \defgroup group_bsp_macros Macros + * \defgroup group_bsp_functions Functions + * + * \defgroup group_udb_sdio UDB_SDIO + * \{ + * SDIO - Secure Digital Input Output is a standard for communicating with various external devices such as Wifi and bluetooth devices. -*

-* The driver is currently designed to only support communication with certain -* Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general -* SDIO card, or even and SD card. It is only intended to be used by the WiFi -* driver for communication. -*

-* This is not intended to be used as a general purpose API. -* -* \section group_udb_sdio_section_configuration_considerations Configuration Considerations -* Features: -* * Always Four Wire Mode -* * Supports Card Interrupt -* * Uses DMA for command and data transfer -* -* \defgroup group_udb_sdio_macros Macros -* \defgroup group_udb_sdio_functions Functions -* \defgroup group_udb_sdio_data_structures Data Structures -*/ + *

+ * The driver is currently designed to only support communication with certain + * Cypress Wifi and Bluetooth chipsets, it is not designed to work with a general + * SDIO card, or even and SD card. It is only intended to be used by the WiFi + * driver for communication. + *

+ * This is not intended to be used as a general purpose API. + * + * \section group_udb_sdio_section_configuration_considerations Configuration Considerations + * Features: + * * Always Four Wire Mode + * * Supports Card Interrupt + * * Uses DMA for command and data transfer + * + * \defgroup group_udb_sdio_macros Macros + * \defgroup group_udb_sdio_functions Functions + * \defgroup group_udb_sdio_data_structures Data Structures + */ -#if !defined(CY_SDIO_H) -#define CY_SDIO_H +#pragma once #if defined(CYHAL_UDB_SDIO) #include "SDIO_HOST_cfg.h" @@ -63,23 +62,25 @@ extern "C" { #endif -/*************************************** -* API Constants -***************************************/ +//================================================================================================== +// API Constants +//================================================================================================== /** -* \addtogroup group_udb_sdio_macros -* \{ -*/ + * \addtogroup group_udb_sdio_macros + * \{ + */ -#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ -#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ -#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ -#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ +#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ +#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ +#define SDIO_DAT_BUSY_TIMEOUT_MS (500u) /**< Value used for firmware timeout*/ +#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ +#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 + bit counters*/ /*! -\defgroup group_sdio_cmd_constants Constants for the command channel -*/ + \defgroup group_sdio_cmd_constants Constants for the command channel + */ /* @{*/ #define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ #define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ @@ -88,35 +89,41 @@ extern "C" { /*@} group_sdio_cmd_constants */ /*! -\defgroup group_sdio_ctrl_reg SDIO control register bits -*/ + \defgroup group_sdio_ctrl_reg SDIO control register bits + */ /* @{*/ -#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ +#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO + block*/ #define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ -#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ -#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ -#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ +#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if + ENABLE_READ is set*/ +#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if + ENABLE_WRITE is set*/ +#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the + command*/ #define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ #define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ #define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ /*@} group_sdio_ctrl_reg */ /*! -\defgroup group_sdio_status_reg SDIO status register bits -*/ + \defgroup group_sdio_status_reg SDIO status register bits + */ /* @{*/ #define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ #define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ #define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ -#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ +#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or + write*/ #define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ #define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ -#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ +#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by + driving DAT[1] low*/ /*@} group_sdio_status_reg */ /*! -\defgroup group_sdio_crc Constants for 7bit CRC for command -*/ + \defgroup group_sdio_crc Constants for 7bit CRC for command + */ /* @{*/ #define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ #define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ @@ -125,166 +132,168 @@ extern "C" { /** \} group_udb_sdio_macros */ -/*************************************** -* Type Definitions -***************************************/ +//================================================================================================== +// Type Definitions +//================================================================================================== /** -* \addtogroup group_udb_sdio_data_structures -* \{ -*/ + * \addtogroup group_udb_sdio_data_structures + * \{ + */ /** -* Create a type for the card interrupt call back -*/ + * Create a type for the card interrupt call back + */ typedef void (* sdio_card_int_cb_t)(void); /** -* \brief This enum is used when checking for specific events -*/ + * \brief This enum is used when checking for specific events + */ typedef enum en_sdio_event { - SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ - SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ - -}en_sdio_event_t; + SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ + SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ +} en_sdio_event_t; /** -* \brief Used to indicate the result of a function -*/ + * \brief Used to indicate the result of a function + */ typedef enum en_sdio_result { - Ok = 0x00, /**< No error*/ - Error = 0x01, /**< Non-specific error code*/ - CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ - CommandIdxError = 0x04, /**< The index for the command didn't match*/ - CommandEndError = 0x08, /**< There was an end bit error on the command*/ - DataCrcError = 0x10, /**< There was a data CRC Error*/ - CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ - DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ + Ok = 0x00, /**< No error*/ + Error = 0x01, /**< Non-specific error code*/ + CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ + CommandIdxError = 0x04, /**< The index for the command didn't match*/ + CommandEndError = 0x08, /**< There was an end bit error on the command*/ + DataCrcError = 0x10, /**< There was a data CRC Error*/ + CMDTimeout = 0x20, /**< The command didn't finish before the timeout period + was over*/ + DataTimeout = 0x40, /**< The data didn't finish before the timeout period + was over*/ ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ - } en_sdio_result_t; /** -* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function -*/ + * \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check + * events function + */ typedef struct stc_sdcmd_event_flag { - uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ - uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ - uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ - -}stc_sdio_event_flag_t; + uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ + uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ + uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data + transfer*/ +} stc_sdio_event_flag_t; /** -* \brief Holds pointers to callback functions -*/ + * \brief Holds pointers to callback functions + */ typedef struct stc_sdio_irq_cb { sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ -}stc_sdio_irq_cb_t; +} stc_sdio_irq_cb_t; /** -* \brief Global structure used to hold data from interrupt and other functions -*/ + * \brief Global structure used to hold data from interrupt and other functions + */ typedef struct stc_sdio_gInternalData { - stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ - stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ -}stc_sdio_gInternalData_t; + stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ + stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in + interrupt used in check events*/ +} stc_sdio_gInternalData_t; /** -* \brief structure used for configuring command -*/ + * \brief structure used for configuring command + */ typedef struct stc_sdio_cmd_config { - uint8_t u8CmdIndex; /**< Command index*/ - uint32_t u32Argument; /**< The argument of command */ - uint8_t bResponseRequired; /**< TRUE: A Response is required*/ - uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ - -}stc_sdio_cmd_config_t; + uint8_t u8CmdIndex; /**< Command index*/ + uint32_t u32Argument; /**< The argument of command */ + uint8_t bResponseRequired; /**< TRUE: A Response is required*/ + uint8_t* pu8ResponseBuf; /**< Pointer to location to store response*/ +} stc_sdio_cmd_config_t; /** -* \brief structure used for the data channel -*/ + * \brief structure used for the data channel + */ typedef struct stc_sdio_data_config { - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockSize; /**< Block size*/ - uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - -}stc_sdio_data_config_t; + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockSize; /**< Block size*/ + uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ + uint8_t* pu8Data; /**< Pointer data buffer*/ +} stc_sdio_data_config_t; /** -* \brief structure used for configuring command and data -*/ + * \brief structure used for configuring command and data + */ typedef struct stc_sdio_cmd { - uint32_t u32CmdIdx; /**< Command index*/ - uint32_t u32Arg; /**< The argument of command*/ - uint32_t *pu32Response; /**< Pointer to location to store response*/ - uint8_t *pu8Data; /**< Pointer data buffer*/ - uint8_t bRead; /**< TRUE: Read, FALSE: write*/ - uint16_t u16BlockCnt; /**< Number of blocks to send*/ - uint16_t u16BlockSize; /**< Block size*/ -}stc_sdio_cmd_t; + uint32_t u32CmdIdx; /**< Command index*/ + uint32_t u32Arg; /**< The argument of command*/ + uint32_t* pu32Response; /**< Pointer to location to store response*/ + uint8_t* pu8Data; /**< Pointer data buffer*/ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockCnt; /**< Number of blocks to send*/ + uint16_t u16BlockSize; /**< Block size*/ +} stc_sdio_cmd_t; /** \} group_udb_sdio_data_structures */ -/*************************************** -* Function Prototypes -***************************************/ +//================================================================================================== +// Function Prototypes +//================================================================================================== /** -* \addtogroup group_udb_sdio_functions -* \{ -*/ + * \addtogroup group_udb_sdio_functions + * \{ + */ -/* Main functions*/ -void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); -en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); -void SDIO_EnableIntClock(void); -void SDIO_DisableIntClock(void); -void SDIO_EnableSdClk(void); -void SDIO_DisableSdClk(void); -void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); -void SDIO_Reset(void); -void SDIO_EnableChipInt(void); -void SDIO_DisableChipInt(void); -void SDIO_Free(void); +// Main functions +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t* pstcCmd); +void SDIO_EnableIntClock(void); +void SDIO_DisableIntClock(void); +void SDIO_EnableSdClk(void); +void SDIO_DisableSdClk(void); +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); +void SDIO_Reset(void); +void SDIO_EnableChipInt(void); +void SDIO_DisableChipInt(void); +void SDIO_Free(void); -/*Low Level Functions*/ -void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); -en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); -void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); -en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); -uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); -void SDIO_SetBlockSize(uint8_t u8ByteCount); -void SDIO_SetNumBlocks(uint8_t u8BlockCount); +// Low Level Functions +void SDIO_SendCommand(stc_sdio_cmd_config_t* pstcCmdConfig); +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, + uint32_t* pu32Response, uint8_t* pu8ResponseBuf); +void SDIO_InitDataTransfer(stc_sdio_data_config_t* pstcDataConfig); +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); +void SDIO_SetBlockSize(uint8_t u8ByteCount); +void SDIO_SetNumBlocks(uint8_t u8BlockCount); -/*DMA setup function*/ -void SDIO_SetupDMA(void); +// DMA setup function +void SDIO_SetupDMA(void); -/*Interrupt Function*/ -void SDIO_IRQ(void); -void SDIO_READ_DMA_IRQ(void); -void SDIO_WRITE_DMA_IRQ(void); +// Interrupt Function +void SDIO_IRQ(void); +void SDIO_READ_DMA_IRQ(void); +void SDIO_WRITE_DMA_IRQ(void); -void SDIO_Crc7Init(void); +void SDIO_Crc7Init(void); -cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); +cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t* params, + cy_en_syspm_callback_mode_t mode); /** \endcond */ /** \} group_udb_sdio_functions */ -/*************************************** -* Hardware Registers -***************************************/ +//================================================================================================== +// Hardware Registers +//================================================================================================== /** \cond INTERNAL */ @@ -390,10 +399,6 @@ SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) } #endif -#endif /* defined(CYHAL_UDB_SDIO) */ - -#endif /* (CY_SDIO_H) */ +#endif // defined(CYHAL_UDB_SDIO) /** \} group_udb_sdio */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/version.xml new file mode 100755 index 0000000000..7a00e5148c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/udb-sdio-whd/version.xml @@ -0,0 +1 @@ +.19214