mirror of https://github.com/ARMmbed/mbed-os.git
[STM32xxx] gcc_arm startup files
Updates startup files to actual versions of STM32 Cube drivers without any changes of STs drivers: - DISCO_F303VC - DISCO_F334 - NUCLEO_F030 - NUCLEO_F072 - NUCLEO_F302 - NUCLEO_F334pull/767/head
ohagendorf
parent
883b2bc0ce
commit
967046e1d6
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@ -100,10 +100,9 @@ LoopFillZerobss:
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call static constructors */
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/* Call static constructors */
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// bl __libc_init_array
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bl __libc_init_array
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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// bl main
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bl main
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bl _start
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LoopForever:
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LoopForever:
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b LoopForever
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b LoopForever
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@ -100,10 +100,9 @@ LoopFillZerobss:
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call static constructors */
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/* Call static constructors */
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// bl __libc_init_array
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bl __libc_init_array
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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// bl main
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bl main
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bl _start
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LoopForever:
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LoopForever:
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b LoopForever
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b LoopForever
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@ -1,17 +1,16 @@
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/**
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/**
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******************************************************************************
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******************************************************************************
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* @file startup_stm32f30x.s
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* @file startup_stm32f303xc.s
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* @author MCD Application Team
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* @author MCD Application Team
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* @version V1.0.0
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* @version V1.1.0
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* @date 04-Spetember-2012
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* @date 12-Sept-2014
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* @brief STM32F4xx Devices vector table for RIDE7 toolchain.
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* @brief STM32F303xB/STM32F303xC devices vector table for Atollic
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* TrueSTUDIO toolchain.
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* This module performs:
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* This module performs:
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* - Set the initial SP
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Set the vector table entries with the exceptions ISR address,
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* - Configure the clock system and the external SRAM mounted on
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* - Configure the clock system
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* STM3230C-EVAL board to be used as data memory (optional,
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* to be enabled by user)
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* - Branches to main in the C library (which eventually
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* - Branches to main in the C library (which eventually
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* calls main()).
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* After Reset the Cortex-M4 processor is in Thread mode,
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@ -19,7 +18,7 @@
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******************************************************************************
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******************************************************************************
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* @attention
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* @attention
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*
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may not use this file except in compliance with the License.
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@ -35,101 +34,108 @@
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*
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*
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******************************************************************************
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******************************************************************************
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*/
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*/
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.syntax unified
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.syntax unified
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.cpu cortex-m4
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.cpu cortex-m4
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.fpu softvfp
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.fpu softvfp
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.thumb
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.thumb
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.global g_pfnVectors
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.global g_pfnVectors
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.global Default_Handler
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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/* start address for the initialization values of the .data section.
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defined in linker script */
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defined in linker script */
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.word _sidata
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.word _sidata
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/* start address for the .data section. defined in linker script */
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/* start address for the .data section. defined in linker script */
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.word _sdata
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.word _sdata
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/* end address for the .data section. defined in linker script */
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/* end address for the .data section. defined in linker script */
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.word _edata
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.word _edata
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/* start address for the .bss section. defined in linker script */
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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.equ BootRAM, 0xF1E0F85F
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/**
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/**
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* @brief This is the code that gets called when the processor first
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* supplied main() routine is called.
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* @param None
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* @param None
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* @retval : None
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* @retval : None
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*/
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*/
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.section .text.Reset_Handler
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.section .text.Reset_Handler
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.weak Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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.type Reset_Handler, %function
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Reset_Handler:
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Reset_Handler:
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ldr sp, =_estack /* Atollic update: set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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movs r1, #0
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b LoopCopyDataInit
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b LoopCopyDataInit
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CopyDataInit:
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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adds r1, r1, #4
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LoopCopyDataInit:
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r0, =_sdata
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ldr r3, =_edata
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ldr r3, =_edata
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adds r2, r0, r1
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adds r2, r0, r1
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cmp r2, r3
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cmp r2, r3
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bcc CopyDataInit
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bcc CopyDataInit
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ldr r2, =_sbss
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ldr r2, =_sbss
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b LoopFillZerobss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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/* Zero fill the bss segment. */
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FillZerobss:
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FillZerobss:
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movs r3, #0
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movs r3, #0
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str r3, [r2], #4
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str r3, [r2], #4
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LoopFillZerobss:
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LoopFillZerobss:
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ldr r3, = _ebss
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ldr r3, = _ebss
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cmp r2, r3
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cmp r2, r3
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bcc FillZerobss
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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/* Call the clock system intitialization function.*/
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bl SystemInit
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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/* Call the application's entry point.*/
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bl _start
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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/**
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* @brief This is the code that gets called when the processor receives an
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* the system state for examination by a debugger.
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* @param None
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*
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* @retval None
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* @param None
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* @retval : None
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*/
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*/
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.section .text.Default_Handler,"ax",%progbits
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Default_Handler:
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Infinite_Loop:
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Infinite_Loop:
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b Infinite_Loop
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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/******************************************************************************
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*
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* The minimal vector table for a Cortex-M4. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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* 0x0000.0000.
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*
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*
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*******************************************************************************/
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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g_pfnVectors:
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.word _estack
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.word _estack
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.word Reset_Handler
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.word Reset_Handler
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@ -149,13 +155,13 @@ g_pfnVectors:
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.word SysTick_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler
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.word WWDG_IRQHandler
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.word PVD_IRQHandler
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.word PVD_IRQHandler
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.word TAMPER_STAMP_IRQHandler
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.word TAMP_STAMP_IRQHandler
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.word RTC_WKUP_IRQHandler
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.word RTC_WKUP_IRQHandler
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.word FLASH_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_TS_IRQHandler
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.word EXTI2_TSC_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel1_IRQHandler
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@ -166,10 +172,10 @@ g_pfnVectors:
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word ADC1_2_IRQHandler
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.word ADC1_2_IRQHandler
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.word USB_HP_CAN1_TX_IRQHandler
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.word USB_HP_CAN_TX_IRQHandler
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.word USB_LP_CAN1_RX0_IRQHandler
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.word USB_LP_CAN_RX0_IRQHandler
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.word CAN1_RX1_IRQHandler
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.word CAN_RX1_IRQHandler
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.word CAN1_SCE_IRQHandler
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.word CAN_SCE_IRQHandler
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.word EXTI9_5_IRQHandler
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.word EXTI9_5_IRQHandler
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.word TIM1_BRK_TIM15_IRQHandler
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.word TIM1_BRK_TIM15_IRQHandler
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.word TIM1_UP_TIM16_IRQHandler
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.word TIM1_UP_TIM16_IRQHandler
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@ -271,8 +277,8 @@ g_pfnVectors:
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.weak PVD_IRQHandler
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.weak PVD_IRQHandler
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.thumb_set PVD_IRQHandler,Default_Handler
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.thumb_set PVD_IRQHandler,Default_Handler
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.weak TAMPER_STAMP_IRQHandler
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.weak TAMP_STAMP_IRQHandler
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.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
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.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
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.weak RTC_WKUP_IRQHandler
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.weak RTC_WKUP_IRQHandler
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler
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@ -289,8 +295,8 @@ g_pfnVectors:
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.weak EXTI1_IRQHandler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_TS_IRQHandler
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.weak EXTI2_TSC_IRQHandler
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.thumb_set EXTI2_TS_IRQHandler,Default_Handler
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.thumb_set EXTI2_TSC_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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@ -322,17 +328,17 @@ g_pfnVectors:
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.weak ADC1_2_IRQHandler
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.weak ADC1_2_IRQHandler
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.thumb_set ADC1_2_IRQHandler,Default_Handler
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.thumb_set ADC1_2_IRQHandler,Default_Handler
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.weak USB_HP_CAN1_TX_IRQHandler
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.weak USB_HP_CAN_TX_IRQHandler
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.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
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.thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
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.weak USB_LP_CAN1_RX0_IRQHandler
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.weak USB_LP_CAN_RX0_IRQHandler
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.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
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.thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
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.weak CAN1_RX1_IRQHandler
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.weak CAN_RX1_IRQHandler
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.thumb_set CAN1_RX1_IRQHandler,Default_Handler
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.thumb_set CAN_RX1_IRQHandler,Default_Handler
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.weak CAN1_SCE_IRQHandler
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.weak CAN_SCE_IRQHandler
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.thumb_set CAN1_SCE_IRQHandler,Default_Handler
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.thumb_set CAN_SCE_IRQHandler,Default_Handler
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.weak EXTI9_5_IRQHandler
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.weak EXTI9_5_IRQHandler
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.thumb_set EXTI9_5_IRQHandler,Default_Handler
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.thumb_set EXTI9_5_IRQHandler,Default_Handler
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@ -1,288 +1,423 @@
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/* File: startup_STM32F40x.S
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/**
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* Purpose: startup file for Cortex-M4 devices. Should use with
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******************************************************************************
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* GCC for ARM Embedded Processors
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* @file startup_stm32f334x8.s
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* Version: V1.4
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* @author MCD Application Team
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* Date: 09 July 2012
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* @version V1.1.0
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*
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* @date 12-Sept-2014
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* Copyright (c) 2011, 2012, ARM Limited
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* @brief STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for
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* All rights reserved.
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* Atollic TrueSTUDIO toolchain.
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*
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* This module performs:
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* Redistribution and use in source and binary forms, with or without
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* - Set the initial SP
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* modification, are permitted provided that the following conditions are met:
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* - Set the initial PC == Reset_Handler,
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* Redistributions of source code must retain the above copyright
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* - Set the vector table entries with the exceptions ISR address,
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notice, this list of conditions and the following disclaimer.
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* - Configure the clock system
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* Redistributions in binary form must reproduce the above copyright
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* - Branches to main in the C library (which eventually
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notice, this list of conditions and the following disclaimer in the
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* calls main()).
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documentation and/or other materials provided with the distribution.
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* After Reset the Cortex-M4 processor is in Thread mode,
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* Neither the name of the ARM Limited nor the
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* priority is Privileged, and the Stack is set to Main.
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names of its contributors may be used to endorse or promote products
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******************************************************************************
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derived from this software without specific prior written permission.
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* @attention
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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*
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
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* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
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* You may not use this file except in compliance with the License.
|
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* You may obtain a copy of the License at:
|
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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*
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* http://www.st.com/software_license_agreement_liberty_v2
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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*
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* Unless required by applicable law or agreed to in writing, software
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* distributed under the License is distributed on an "AS IS" BASIS,
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*/
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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.syntax unified
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* See the License for the specific language governing permissions and
|
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.arch armv7-m
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* limitations under the License.
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*
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******************************************************************************
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*/
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.section .stack
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.syntax unified
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.align 3
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.cpu cortex-m4
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#ifdef __STACK_SIZE
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.fpu softvfp
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.equ Stack_Size, __STACK_SIZE
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.thumb
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#else
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.equ Stack_Size, 0xc00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.global g_pfnVectors
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.align 3
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.global Default_Handler
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x400
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
|
|
||||||
.if Heap_Size
|
|
||||||
.space Heap_Size
|
|
||||||
.endif
|
|
||||||
.size __HeapBase, . - __HeapBase
|
|
||||||
__HeapLimit:
|
|
||||||
.size __HeapLimit, . - __HeapLimit
|
|
||||||
|
|
||||||
.section .isr_vector
|
/* start address for the initialization values of the .data section.
|
||||||
.align 2
|
defined in linker script */
|
||||||
.globl __isr_vector
|
.word _sidata
|
||||||
__isr_vector:
|
/* start address for the .data section. defined in linker script */
|
||||||
.long __StackTop /* Top of Stack */
|
.word _sdata
|
||||||
.long Reset_Handler /* Reset Handler */
|
/* end address for the .data section. defined in linker script */
|
||||||
.long NMI_Handler /* NMI Handler */
|
.word _edata
|
||||||
.long HardFault_Handler /* Hard Fault Handler */
|
/* start address for the .bss section. defined in linker script */
|
||||||
.long MemManage_Handler /* MPU Fault Handler */
|
.word _sbss
|
||||||
.long BusFault_Handler /* Bus Fault Handler */
|
/* end address for the .bss section. defined in linker script */
|
||||||
.long UsageFault_Handler /* Usage Fault Handler */
|
.word _ebss
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long SVC_Handler /* SVCall Handler */
|
|
||||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long PendSV_Handler /* PendSV Handler */
|
|
||||||
.long SysTick_Handler /* SysTick Handler */
|
|
||||||
|
|
||||||
/* External interrupts */
|
.equ BootRAM, 0xF1E0F85F
|
||||||
.long WWDG_IRQHandler /* Window WatchDog */
|
/**
|
||||||
.long PVD_IRQHandler /* PVD through EXTI Line detection */
|
* @brief This is the code that gets called when the processor first
|
||||||
.long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
* starts execution following a reset event. Only the absolutely
|
||||||
.long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
* necessary set is performed, after which the application
|
||||||
.long FLASH_IRQHandler /* FLASH */
|
* supplied main() routine is called.
|
||||||
.long RCC_IRQHandler /* RCC */
|
* @param None
|
||||||
.long EXTI0_IRQHandler /* EXTI Line0 */
|
* @retval : None
|
||||||
.long EXTI1_IRQHandler /* EXTI Line1 */
|
*/
|
||||||
.long EXTI2_TSC_IRQHandler /* EXTI Line2 */
|
|
||||||
.long EXTI3_IRQHandler /* EXTI Line3 */
|
|
||||||
.long EXTI4_IRQHandler /* EXTI Line4 */
|
|
||||||
.long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
|
||||||
.long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
|
||||||
.long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
|
||||||
.long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
|
||||||
.long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
|
||||||
.long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
|
||||||
.long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
|
||||||
.long ADC1_2_IRQHandler /* ADC1, ADC2 and ADC3s */
|
|
||||||
.long CAN_TX_IRQHandler /* Reserved */
|
|
||||||
.long CAN_RX0_IRQHandler /* Reserved */
|
|
||||||
.long CAN_RX1_IRQHandler /* Reserved */
|
|
||||||
.long CAN_SCE_IRQHandler /* Reserved */
|
|
||||||
.long EXTI9_5_IRQHandler /* External Line[9:5]s */
|
|
||||||
.long TIM1_BRK_TIM15_IRQHandler /* TIM1 Break and TIM9 */
|
|
||||||
.long TIM1_UP_TIM16_IRQHandler /* TIM1 Update and TIM10 */
|
|
||||||
.long TIM1_TRG_COM_TIM17_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
|
||||||
.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
|
||||||
.long TIM2_IRQHandler /* TIM2 */
|
|
||||||
.long TIM3_IRQHandler /* TIM3 */
|
|
||||||
.long 0 /* TIM4 */
|
|
||||||
.long I2C1_EV_IRQHandler /* I2C1 Event */
|
|
||||||
.long I2C1_ER_IRQHandler /* I2C1 Error */
|
|
||||||
.long 0 /* I2C2 Event */
|
|
||||||
.long 0 /* I2C2 Error */
|
|
||||||
.long SPI1_IRQHandler /* SPI1 */
|
|
||||||
.long 0 /* SPI2 */
|
|
||||||
.long USART1_IRQHandler /* USART1 */
|
|
||||||
.long USART2_IRQHandler /* USART2 */
|
|
||||||
.long USART3_IRQHandler /* Reserved */
|
|
||||||
.long EXTI15_10_IRQHandler /* External Line[15:10]s */
|
|
||||||
.long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
|
||||||
.long 0 /* USB OTG FS Wakeup through EXTI line */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* DMA1 Stream7 */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* SDIO */
|
|
||||||
.long 0 /* TIM5 */
|
|
||||||
.long 0 /* SPI3 */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long TIM6_DAC1_IRQHandler /* Reserved */
|
|
||||||
.long TIM7_DAC2_IRQHandler /* Reserved */
|
|
||||||
.long 0 /* DMA2 Stream 0 */
|
|
||||||
.long 0 /* DMA2 Stream 1 */
|
|
||||||
.long 0 /* DMA2 Stream 2 */
|
|
||||||
.long 0 /* DMA2 Stream 3 */
|
|
||||||
.long 0 /* DMA2 Stream 4 */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long COMP2_IRQHandler /* Reserved */
|
|
||||||
.long COMP4_6_IRQHandler /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long HRTIM1_Master_IRQHandler /* USB OTG FS */
|
|
||||||
.long HRTIM1_TIMA_IRQHandler /* DMA2 Stream 5 */
|
|
||||||
.long HRTIM1_TIMB_IRQHandler /* DMA2 Stream 6 */
|
|
||||||
.long HRTIM1_TIMC_IRQHandler /* DMA2 Stream 7 */
|
|
||||||
.long HRTIM1_TIMD_IRQHandler /* USART6 */
|
|
||||||
.long HRTIM1_TIME_IRQHandler /* I2C3 event */
|
|
||||||
.long HRTIM1_FLT_IRQHandler /* I2C3 error */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long FPU_IRQHandler /* FPU */
|
|
||||||
|
|
||||||
.size __isr_vector, . - __isr_vector
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
.text
|
.type Reset_Handler, %function
|
||||||
.thumb
|
|
||||||
.thumb_func
|
|
||||||
.align 2
|
|
||||||
.globl Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
Reset_Handler:
|
||||||
/* Loop to copy data from read only memory to RAM. The ranges
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
||||||
* of copy from/to are specified by following symbols evaluated in
|
|
||||||
* linker script.
|
|
||||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
|
||||||
* __data_start__/__data_end__: RAM address range that data should be
|
|
||||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
|
||||||
|
|
||||||
ldr r1, =__etext
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
ldr r2, =__data_start__
|
movs r1, #0
|
||||||
ldr r3, =__data_end__
|
b LoopCopyDataInit
|
||||||
|
|
||||||
.LC0:
|
CopyDataInit:
|
||||||
cmp r2, r3
|
ldr r3, =_sidata
|
||||||
ittt lt
|
ldr r3, [r3, r1]
|
||||||
ldrlt r0, [r1], #4
|
str r3, [r0, r1]
|
||||||
strlt r0, [r2], #4
|
adds r1, r1, #4
|
||||||
blt .LC0
|
|
||||||
|
|
||||||
ldr r0, =SystemInit
|
LoopCopyDataInit:
|
||||||
blx r0
|
ldr r0, =_sdata
|
||||||
ldr r0, =_start
|
ldr r3, =_edata
|
||||||
bx r0
|
adds r2, r0, r1
|
||||||
.pool
|
cmp r2, r3
|
||||||
.size Reset_Handler, . - Reset_Handler
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
.text
|
LoopFillZerobss:
|
||||||
/* Macro to define default handlers. Default handler
|
ldr r3, = _ebss
|
||||||
* will be weak symbol and just dead loops. They can be
|
cmp r2, r3
|
||||||
* overwritten by other handlers */
|
bcc FillZerobss
|
||||||
.macro def_default_handler handler_name
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak \handler_name
|
|
||||||
.type \handler_name, %function
|
|
||||||
\handler_name :
|
|
||||||
b .
|
|
||||||
.size \handler_name, . - \handler_name
|
|
||||||
.endm
|
|
||||||
|
|
||||||
def_default_handler NMI_Handler
|
/* Call the clock system intitialization function.*/
|
||||||
def_default_handler HardFault_Handler
|
bl SystemInit
|
||||||
def_default_handler MemManage_Handler
|
/* Call static constructors */
|
||||||
def_default_handler BusFault_Handler
|
bl __libc_init_array
|
||||||
def_default_handler UsageFault_Handler
|
/* Call the application's entry point.*/
|
||||||
def_default_handler SVC_Handler
|
bl main
|
||||||
def_default_handler DebugMon_Handler
|
|
||||||
def_default_handler PendSV_Handler
|
|
||||||
def_default_handler SysTick_Handler
|
|
||||||
def_default_handler Default_Handler
|
|
||||||
|
|
||||||
.macro def_irq_default_handler handler_name
|
LoopForever:
|
||||||
.weak \handler_name
|
b LoopForever
|
||||||
.set \handler_name, Default_Handler
|
|
||||||
.endm
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
def_irq_default_handler WWDG_IRQHandler
|
/**
|
||||||
def_irq_default_handler PVD_IRQHandler
|
* @brief This is the code that gets called when the processor receives an
|
||||||
def_irq_default_handler TAMP_STAMP_IRQHandler
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
def_irq_default_handler RTC_WKUP_IRQHandler
|
* the system state for examination by a debugger.
|
||||||
def_irq_default_handler FLASH_IRQHandler
|
*
|
||||||
def_irq_default_handler RCC_IRQHandler
|
* @param None
|
||||||
def_irq_default_handler EXTI0_IRQHandler
|
* @retval : None
|
||||||
def_irq_default_handler EXTI1_IRQHandler
|
*/
|
||||||
def_irq_default_handler EXTI2_TSC_IRQHandler
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
def_irq_default_handler EXTI3_IRQHandler
|
Default_Handler:
|
||||||
def_irq_default_handler EXTI4_IRQHandler
|
Infinite_Loop:
|
||||||
def_irq_default_handler DMA1_Stream0_IRQHandler
|
b Infinite_Loop
|
||||||
def_irq_default_handler DMA1_Stream1_IRQHandler
|
.size Default_Handler, .-Default_Handler
|
||||||
def_irq_default_handler DMA1_Stream2_IRQHandler
|
/******************************************************************************
|
||||||
def_irq_default_handler DMA1_Stream3_IRQHandler
|
*
|
||||||
def_irq_default_handler DMA1_Stream4_IRQHandler
|
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||||
def_irq_default_handler DMA1_Stream5_IRQHandler
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
def_irq_default_handler DMA1_Stream6_IRQHandler
|
* 0x0000.0000.
|
||||||
def_irq_default_handler ADC1_2_IRQHandler
|
*
|
||||||
def_irq_default_handler CAN_TX_IRQHandler
|
******************************************************************************/
|
||||||
def_irq_default_handler CAN_RX0_IRQHandler
|
.section .isr_vector,"a",%progbits
|
||||||
def_irq_default_handler CAN_RX1_IRQHandler
|
.type g_pfnVectors, %object
|
||||||
def_irq_default_handler CAN_SCE_IRQHandler
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
def_irq_default_handler EXTI9_5_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_BRK_TIM15_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_UP_TIM16_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_TRG_COM_TIM17_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_CC_IRQHandler
|
|
||||||
def_irq_default_handler TIM2_IRQHandler
|
|
||||||
def_irq_default_handler TIM3_IRQHandler
|
|
||||||
def_irq_default_handler I2C1_EV_IRQHandler
|
|
||||||
def_irq_default_handler I2C1_ER_IRQHandler
|
|
||||||
def_irq_default_handler SPI1_IRQHandler
|
|
||||||
def_irq_default_handler USART1_IRQHandler
|
|
||||||
def_irq_default_handler USART2_IRQHandler
|
|
||||||
def_irq_default_handler USART3_IRQHandler
|
|
||||||
def_irq_default_handler EXTI15_10_IRQHandler
|
|
||||||
def_irq_default_handler RTC_Alarm_IRQHandler
|
|
||||||
def_irq_default_handler TIM6_DAC1_IRQHandler
|
|
||||||
def_irq_default_handler TIM7_DAC2_IRQHandler
|
|
||||||
def_irq_default_handler COMP2_IRQHandler
|
|
||||||
def_irq_default_handler COMP4_6_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_Master_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMA_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMB_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMC_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMD_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIME_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_FLT_IRQHandler
|
|
||||||
def_irq_default_handler FPU_IRQHandler
|
|
||||||
def_irq_default_handler DEF_IRQHandler
|
|
||||||
|
|
||||||
.end
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMP_STAMP_IRQHandler
|
||||||
|
.word RTC_WKUP_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_TSC_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word CAN_TX_IRQHandler
|
||||||
|
.word CAN_RX0_IRQHandler
|
||||||
|
.word CAN_RX1_IRQHandler
|
||||||
|
.word CAN_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.word TIM1_UP_TIM16_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM6_DAC1_IRQHandler
|
||||||
|
.word TIM7_DAC2_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word COMP2_IRQHandler
|
||||||
|
.word COMP4_6_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word HRTIM1_Master_IRQHandler
|
||||||
|
.word HRTIM1_TIMA_IRQHandler
|
||||||
|
.word HRTIM1_TIMB_IRQHandler
|
||||||
|
.word HRTIM1_TIMC_IRQHandler
|
||||||
|
.word HRTIM1_TIMD_IRQHandler
|
||||||
|
.word HRTIM1_TIME_IRQHandler
|
||||||
|
.word HRTIM1_FLT_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word FPU_IRQHandler
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_TSC_IRQHandler
|
||||||
|
.thumb_set EXTI2_TSC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_TX_IRQHandler
|
||||||
|
.thumb_set CAN_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_RX0_IRQHandler
|
||||||
|
.thumb_set CAN_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_RX1_IRQHandler
|
||||||
|
.thumb_set CAN_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_SCE_IRQHandler
|
||||||
|
.thumb_set CAN_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM16_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC1_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_DAC2_IRQHandler
|
||||||
|
.thumb_set TIM7_DAC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP2_IRQHandler
|
||||||
|
.thumb_set COMP2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP4_6_IRQHandler
|
||||||
|
.thumb_set COMP4_6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
|
|
@ -2,8 +2,8 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file startup_stm32f302x8.s
|
* @file startup_stm32f302x8.s
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @version V2.0.1
|
* @version V1.1.0
|
||||||
* @date 18-June-2014
|
* @date 12-Sept-2014
|
||||||
* @brief STM32F302x6/STM32F302x8 devices vector table for
|
* @brief STM32F302x6/STM32F302x8 devices vector table for
|
||||||
* Atollic TrueSTUDIO toolchain.
|
* Atollic TrueSTUDIO toolchain.
|
||||||
* This module performs:
|
* This module performs:
|
||||||
|
|
|
||||||
|
|
@ -1,288 +1,423 @@
|
||||||
/* File: startup_STM32F40x.S
|
/**
|
||||||
* Purpose: startup file for Cortex-M4 devices. Should use with
|
******************************************************************************
|
||||||
* GCC for ARM Embedded Processors
|
* @file startup_stm32f334x8.s
|
||||||
* Version: V1.4
|
* @author MCD Application Team
|
||||||
* Date: 09 July 2012
|
* @version V1.1.0
|
||||||
*
|
* @date 12-Sept-2014
|
||||||
* Copyright (c) 2011, 2012, ARM Limited
|
* @brief STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for
|
||||||
* All rights reserved.
|
* Atollic TrueSTUDIO toolchain.
|
||||||
*
|
* This module performs:
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* - Set the initial SP
|
||||||
* modification, are permitted provided that the following conditions are met:
|
* - Set the initial PC == Reset_Handler,
|
||||||
* Redistributions of source code must retain the above copyright
|
* - Set the vector table entries with the exceptions ISR address,
|
||||||
notice, this list of conditions and the following disclaimer.
|
* - Configure the clock system
|
||||||
* Redistributions in binary form must reproduce the above copyright
|
* - Branches to main in the C library (which eventually
|
||||||
notice, this list of conditions and the following disclaimer in the
|
* calls main()).
|
||||||
documentation and/or other materials provided with the distribution.
|
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||||
* Neither the name of the ARM Limited nor the
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
names of its contributors may be used to endorse or promote products
|
******************************************************************************
|
||||||
derived from this software without specific prior written permission.
|
* @attention
|
||||||
*
|
*
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
*
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
* You may not use this file except in compliance with the License.
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
* You may obtain a copy of the License at:
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
*
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
* http://www.st.com/software_license_agreement_liberty_v2
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
*
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
*/
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
.syntax unified
|
* See the License for the specific language governing permissions and
|
||||||
.arch armv7-m
|
* limitations under the License.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
.section .stack
|
.syntax unified
|
||||||
.align 3
|
.cpu cortex-m4
|
||||||
#ifdef __STACK_SIZE
|
.fpu softvfp
|
||||||
.equ Stack_Size, __STACK_SIZE
|
.thumb
|
||||||
#else
|
|
||||||
.equ Stack_Size, 0xc00
|
|
||||||
#endif
|
|
||||||
.globl __StackTop
|
|
||||||
.globl __StackLimit
|
|
||||||
__StackLimit:
|
|
||||||
.space Stack_Size
|
|
||||||
.size __StackLimit, . - __StackLimit
|
|
||||||
__StackTop:
|
|
||||||
.size __StackTop, . - __StackTop
|
|
||||||
|
|
||||||
.section .heap
|
.global g_pfnVectors
|
||||||
.align 3
|
.global Default_Handler
|
||||||
#ifdef __HEAP_SIZE
|
|
||||||
.equ Heap_Size, __HEAP_SIZE
|
|
||||||
#else
|
|
||||||
.equ Heap_Size, 0x400
|
|
||||||
#endif
|
|
||||||
.globl __HeapBase
|
|
||||||
.globl __HeapLimit
|
|
||||||
__HeapBase:
|
|
||||||
.if Heap_Size
|
|
||||||
.space Heap_Size
|
|
||||||
.endif
|
|
||||||
.size __HeapBase, . - __HeapBase
|
|
||||||
__HeapLimit:
|
|
||||||
.size __HeapLimit, . - __HeapLimit
|
|
||||||
|
|
||||||
.section .isr_vector
|
/* start address for the initialization values of the .data section.
|
||||||
.align 2
|
defined in linker script */
|
||||||
.globl __isr_vector
|
.word _sidata
|
||||||
__isr_vector:
|
/* start address for the .data section. defined in linker script */
|
||||||
.long __StackTop /* Top of Stack */
|
.word _sdata
|
||||||
.long Reset_Handler /* Reset Handler */
|
/* end address for the .data section. defined in linker script */
|
||||||
.long NMI_Handler /* NMI Handler */
|
.word _edata
|
||||||
.long HardFault_Handler /* Hard Fault Handler */
|
/* start address for the .bss section. defined in linker script */
|
||||||
.long MemManage_Handler /* MPU Fault Handler */
|
.word _sbss
|
||||||
.long BusFault_Handler /* Bus Fault Handler */
|
/* end address for the .bss section. defined in linker script */
|
||||||
.long UsageFault_Handler /* Usage Fault Handler */
|
.word _ebss
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long SVC_Handler /* SVCall Handler */
|
|
||||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long PendSV_Handler /* PendSV Handler */
|
|
||||||
.long SysTick_Handler /* SysTick Handler */
|
|
||||||
|
|
||||||
/* External interrupts */
|
.equ BootRAM, 0xF1E0F85F
|
||||||
.long WWDG_IRQHandler /* Window WatchDog */
|
/**
|
||||||
.long PVD_IRQHandler /* PVD through EXTI Line detection */
|
* @brief This is the code that gets called when the processor first
|
||||||
.long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
* starts execution following a reset event. Only the absolutely
|
||||||
.long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
* necessary set is performed, after which the application
|
||||||
.long FLASH_IRQHandler /* FLASH */
|
* supplied main() routine is called.
|
||||||
.long RCC_IRQHandler /* RCC */
|
* @param None
|
||||||
.long EXTI0_IRQHandler /* EXTI Line0 */
|
* @retval : None
|
||||||
.long EXTI1_IRQHandler /* EXTI Line1 */
|
*/
|
||||||
.long EXTI2_TSC_IRQHandler /* EXTI Line2 */
|
|
||||||
.long EXTI3_IRQHandler /* EXTI Line3 */
|
|
||||||
.long EXTI4_IRQHandler /* EXTI Line4 */
|
|
||||||
.long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
|
||||||
.long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
|
||||||
.long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
|
||||||
.long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
|
||||||
.long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
|
||||||
.long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
|
||||||
.long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
|
||||||
.long ADC1_2_IRQHandler /* ADC1, ADC2 and ADC3s */
|
|
||||||
.long CAN_TX_IRQHandler /* Reserved */
|
|
||||||
.long CAN_RX0_IRQHandler /* Reserved */
|
|
||||||
.long CAN_RX1_IRQHandler /* Reserved */
|
|
||||||
.long CAN_SCE_IRQHandler /* Reserved */
|
|
||||||
.long EXTI9_5_IRQHandler /* External Line[9:5]s */
|
|
||||||
.long TIM1_BRK_TIM15_IRQHandler /* TIM1 Break and TIM9 */
|
|
||||||
.long TIM1_UP_TIM16_IRQHandler /* TIM1 Update and TIM10 */
|
|
||||||
.long TIM1_TRG_COM_TIM17_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
|
||||||
.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
|
||||||
.long TIM2_IRQHandler /* TIM2 */
|
|
||||||
.long TIM3_IRQHandler /* TIM3 */
|
|
||||||
.long 0 /* TIM4 */
|
|
||||||
.long I2C1_EV_IRQHandler /* I2C1 Event */
|
|
||||||
.long I2C1_ER_IRQHandler /* I2C1 Error */
|
|
||||||
.long 0 /* I2C2 Event */
|
|
||||||
.long 0 /* I2C2 Error */
|
|
||||||
.long SPI1_IRQHandler /* SPI1 */
|
|
||||||
.long 0 /* SPI2 */
|
|
||||||
.long USART1_IRQHandler /* USART1 */
|
|
||||||
.long USART2_IRQHandler /* USART2 */
|
|
||||||
.long USART3_IRQHandler /* Reserved */
|
|
||||||
.long EXTI15_10_IRQHandler /* External Line[15:10]s */
|
|
||||||
.long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
|
||||||
.long 0 /* USB OTG FS Wakeup through EXTI line */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* DMA1 Stream7 */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* SDIO */
|
|
||||||
.long 0 /* TIM5 */
|
|
||||||
.long 0 /* SPI3 */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long TIM6_DAC1_IRQHandler /* Reserved */
|
|
||||||
.long TIM7_DAC2_IRQHandler /* Reserved */
|
|
||||||
.long 0 /* DMA2 Stream 0 */
|
|
||||||
.long 0 /* DMA2 Stream 1 */
|
|
||||||
.long 0 /* DMA2 Stream 2 */
|
|
||||||
.long 0 /* DMA2 Stream 3 */
|
|
||||||
.long 0 /* DMA2 Stream 4 */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long COMP2_IRQHandler /* Reserved */
|
|
||||||
.long COMP4_6_IRQHandler /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long HRTIM1_Master_IRQHandler /* USB OTG FS */
|
|
||||||
.long HRTIM1_TIMA_IRQHandler /* DMA2 Stream 5 */
|
|
||||||
.long HRTIM1_TIMB_IRQHandler /* DMA2 Stream 6 */
|
|
||||||
.long HRTIM1_TIMC_IRQHandler /* DMA2 Stream 7 */
|
|
||||||
.long HRTIM1_TIMD_IRQHandler /* USART6 */
|
|
||||||
.long HRTIM1_TIME_IRQHandler /* I2C3 event */
|
|
||||||
.long HRTIM1_FLT_IRQHandler /* I2C3 error */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long 0 /* Reserved */
|
|
||||||
.long FPU_IRQHandler /* FPU */
|
|
||||||
|
|
||||||
.size __isr_vector, . - __isr_vector
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
.text
|
.type Reset_Handler, %function
|
||||||
.thumb
|
|
||||||
.thumb_func
|
|
||||||
.align 2
|
|
||||||
.globl Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
Reset_Handler:
|
||||||
/* Loop to copy data from read only memory to RAM. The ranges
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
||||||
* of copy from/to are specified by following symbols evaluated in
|
|
||||||
* linker script.
|
|
||||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
|
||||||
* __data_start__/__data_end__: RAM address range that data should be
|
|
||||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
|
||||||
|
|
||||||
ldr r1, =__etext
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
ldr r2, =__data_start__
|
movs r1, #0
|
||||||
ldr r3, =__data_end__
|
b LoopCopyDataInit
|
||||||
|
|
||||||
.LC0:
|
CopyDataInit:
|
||||||
cmp r2, r3
|
ldr r3, =_sidata
|
||||||
ittt lt
|
ldr r3, [r3, r1]
|
||||||
ldrlt r0, [r1], #4
|
str r3, [r0, r1]
|
||||||
strlt r0, [r2], #4
|
adds r1, r1, #4
|
||||||
blt .LC0
|
|
||||||
|
|
||||||
ldr r0, =SystemInit
|
LoopCopyDataInit:
|
||||||
blx r0
|
ldr r0, =_sdata
|
||||||
ldr r0, =_start
|
ldr r3, =_edata
|
||||||
bx r0
|
adds r2, r0, r1
|
||||||
.pool
|
cmp r2, r3
|
||||||
.size Reset_Handler, . - Reset_Handler
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
.text
|
LoopFillZerobss:
|
||||||
/* Macro to define default handlers. Default handler
|
ldr r3, = _ebss
|
||||||
* will be weak symbol and just dead loops. They can be
|
cmp r2, r3
|
||||||
* overwritten by other handlers */
|
bcc FillZerobss
|
||||||
.macro def_default_handler handler_name
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak \handler_name
|
|
||||||
.type \handler_name, %function
|
|
||||||
\handler_name :
|
|
||||||
b .
|
|
||||||
.size \handler_name, . - \handler_name
|
|
||||||
.endm
|
|
||||||
|
|
||||||
def_default_handler NMI_Handler
|
/* Call the clock system intitialization function.*/
|
||||||
def_default_handler HardFault_Handler
|
bl SystemInit
|
||||||
def_default_handler MemManage_Handler
|
/* Call static constructors */
|
||||||
def_default_handler BusFault_Handler
|
bl __libc_init_array
|
||||||
def_default_handler UsageFault_Handler
|
/* Call the application's entry point.*/
|
||||||
def_default_handler SVC_Handler
|
bl main
|
||||||
def_default_handler DebugMon_Handler
|
|
||||||
def_default_handler PendSV_Handler
|
|
||||||
def_default_handler SysTick_Handler
|
|
||||||
def_default_handler Default_Handler
|
|
||||||
|
|
||||||
.macro def_irq_default_handler handler_name
|
LoopForever:
|
||||||
.weak \handler_name
|
b LoopForever
|
||||||
.set \handler_name, Default_Handler
|
|
||||||
.endm
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
def_irq_default_handler WWDG_IRQHandler
|
/**
|
||||||
def_irq_default_handler PVD_IRQHandler
|
* @brief This is the code that gets called when the processor receives an
|
||||||
def_irq_default_handler TAMP_STAMP_IRQHandler
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
def_irq_default_handler RTC_WKUP_IRQHandler
|
* the system state for examination by a debugger.
|
||||||
def_irq_default_handler FLASH_IRQHandler
|
*
|
||||||
def_irq_default_handler RCC_IRQHandler
|
* @param None
|
||||||
def_irq_default_handler EXTI0_IRQHandler
|
* @retval : None
|
||||||
def_irq_default_handler EXTI1_IRQHandler
|
*/
|
||||||
def_irq_default_handler EXTI2_TSC_IRQHandler
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
def_irq_default_handler EXTI3_IRQHandler
|
Default_Handler:
|
||||||
def_irq_default_handler EXTI4_IRQHandler
|
Infinite_Loop:
|
||||||
def_irq_default_handler DMA1_Stream0_IRQHandler
|
b Infinite_Loop
|
||||||
def_irq_default_handler DMA1_Stream1_IRQHandler
|
.size Default_Handler, .-Default_Handler
|
||||||
def_irq_default_handler DMA1_Stream2_IRQHandler
|
/******************************************************************************
|
||||||
def_irq_default_handler DMA1_Stream3_IRQHandler
|
*
|
||||||
def_irq_default_handler DMA1_Stream4_IRQHandler
|
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||||
def_irq_default_handler DMA1_Stream5_IRQHandler
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
def_irq_default_handler DMA1_Stream6_IRQHandler
|
* 0x0000.0000.
|
||||||
def_irq_default_handler ADC1_2_IRQHandler
|
*
|
||||||
def_irq_default_handler CAN_TX_IRQHandler
|
******************************************************************************/
|
||||||
def_irq_default_handler CAN_RX0_IRQHandler
|
.section .isr_vector,"a",%progbits
|
||||||
def_irq_default_handler CAN_RX1_IRQHandler
|
.type g_pfnVectors, %object
|
||||||
def_irq_default_handler CAN_SCE_IRQHandler
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
def_irq_default_handler EXTI9_5_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_BRK_TIM15_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_UP_TIM16_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_TRG_COM_TIM17_IRQHandler
|
|
||||||
def_irq_default_handler TIM1_CC_IRQHandler
|
|
||||||
def_irq_default_handler TIM2_IRQHandler
|
|
||||||
def_irq_default_handler TIM3_IRQHandler
|
|
||||||
def_irq_default_handler I2C1_EV_IRQHandler
|
|
||||||
def_irq_default_handler I2C1_ER_IRQHandler
|
|
||||||
def_irq_default_handler SPI1_IRQHandler
|
|
||||||
def_irq_default_handler USART1_IRQHandler
|
|
||||||
def_irq_default_handler USART2_IRQHandler
|
|
||||||
def_irq_default_handler USART3_IRQHandler
|
|
||||||
def_irq_default_handler EXTI15_10_IRQHandler
|
|
||||||
def_irq_default_handler RTC_Alarm_IRQHandler
|
|
||||||
def_irq_default_handler TIM6_DAC1_IRQHandler
|
|
||||||
def_irq_default_handler TIM7_DAC2_IRQHandler
|
|
||||||
def_irq_default_handler COMP2_IRQHandler
|
|
||||||
def_irq_default_handler COMP4_6_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_Master_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMA_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMB_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMC_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIMD_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_TIME_IRQHandler
|
|
||||||
def_irq_default_handler HRTIM1_FLT_IRQHandler
|
|
||||||
def_irq_default_handler FPU_IRQHandler
|
|
||||||
def_irq_default_handler DEF_IRQHandler
|
|
||||||
|
|
||||||
.end
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMP_STAMP_IRQHandler
|
||||||
|
.word RTC_WKUP_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_TSC_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word CAN_TX_IRQHandler
|
||||||
|
.word CAN_RX0_IRQHandler
|
||||||
|
.word CAN_RX1_IRQHandler
|
||||||
|
.word CAN_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.word TIM1_UP_TIM16_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM6_DAC1_IRQHandler
|
||||||
|
.word TIM7_DAC2_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word COMP2_IRQHandler
|
||||||
|
.word COMP4_6_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word HRTIM1_Master_IRQHandler
|
||||||
|
.word HRTIM1_TIMA_IRQHandler
|
||||||
|
.word HRTIM1_TIMB_IRQHandler
|
||||||
|
.word HRTIM1_TIMC_IRQHandler
|
||||||
|
.word HRTIM1_TIMD_IRQHandler
|
||||||
|
.word HRTIM1_TIME_IRQHandler
|
||||||
|
.word HRTIM1_FLT_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word FPU_IRQHandler
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_TSC_IRQHandler
|
||||||
|
.thumb_set EXTI2_TSC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_TX_IRQHandler
|
||||||
|
.thumb_set CAN_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_RX0_IRQHandler
|
||||||
|
.thumb_set CAN_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_RX1_IRQHandler
|
||||||
|
.thumb_set CAN_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN_SCE_IRQHandler
|
||||||
|
.thumb_set CAN_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM16_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC1_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_DAC2_IRQHandler
|
||||||
|
.thumb_set TIM7_DAC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP2_IRQHandler
|
||||||
|
.thumb_set COMP2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP4_6_IRQHandler
|
||||||
|
.thumb_set COMP4_6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue