diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s
index 820d8b91da..1bba55d456 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s
@@ -100,10 +100,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-// bl __libc_init_array
+ bl __libc_init_array
/* Call the application's entry point.*/
-// bl main
- bl _start
+ bl main
LoopForever:
b LoopForever
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s
index df1ecffff5..6ee8242f46 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s
@@ -100,10 +100,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
-// bl __libc_init_array
+ bl __libc_init_array
/* Call the application's entry point.*/
-// bl main
- bl _start
+ bl main
LoopForever:
b LoopForever
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f30x.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f303xc.s
similarity index 81%
rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f30x.s
rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f303xc.s
index 8bc24e04fe..35ca037e1e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f30x.s
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f303xc.s
@@ -1,17 +1,16 @@
/**
******************************************************************************
- * @file startup_stm32f30x.s
+ * @file startup_stm32f303xc.s
* @author MCD Application Team
- * @version V1.0.0
- * @date 04-Spetember-2012
- * @brief STM32F4xx Devices vector table for RIDE7 toolchain.
+ * @version V1.1.0
+ * @date 12-Sept-2014
+ * @brief STM32F303xB/STM32F303xC devices vector table for Atollic
+ * TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM3230C-EVAL board to be used as data memory (optional,
- * to be enabled by user)
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
@@ -19,7 +18,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2012 STMicroelectronics
+ * © COPYRIGHT 2014 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,101 +34,108 @@
*
******************************************************************************
*/
-
+
.syntax unified
- .cpu cortex-m4
- .fpu softvfp
- .thumb
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
-.global g_pfnVectors
-.global Default_Handler
+.global g_pfnVectors
+.global Default_Handler
-/* start address for the initialization values of the .data section.
+/* start address for the initialization values of the .data section.
defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
/* end address for the .data section. defined in linker script */
-.word _edata
+.word _edata
/* start address for the .bss section. defined in linker script */
-.word _sbss
+.word _sbss
/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+.word _ebss
+.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
- * supplied main() routine is called.
+ * supplied main() routine is called.
* @param None
* @retval : None
*/
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ movs r3, #0
+ str r3, [r2], #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
/* Call the clock system intitialization function.*/
- bl SystemInit
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
/* Call the application's entry point.*/
- bl _start
- bx lr
-.size Reset_Handler, .-Reset_Handler
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
/**
- * @brief This is the code that gets called when the processor receives an
+ * @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
- * @param None
- * @retval None
+ *
+ * @param None
+ * @retval : None
*/
- .section .text.Default_Handler,"ax",%progbits
+ .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
/******************************************************************************
*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
g_pfnVectors:
.word _estack
.word Reset_Handler
@@ -149,13 +155,13 @@ g_pfnVectors:
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
- .word TAMPER_STAMP_IRQHandler
+ .word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
- .word EXTI2_TS_IRQHandler
+ .word EXTI2_TSC_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
@@ -166,10 +172,10 @@ g_pfnVectors:
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
- .word USB_HP_CAN1_TX_IRQHandler
- .word USB_LP_CAN1_RX0_IRQHandler
- .word CAN1_RX1_IRQHandler
- .word CAN1_SCE_IRQHandler
+ .word USB_HP_CAN_TX_IRQHandler
+ .word USB_LP_CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
@@ -271,8 +277,8 @@ g_pfnVectors:
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
- .weak TAMPER_STAMP_IRQHandler
- .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
@@ -289,8 +295,8 @@ g_pfnVectors:
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
- .weak EXTI2_TS_IRQHandler
- .thumb_set EXTI2_TS_IRQHandler,Default_Handler
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
@@ -322,17 +328,17 @@ g_pfnVectors:
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
- .weak USB_HP_CAN1_TX_IRQHandler
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
- .weak USB_LP_CAN1_RX0_IRQHandler
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s
index 0e36a12055..aeedd2d4cd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s
@@ -1,288 +1,423 @@
-/* File: startup_STM32F40x.S
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.4
- * Date: 09 July 2012
- *
- * Copyright (c) 2011, 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
+/**
+ ******************************************************************************
+ * @file startup_stm32f334x8.s
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 12-Sept-2014
+ * @brief STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0xc00
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x400
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+.global g_pfnVectors
+.global Default_Handler
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
- /* External interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_IRQHandler /* PVD through EXTI Line detection */
- .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .long FLASH_IRQHandler /* FLASH */
- .long RCC_IRQHandler /* RCC */
- .long EXTI0_IRQHandler /* EXTI Line0 */
- .long EXTI1_IRQHandler /* EXTI Line1 */
- .long EXTI2_TSC_IRQHandler /* EXTI Line2 */
- .long EXTI3_IRQHandler /* EXTI Line3 */
- .long EXTI4_IRQHandler /* EXTI Line4 */
- .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .long ADC1_2_IRQHandler /* ADC1, ADC2 and ADC3s */
- .long CAN_TX_IRQHandler /* Reserved */
- .long CAN_RX0_IRQHandler /* Reserved */
- .long CAN_RX1_IRQHandler /* Reserved */
- .long CAN_SCE_IRQHandler /* Reserved */
- .long EXTI9_5_IRQHandler /* External Line[9:5]s */
- .long TIM1_BRK_TIM15_IRQHandler /* TIM1 Break and TIM9 */
- .long TIM1_UP_TIM16_IRQHandler /* TIM1 Update and TIM10 */
- .long TIM1_TRG_COM_TIM17_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long 0 /* TIM4 */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long 0 /* I2C2 Event */
- .long 0 /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long 0 /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* Reserved */
- .long EXTI15_10_IRQHandler /* External Line[15:10]s */
- .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .long 0 /* USB OTG FS Wakeup through EXTI line */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* DMA1 Stream7 */
- .long 0 /* Reserved */
- .long 0 /* SDIO */
- .long 0 /* TIM5 */
- .long 0 /* SPI3 */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long TIM6_DAC1_IRQHandler /* Reserved */
- .long TIM7_DAC2_IRQHandler /* Reserved */
- .long 0 /* DMA2 Stream 0 */
- .long 0 /* DMA2 Stream 1 */
- .long 0 /* DMA2 Stream 2 */
- .long 0 /* DMA2 Stream 3 */
- .long 0 /* DMA2 Stream 4 */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long COMP2_IRQHandler /* Reserved */
- .long COMP4_6_IRQHandler /* Reserved */
- .long 0 /* Reserved */
- .long HRTIM1_Master_IRQHandler /* USB OTG FS */
- .long HRTIM1_TIMA_IRQHandler /* DMA2 Stream 5 */
- .long HRTIM1_TIMB_IRQHandler /* DMA2 Stream 6 */
- .long HRTIM1_TIMC_IRQHandler /* DMA2 Stream 7 */
- .long HRTIM1_TIMD_IRQHandler /* USART6 */
- .long HRTIM1_TIME_IRQHandler /* I2C3 event */
- .long HRTIM1_FLT_IRQHandler /* I2C3 error */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long FPU_IRQHandler /* FPU */
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
- .size __isr_vector, . - __isr_vector
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
Reset_Handler:
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr sp, =_estack /* Atollic update: set stack pointer */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
-.LC0:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .LC0
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
- ldr r0, =SystemInit
- blx r0
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
- def_irq_default_handler WWDG_IRQHandler
- def_irq_default_handler PVD_IRQHandler
- def_irq_default_handler TAMP_STAMP_IRQHandler
- def_irq_default_handler RTC_WKUP_IRQHandler
- def_irq_default_handler FLASH_IRQHandler
- def_irq_default_handler RCC_IRQHandler
- def_irq_default_handler EXTI0_IRQHandler
- def_irq_default_handler EXTI1_IRQHandler
- def_irq_default_handler EXTI2_TSC_IRQHandler
- def_irq_default_handler EXTI3_IRQHandler
- def_irq_default_handler EXTI4_IRQHandler
- def_irq_default_handler DMA1_Stream0_IRQHandler
- def_irq_default_handler DMA1_Stream1_IRQHandler
- def_irq_default_handler DMA1_Stream2_IRQHandler
- def_irq_default_handler DMA1_Stream3_IRQHandler
- def_irq_default_handler DMA1_Stream4_IRQHandler
- def_irq_default_handler DMA1_Stream5_IRQHandler
- def_irq_default_handler DMA1_Stream6_IRQHandler
- def_irq_default_handler ADC1_2_IRQHandler
- def_irq_default_handler CAN_TX_IRQHandler
- def_irq_default_handler CAN_RX0_IRQHandler
- def_irq_default_handler CAN_RX1_IRQHandler
- def_irq_default_handler CAN_SCE_IRQHandler
- def_irq_default_handler EXTI9_5_IRQHandler
- def_irq_default_handler TIM1_BRK_TIM15_IRQHandler
- def_irq_default_handler TIM1_UP_TIM16_IRQHandler
- def_irq_default_handler TIM1_TRG_COM_TIM17_IRQHandler
- def_irq_default_handler TIM1_CC_IRQHandler
- def_irq_default_handler TIM2_IRQHandler
- def_irq_default_handler TIM3_IRQHandler
- def_irq_default_handler I2C1_EV_IRQHandler
- def_irq_default_handler I2C1_ER_IRQHandler
- def_irq_default_handler SPI1_IRQHandler
- def_irq_default_handler USART1_IRQHandler
- def_irq_default_handler USART2_IRQHandler
- def_irq_default_handler USART3_IRQHandler
- def_irq_default_handler EXTI15_10_IRQHandler
- def_irq_default_handler RTC_Alarm_IRQHandler
- def_irq_default_handler TIM6_DAC1_IRQHandler
- def_irq_default_handler TIM7_DAC2_IRQHandler
- def_irq_default_handler COMP2_IRQHandler
- def_irq_default_handler COMP4_6_IRQHandler
- def_irq_default_handler HRTIM1_Master_IRQHandler
- def_irq_default_handler HRTIM1_TIMA_IRQHandler
- def_irq_default_handler HRTIM1_TIMB_IRQHandler
- def_irq_default_handler HRTIM1_TIMC_IRQHandler
- def_irq_default_handler HRTIM1_TIMD_IRQHandler
- def_irq_default_handler HRTIM1_TIME_IRQHandler
- def_irq_default_handler HRTIM1_FLT_IRQHandler
- def_irq_default_handler FPU_IRQHandler
- def_irq_default_handler DEF_IRQHandler
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
- .end
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_DAC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word HRTIM1_Master_IRQHandler
+ .word HRTIM1_TIMA_IRQHandler
+ .word HRTIM1_TIMB_IRQHandler
+ .word HRTIM1_TIMC_IRQHandler
+ .word HRTIM1_TIMD_IRQHandler
+ .word HRTIM1_TIME_IRQHandler
+ .word HRTIM1_FLT_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_DAC2_IRQHandler
+ .thumb_set TIM7_DAC2_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s
index 18c4997a6c..1d3731f465 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.s
@@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32f302x8.s
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
+ * @version V1.1.0
+ * @date 12-Sept-2014
* @brief STM32F302x6/STM32F302x8 devices vector table for
* Atollic TrueSTUDIO toolchain.
* This module performs:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s
index 0e36a12055..aeedd2d4cd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.s
@@ -1,288 +1,423 @@
-/* File: startup_STM32F40x.S
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.4
- * Date: 09 July 2012
- *
- * Copyright (c) 2011, 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
+/**
+ ******************************************************************************
+ * @file startup_stm32f334x8.s
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 12-Sept-2014
+ * @brief STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0xc00
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x400
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+.global g_pfnVectors
+.global Default_Handler
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
- /* External interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_IRQHandler /* PVD through EXTI Line detection */
- .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .long FLASH_IRQHandler /* FLASH */
- .long RCC_IRQHandler /* RCC */
- .long EXTI0_IRQHandler /* EXTI Line0 */
- .long EXTI1_IRQHandler /* EXTI Line1 */
- .long EXTI2_TSC_IRQHandler /* EXTI Line2 */
- .long EXTI3_IRQHandler /* EXTI Line3 */
- .long EXTI4_IRQHandler /* EXTI Line4 */
- .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .long ADC1_2_IRQHandler /* ADC1, ADC2 and ADC3s */
- .long CAN_TX_IRQHandler /* Reserved */
- .long CAN_RX0_IRQHandler /* Reserved */
- .long CAN_RX1_IRQHandler /* Reserved */
- .long CAN_SCE_IRQHandler /* Reserved */
- .long EXTI9_5_IRQHandler /* External Line[9:5]s */
- .long TIM1_BRK_TIM15_IRQHandler /* TIM1 Break and TIM9 */
- .long TIM1_UP_TIM16_IRQHandler /* TIM1 Update and TIM10 */
- .long TIM1_TRG_COM_TIM17_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long 0 /* TIM4 */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long 0 /* I2C2 Event */
- .long 0 /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long 0 /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* Reserved */
- .long EXTI15_10_IRQHandler /* External Line[15:10]s */
- .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .long 0 /* USB OTG FS Wakeup through EXTI line */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* DMA1 Stream7 */
- .long 0 /* Reserved */
- .long 0 /* SDIO */
- .long 0 /* TIM5 */
- .long 0 /* SPI3 */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long TIM6_DAC1_IRQHandler /* Reserved */
- .long TIM7_DAC2_IRQHandler /* Reserved */
- .long 0 /* DMA2 Stream 0 */
- .long 0 /* DMA2 Stream 1 */
- .long 0 /* DMA2 Stream 2 */
- .long 0 /* DMA2 Stream 3 */
- .long 0 /* DMA2 Stream 4 */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long COMP2_IRQHandler /* Reserved */
- .long COMP4_6_IRQHandler /* Reserved */
- .long 0 /* Reserved */
- .long HRTIM1_Master_IRQHandler /* USB OTG FS */
- .long HRTIM1_TIMA_IRQHandler /* DMA2 Stream 5 */
- .long HRTIM1_TIMB_IRQHandler /* DMA2 Stream 6 */
- .long HRTIM1_TIMC_IRQHandler /* DMA2 Stream 7 */
- .long HRTIM1_TIMD_IRQHandler /* USART6 */
- .long HRTIM1_TIME_IRQHandler /* I2C3 event */
- .long HRTIM1_FLT_IRQHandler /* I2C3 error */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long FPU_IRQHandler /* FPU */
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
- .size __isr_vector, . - __isr_vector
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
Reset_Handler:
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr sp, =_estack /* Atollic update: set stack pointer */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
-.LC0:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .LC0
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
- ldr r0, =SystemInit
- blx r0
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
- def_irq_default_handler WWDG_IRQHandler
- def_irq_default_handler PVD_IRQHandler
- def_irq_default_handler TAMP_STAMP_IRQHandler
- def_irq_default_handler RTC_WKUP_IRQHandler
- def_irq_default_handler FLASH_IRQHandler
- def_irq_default_handler RCC_IRQHandler
- def_irq_default_handler EXTI0_IRQHandler
- def_irq_default_handler EXTI1_IRQHandler
- def_irq_default_handler EXTI2_TSC_IRQHandler
- def_irq_default_handler EXTI3_IRQHandler
- def_irq_default_handler EXTI4_IRQHandler
- def_irq_default_handler DMA1_Stream0_IRQHandler
- def_irq_default_handler DMA1_Stream1_IRQHandler
- def_irq_default_handler DMA1_Stream2_IRQHandler
- def_irq_default_handler DMA1_Stream3_IRQHandler
- def_irq_default_handler DMA1_Stream4_IRQHandler
- def_irq_default_handler DMA1_Stream5_IRQHandler
- def_irq_default_handler DMA1_Stream6_IRQHandler
- def_irq_default_handler ADC1_2_IRQHandler
- def_irq_default_handler CAN_TX_IRQHandler
- def_irq_default_handler CAN_RX0_IRQHandler
- def_irq_default_handler CAN_RX1_IRQHandler
- def_irq_default_handler CAN_SCE_IRQHandler
- def_irq_default_handler EXTI9_5_IRQHandler
- def_irq_default_handler TIM1_BRK_TIM15_IRQHandler
- def_irq_default_handler TIM1_UP_TIM16_IRQHandler
- def_irq_default_handler TIM1_TRG_COM_TIM17_IRQHandler
- def_irq_default_handler TIM1_CC_IRQHandler
- def_irq_default_handler TIM2_IRQHandler
- def_irq_default_handler TIM3_IRQHandler
- def_irq_default_handler I2C1_EV_IRQHandler
- def_irq_default_handler I2C1_ER_IRQHandler
- def_irq_default_handler SPI1_IRQHandler
- def_irq_default_handler USART1_IRQHandler
- def_irq_default_handler USART2_IRQHandler
- def_irq_default_handler USART3_IRQHandler
- def_irq_default_handler EXTI15_10_IRQHandler
- def_irq_default_handler RTC_Alarm_IRQHandler
- def_irq_default_handler TIM6_DAC1_IRQHandler
- def_irq_default_handler TIM7_DAC2_IRQHandler
- def_irq_default_handler COMP2_IRQHandler
- def_irq_default_handler COMP4_6_IRQHandler
- def_irq_default_handler HRTIM1_Master_IRQHandler
- def_irq_default_handler HRTIM1_TIMA_IRQHandler
- def_irq_default_handler HRTIM1_TIMB_IRQHandler
- def_irq_default_handler HRTIM1_TIMC_IRQHandler
- def_irq_default_handler HRTIM1_TIMD_IRQHandler
- def_irq_default_handler HRTIM1_TIME_IRQHandler
- def_irq_default_handler HRTIM1_FLT_IRQHandler
- def_irq_default_handler FPU_IRQHandler
- def_irq_default_handler DEF_IRQHandler
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
- .end
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_DAC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word HRTIM1_Master_IRQHandler
+ .word HRTIM1_TIMA_IRQHandler
+ .word HRTIM1_TIMB_IRQHandler
+ .word HRTIM1_TIMC_IRQHandler
+ .word HRTIM1_TIMD_IRQHandler
+ .word HRTIM1_TIME_IRQHandler
+ .word HRTIM1_FLT_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_DAC2_IRQHandler
+ .thumb_set TIM7_DAC2_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/