mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #372 from bcostm/dev_NUCLEO_F334R8
[NUCLEO_F334R8] Add platform filespull/367/head
Bogdan Marinescu
commit
8ef659bca8
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;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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;* File Name : startup_stm32f334x8.s
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;* Author : MCD Application Team
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;* Version : V2.0.1
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;* Date : 18-June-2014
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;* Description : STM32F334x4/x6/x8 devices vector table for MDK-ARM_MICRO toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
|
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20003000 ; Top of RAM
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_2_IRQHandler ; ADC1 and ADC2
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DCD CAN_TX_IRQHandler ; CAN TX
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DCD CAN_RX0_IRQHandler ; CAN RX0
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DCD CAN_RX1_IRQHandler ; CAN RX1
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DCD CAN_SCE_IRQHandler ; CAN SCE
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
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DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
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DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD 0 ; Reserved
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DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI1_IRQHandler ; SPI1
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DCD 0 ; Reserved
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DCD USART1_IRQHandler ; USART1 and EXTI Line 25
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DCD USART2_IRQHandler ; USART2 and EXTI Line 26
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DCD USART3_IRQHandler ; USART3 and EXTI Line 28
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
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DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD COMP2_IRQHandler ; COMP2
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DCD COMP4_6_IRQHandler ; COMP4 and COMP6
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DCD 0 ; Reserved
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DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
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DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
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DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
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DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
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DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
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DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
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DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD FPU_IRQHandler ; FPU
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_TSC_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_IRQHandler [WEAK]
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EXPORT DMA1_Channel2_IRQHandler [WEAK]
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EXPORT DMA1_Channel3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_IRQHandler [WEAK]
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EXPORT DMA1_Channel5_IRQHandler [WEAK]
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EXPORT DMA1_Channel6_IRQHandler [WEAK]
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EXPORT DMA1_Channel7_IRQHandler [WEAK]
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EXPORT ADC1_2_IRQHandler [WEAK]
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EXPORT CAN_TX_IRQHandler [WEAK]
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EXPORT CAN_RX0_IRQHandler [WEAK]
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EXPORT CAN_RX1_IRQHandler [WEAK]
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EXPORT CAN_SCE_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
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EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT TIM6_DAC1_IRQHandler [WEAK]
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EXPORT TIM7_DAC2_IRQHandler [WEAK]
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EXPORT COMP2_IRQHandler [WEAK]
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EXPORT COMP4_6_IRQHandler [WEAK]
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EXPORT HRTIM1_Master_IRQHandler [WEAK]
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EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
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EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
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EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
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EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
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EXPORT HRTIM1_TIME_IRQHandler [WEAK]
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EXPORT HRTIM1_FLT_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_IRQHandler
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TAMP_STAMP_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_TSC_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Channel1_IRQHandler
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DMA1_Channel2_IRQHandler
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DMA1_Channel3_IRQHandler
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DMA1_Channel4_IRQHandler
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DMA1_Channel5_IRQHandler
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DMA1_Channel6_IRQHandler
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DMA1_Channel7_IRQHandler
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ADC1_2_IRQHandler
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CAN_TX_IRQHandler
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CAN_RX0_IRQHandler
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CAN_RX1_IRQHandler
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CAN_SCE_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_TIM15_IRQHandler
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TIM1_UP_TIM16_IRQHandler
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TIM1_TRG_COM_TIM17_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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SPI1_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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USART3_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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TIM6_DAC1_IRQHandler
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TIM7_DAC2_IRQHandler
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COMP2_IRQHandler
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COMP4_6_IRQHandler
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HRTIM1_Master_IRQHandler
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HRTIM1_TIMA_IRQHandler
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HRTIM1_TIMB_IRQHandler
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HRTIM1_TIMC_IRQHandler
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HRTIM1_TIMD_IRQHandler
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HRTIM1_TIME_IRQHandler
|
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HRTIM1_FLT_IRQHandler
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FPU_IRQHandler
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B .
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ENDP
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ALIGN
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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@ -0,0 +1,45 @@
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; Scatter-Loading Description File
|
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
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; Copyright (c) 2014, STMicroelectronics
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
; STM32F334R8: 64KB FLASH (0x10000) + 12KB SRAM (0x3000)
|
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LR_IROM1 0x08000000 0x10000 { ; load region size_region
|
||||
|
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ER_IROM1 0x08000000 0x10000 { ; load address = execution address
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||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
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.ANY (+RO)
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}
|
||||
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; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
|
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RW_IRAM1 (0x20000000+0x188) (0x3000-0x188) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
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|
|
@ -0,0 +1,56 @@
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/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f334x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.0.1
|
||||
;* Date : 18-June-2014
|
||||
;* Description : STM32F334x4/x6/x8 devices vector table for MDK-ARM_STD toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
__initial_sp EQU 0x20003000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
|
||||
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
|
||||
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
|
||||
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
|
||||
DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
|
||||
DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
|
||||
DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
|
||||
DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
|
||||
DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
|
||||
DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT CAN_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC1_IRQHandler [WEAK]
|
||||
EXPORT TIM7_DAC2_IRQHandler [WEAK]
|
||||
EXPORT COMP2_IRQHandler [WEAK]
|
||||
EXPORT COMP4_6_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_TSC_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
CAN_TX_IRQHandler
|
||||
CAN_RX0_IRQHandler
|
||||
CAN_RX1_IRQHandler
|
||||
CAN_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
TIM6_DAC1_IRQHandler
|
||||
TIM7_DAC2_IRQHandler
|
||||
COMP2_IRQHandler
|
||||
COMP4_6_IRQHandler
|
||||
HRTIM1_Master_IRQHandler
|
||||
HRTIM1_TIMA_IRQHandler
|
||||
HRTIM1_TIMB_IRQHandler
|
||||
HRTIM1_TIMC_IRQHandler
|
||||
HRTIM1_TIMD_IRQHandler
|
||||
HRTIM1_TIME_IRQHandler
|
||||
HRTIM1_FLT_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
; Scatter-Loading Description File
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Copyright (c) 2014, STMicroelectronics
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
; STM32F334R8: 64KB FLASH (0x10000) + 12KB SRAM (0x3000)
|
||||
LR_IROM1 0x08000000 0x10000 { ; load region size_region
|
||||
|
||||
ER_IROM1 0x08000000 0x10000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
|
||||
RW_IRAM1 (0x20000000+0x188) (0x3000-0x188) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/* mbed Microcontroller Library
|
||||
* A generic CMSIS include header
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "stm32f3xx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
// STM32F334R8
|
||||
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||
// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
|
||||
// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
|
||||
#define NVIC_NUM_VECTORS 98
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,229 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F3xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f3xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F3xx_H
|
||||
#define __STM32F3xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
|
||||
!defined (STM32F302x8) && !defined (STM32F302xC) && \
|
||||
!defined (STM32F303x8) && \
|
||||
!defined (STM32F303xC) && !defined (STM32F358xx) && \
|
||||
!defined (STM32F373xC) && !defined (STM32F378xx) && \
|
||||
!defined (STM32F334x8) && !defined (STM32F328xx)
|
||||
/* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
|
||||
STM32F301R6 and STM32F301R8 Devices */
|
||||
/* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
|
||||
STM32F302R6 and STM32F302R8 Devices */
|
||||
/* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */
|
||||
/* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
|
||||
STM32F303R6 and STM32F303R8 Devices */
|
||||
/* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
|
||||
/* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC,
|
||||
STM32F373V8, STM32F373VB and STM32F373VC Devices */
|
||||
#define STM32F334x8 /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
|
||||
/* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
|
||||
/* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
|
||||
/* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
|
||||
/* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
#define USE_HAL_DRIVER
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.0.1
|
||||
*/
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8)
|
||||
#include "stm32f301x8.h"
|
||||
#elif defined(STM32F302x8)
|
||||
#include "stm32f302x8.h"
|
||||
#elif defined(STM32F302xC)
|
||||
#include "stm32f302xc.h"
|
||||
#elif defined(STM32F303x8)
|
||||
#include "stm32f303x8.h"
|
||||
#elif defined(STM32F303xC)
|
||||
#include "stm32f303xc.h"
|
||||
#elif defined(STM32F373xC)
|
||||
#include "stm32f373xc.h"
|
||||
#elif defined(STM32F334x8)
|
||||
#include "stm32f334x8.h"
|
||||
#elif defined(STM32F318xx)
|
||||
#include "stm32f318xx.h"
|
||||
#elif defined(STM32F328xx)
|
||||
#include "stm32f328xx.h"
|
||||
#elif defined(STM32F358xx)
|
||||
#include "stm32f358xx.h"
|
||||
#elif defined(STM32F378xx)
|
||||
#include "stm32f378xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32f3xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F3xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,463 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs categories:
|
||||
(+) HAL Initialization and de-initialization functions
|
||||
(+) HAL Control functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief STM32F3xx HAL Driver version number V1.0.1
|
||||
*/
|
||||
#define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F3xx_HAL_VERSION_SUB1 << 16)\
|
||||
|(__STM32F3xx_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F3xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
static __IO uint32_t uwTick;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) de-Initializes common part of the HAL
|
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) Systick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __Weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Flash prefetch,
|
||||
* Configures time base source, NVIC and Low level hardware
|
||||
*
|
||||
* @note This function is called at the beginning of program after reset and before
|
||||
* the clock configuration
|
||||
*
|
||||
* @note The Systick configuration is based on HSI clock, as HSI is the clock
|
||||
* used after a system Reset and the NVIC configuration is set to Priority group 4
|
||||
*
|
||||
* @note The time base configuration is based on MSI clock when exting from Reset.
|
||||
* Once done, time base tick start incrementing.
|
||||
* In the default implementation,Systick is used as source of time base.
|
||||
* the tick variable is incremented each 1ms in its ISR.
|
||||
*
|
||||
* @note
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Flash prefetch */
|
||||
#if (PREFETCH_ENABLE != 0)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the source
|
||||
* of time base.
|
||||
* This function is optional.
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__APB1_FORCE_RESET();
|
||||
__APB1_RELEASE_RESET();
|
||||
|
||||
__APB2_FORCE_RESET();
|
||||
__APB2_RELEASE_RESET();
|
||||
|
||||
__AHB_FORCE_RESET();
|
||||
__AHB_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the MSP.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The the SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority: Tick interrupt priorty.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
|
||||
|
||||
/*Configure the SysTick IRQ priority */
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/** @defgroup HAL_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) provide a tick value in millisecond
|
||||
(+) provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during Sleep mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implemetation, this variable is incremented each 1ms
|
||||
* in Systick ISR.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Povides a tick value in millisecond.
|
||||
* @note The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay: specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(__IO uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
while((HAL_GetTick() - tickstart) < Delay)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns the HAL revision
|
||||
* @param None
|
||||
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F3xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,675 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_H
|
||||
#define __STM32F3xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_BitAddress_AliasRegion
|
||||
* @brief SYSCFG registers bit address in the alias region
|
||||
* @{
|
||||
*/
|
||||
/* ------------ SYSCFG registers bit address in the alias region -------------*/
|
||||
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
|
||||
/* --- CFGR2 Register ---*/
|
||||
/* Alias word address of BYP_ADDR_PAR bit */
|
||||
#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
|
||||
#define BYPADDRPAR_BitNumber 0x04
|
||||
#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @defgroup HAL_DMA_Remapping
|
||||
* Elements values convention: 0xXXYYYYYY
|
||||
* - YYYYYY : Position in the register
|
||||
* - XX : Register index
|
||||
* - 00: CFGR1 register in SYSCFG
|
||||
* - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
|
||||
* @{
|
||||
*/
|
||||
#define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
|
||||
1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
|
||||
#define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
|
||||
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
|
||||
#define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
|
||||
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
|
||||
#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
|
||||
1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
|
||||
#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
|
||||
1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
|
||||
#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
|
||||
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
|
||||
#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
|
||||
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
|
||||
#if defined(SYSCFG_CFGR3_DMA_RMP)
|
||||
#if !defined(HAL_REMAP_CFGR3_MASK)
|
||||
#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
|
||||
#endif
|
||||
|
||||
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 2 */
|
||||
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 4 */
|
||||
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 6 */
|
||||
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 3 */
|
||||
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 5 */
|
||||
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 7 */
|
||||
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 7 */
|
||||
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 3 */
|
||||
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 5 */
|
||||
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 6 */
|
||||
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 2 */
|
||||
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 4 */
|
||||
#define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
|
||||
x0: No remap (ADC2 on DMA2)
|
||||
10: Map on DMA1 channel 2 */
|
||||
#define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
|
||||
11: Map on DMA1 channel 4 */
|
||||
#endif /* SYSCFG_CFGR3_DMA_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
#define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
|
||||
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
|
||||
#elif defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
#define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
|
||||
#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
/** @defgroup HAL_Trigger_Remapping
|
||||
* Elements values convention: 0xXXYYYYYY
|
||||
* - YYYYYY : Position in the register
|
||||
* - XX : Register index
|
||||
* - 00: CFGR1 register in SYSCFG
|
||||
* - 01: CFGR3 register in SYSCFG
|
||||
* @{
|
||||
*/
|
||||
#define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
|
||||
0: No remap (DAC trigger is TIM8_TRGO)
|
||||
1: Remap (DAC trigger is TIM3_TRGO) */
|
||||
#define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
|
||||
0: No remap
|
||||
1: Remap (TIM1_TRG3 = TIM17_OC) */
|
||||
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
|
||||
#if !defined(HAL_REMAP_CFGR3_MASK)
|
||||
#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
|
||||
#endif
|
||||
#define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
|
||||
0: Remap (DAC trigger is TIM15_TRGO)
|
||||
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
|
||||
#define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
|
||||
0: No remap
|
||||
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
|
||||
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
|
||||
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
|
||||
#else
|
||||
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
|
||||
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FastModePlus_I2C
|
||||
* @{
|
||||
*/
|
||||
#if defined(SYSCFG_CFGR1_I2C1_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< I2C1 fast mode Plus driving capability activation
|
||||
0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
|
||||
1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
|
||||
#endif /* SYSCFG_CFGR1_I2C1_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C2_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< I2C2 fast mode Plus driving capability activation
|
||||
0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
|
||||
1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
|
||||
#endif /* SYSCFG_CFGR1_I2C2_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< I2C3 fast mode Plus driving capability activation
|
||||
0: FM+ mode is not enabled on I2C3 pins selected through AF selection bits
|
||||
1: FM+ mode is enabled on I2C3 pins selected through AF selection bits */
|
||||
#endif /* SYSCFG_CFGR1_I2C3_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB6 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB7 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB8 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB9 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C3) == HAL_SYSCFG_FASTMODEPLUS_I2C3) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
|
||||
#elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
|
||||
#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
|
||||
#elif defined(SYSCFG_CFGR1_I2C1_FMP)
|
||||
#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
|
||||
#endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_RCR_PAGE0)
|
||||
/* CCM-SRAM defined */
|
||||
/** @defgroup HAL_Page_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
|
||||
#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
|
||||
#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
|
||||
#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
|
||||
#if defined(SYSCFG_RCR_PAGE4)
|
||||
/* More than 4KB CCM-SRAM defined */
|
||||
#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
|
||||
#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
|
||||
#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
|
||||
#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
|
||||
#endif /* SYSCFG_RCR_PAGE4 */
|
||||
|
||||
#if defined(SYSCFG_RCR_PAGE4)
|
||||
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= SYSCFG_RCR_PAGE7))
|
||||
#else
|
||||
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= SYSCFG_RCR_PAGE3))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_RCR_PAGE0 */
|
||||
|
||||
/** @defgroup HAL_SYSCFG_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
|
||||
|
||||
#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
|
||||
#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
|
||||
#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
|
||||
#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
|
||||
#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
|
||||
#define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
|
||||
#define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
|
||||
#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
|
||||
#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
|
||||
#define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
|
||||
#define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
|
||||
#define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
|
||||
#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
|
||||
#define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
|
||||
#define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
|
||||
#define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
|
||||
#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
|
||||
#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
|
||||
#endif /* */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
|
||||
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
|
||||
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
|
||||
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
|
||||
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE)
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE)
|
||||
/** @brief No Encoder mode
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
|
||||
/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
|
||||
/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
|
||||
/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
|
||||
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @brief DMA remapping enable/disable macros
|
||||
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
|
||||
}while(0)
|
||||
#elif defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @brief DMA remapping enable/disable macros
|
||||
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
/** @brief Fast mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
|
||||
SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
|
||||
SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
/** @brief SYSCFG interrupt enable/disable macros
|
||||
* @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
|
||||
*/
|
||||
#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
|
||||
SYSCFG->CFGR1 |= (__INTERRUPT__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
|
||||
SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
|
||||
}while(0)
|
||||
|
||||
#if defined(SYSCFG_CFGR1_USB_IT_RMP)
|
||||
/** @brief USB interrupt remapping enable/disable macros
|
||||
*/
|
||||
#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
|
||||
#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
|
||||
#endif /* SYSCFG_CFGR1_USB_IT_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_VBAT)
|
||||
/** @brief SYSCFG interrupt enable/disable macros
|
||||
*/
|
||||
#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
|
||||
#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
|
||||
#endif /* SYSCFG_CFGR1_VBAT */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
|
||||
/** @brief SYSCFG Break Lockup lock
|
||||
* Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_PVD_LOCK)
|
||||
/** @brief SYSCFG Break PVD lock
|
||||
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR2_PVD_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
|
||||
/** @brief SYSCFG Break SRAM PARITY lock
|
||||
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
|
||||
/** @brief Trigger remapping enable/disable macros
|
||||
* @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
|
||||
}while(0)
|
||||
#else
|
||||
/** @brief Trigger remapping enable/disable macros
|
||||
* @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
|
||||
/**
|
||||
* @brief Parity check on RAM disable macro
|
||||
* @note Disabling the parity check on RAM locks the configuration bit.
|
||||
* To re-enable the parity check on RAM perform a system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
|
||||
#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
|
||||
|
||||
#if defined(SYSCFG_RCR_PAGE0)
|
||||
/** @brief CCM RAM page write protection enable macro
|
||||
* @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
|
||||
* @note write protection can only be disabled by a system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
|
||||
SYSCFG->RCR |= (__PAGE_WP__); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_RCR_PAGE0 */
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(__IO uint32_t Delay);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
void HAL_EnableDBGSleepMode(void);
|
||||
void HAL_DisableDBGSleepMode(void);
|
||||
void HAL_EnableDBGStopMode(void);
|
||||
void HAL_DisableDBGStopMode(void);
|
||||
void HAL_EnableDBGStandbyMode(void);
|
||||
void HAL_DisableDBGStandbyMode(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,725 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc.c
|
||||
* @author MCD Application conversion
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* ++ Initialization and Configuration of ADC
|
||||
* + Operation functions
|
||||
* ++ Start, stop, get result of conversions of regular and injected
|
||||
* groups, using 3 possible modes: polling, interruption or DMA.
|
||||
* + Control functions
|
||||
* ++ Analog Watchdog configuration
|
||||
* ++ Channels configuration on regular group
|
||||
* + State functions
|
||||
* ++ ADC state machine management
|
||||
* ++ Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### ADC specific features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
|
||||
STM32F30xxC devices).
|
||||
|
||||
(#) Interrupt generation at the end of regular conversion, end of injected
|
||||
conversion, and in case of analog watchdog or overrun events.
|
||||
|
||||
(#) Single and continuous conversion modes.
|
||||
|
||||
(#) Scan mode for automatic conversion of channel 0 to channel 'n'.
|
||||
|
||||
(#) Data alignment with in-built data coherency.
|
||||
|
||||
(#) Channel-wise programmable sampling time.
|
||||
|
||||
(#) ADC conversion Regular or Injected groups.
|
||||
|
||||
(#) External trigger (timer or EXTI) with configurable polarity for both
|
||||
regular and injected groups.
|
||||
|
||||
(#) DMA request generation for transfer of conversions data of regular group.
|
||||
|
||||
(#) Multimode Dual mode (available on devices with 2 ADCs or more).
|
||||
|
||||
(#) Configurable DMA data storage in Multimode Dual mode (available on devices
|
||||
with 2 DCs or more).
|
||||
|
||||
(#) Configurable delay between conversions in Dual interleaved mode (available
|
||||
on devices with 2 DCs or more).
|
||||
|
||||
(#) ADC calibration
|
||||
|
||||
(#) ADC channels selectable single/differential input (available only on
|
||||
STM32F30xxC devices)
|
||||
|
||||
(#) ADC Injected sequencer&channels configuration context queue (available
|
||||
only on STM32F30xxC devices)
|
||||
|
||||
(#) ADC offset on injected and regular groups (offset on regular group
|
||||
available only on STM32F30xxC devices)
|
||||
|
||||
(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
|
||||
slower speed.
|
||||
|
||||
(#) ADC input range: from Vref– (connected to Vssa) to Vref+ (connected to
|
||||
Vdda or to an external voltage reference).
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Enable the ADC interface
|
||||
As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
|
||||
at RCC top level: clock source and clock prescaler.
|
||||
|
||||
For STM32F30x/STM32F33x devices:
|
||||
Two possible clock sources: synchronous clock derived from AHB clock
|
||||
or asynchronous clock derived from ADC dedicated PLL 72MHz.
|
||||
|
||||
For example, in case of device with a single ADC:
|
||||
__ADC1_CLK_ENABLE() (mandatory)
|
||||
__HAL_RCC_ADC1_CONFIG(RCC_ADC1PLLCLK_DIV1); (optional)
|
||||
|
||||
For example, in case of device with several ADCs:
|
||||
if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
|
||||
{
|
||||
__ADC12_CLK_ENABLE() (mandatory)
|
||||
__HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_DIV1); (optional)
|
||||
}
|
||||
else
|
||||
{
|
||||
__ADC34_CLK_ENABLE() (mandatory)
|
||||
__HAL_RCC_ADC34_CONFIG(RCC_ADC34PLLCLK_DIV1); (optional)
|
||||
}
|
||||
|
||||
For STM32F37x devices:
|
||||
Only one clock source: APB2 clock.
|
||||
Example:
|
||||
__HAL_RCC_ADC1_CONFIG(RCC_ADC1PCLK2_DIV2);
|
||||
|
||||
(#) ADC pins configuration
|
||||
(++) Enable the clock for the ADC GPIOs using the following function:
|
||||
__GPIOx_CLK_ENABLE();
|
||||
(++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
|
||||
|
||||
(#) Configure the ADC parameters (conversion resolution, data alignment,
|
||||
continuous mode, ...) using the HAL_ADC_Init() function.
|
||||
|
||||
(#) Activate the ADC peripheral using one of the start functions:
|
||||
HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()
|
||||
HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
|
||||
HAL_ADC_MultiModeStart_DMA().
|
||||
|
||||
*** Channels to regular group configuration ***
|
||||
============================================
|
||||
[..]
|
||||
(+) To configure the ADC regular group features, use
|
||||
HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
|
||||
(+) To activate the continuous mode, use the HAL_ADC_Init() function.
|
||||
(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
|
||||
|
||||
*** Multimode ADCs configuration ***
|
||||
======================================================
|
||||
[..]
|
||||
(+) Multimode feature is available on devices with 2 ADCs or more.
|
||||
(+) Refer to "Channels to regular group" description to
|
||||
configure the ADC1 and ADC2 regular groups.
|
||||
(+) Select the Multi mode ADC features (dual mode
|
||||
simultaneous, interleaved, ...) and configure the DMA mode using
|
||||
HAL_ADCEx_MultiModeConfigChannel() functions.
|
||||
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
|
||||
function.
|
||||
|
||||
*** DMA for regular configuration ***
|
||||
=============================================================
|
||||
[..]
|
||||
(+) To enable the DMA mode for regular group, use the
|
||||
HAL_ADC_Start_DMA() function.
|
||||
(+) To enable the generation of DMA requests continuously at the end of
|
||||
the last DMA transfer, use the HAL_ADC_Init() function.
|
||||
|
||||
*** Channels to injected group configuration ***
|
||||
=============================================
|
||||
[..]
|
||||
(+) To configure the ADC Injected channels group features, use
|
||||
HAL_ADCEx_InjectedConfigChannel() functions.
|
||||
(+) To activate the continuous mode, use the HAL_ADC_Init() function.
|
||||
(+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
|
||||
function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC
|
||||
* @brief ADC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the ADC.
|
||||
(+) De-initialize the ADC.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the ADC peripheral and regular group according to
|
||||
* parameters specified in structure "ADC_InitTypeDef".
|
||||
* @note As prerequisite, ADC clock must be configured at RCC top level
|
||||
* depending on both possible clock sources: PLL clock or AHB clock.
|
||||
* See commented example code below that can be copied and uncommented
|
||||
* into HAL_ADC_MspInit().
|
||||
* @note Possibility to update parameters on the fly:
|
||||
* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
|
||||
* coming from ADC state reset. Following calls to this function can
|
||||
* be used to reconfigure some parameters of ADC_InitTypeDef
|
||||
* structure on the fly, without modifying MSP configuration. If ADC
|
||||
* MSP has to be modified again, HAL_ADC_DeInit() must be called
|
||||
* before HAL_ADC_Init().
|
||||
* The setting of these parameters is conditioned to ADC state.
|
||||
* For parameters constraints, see comments of structure
|
||||
* "ADC_InitTypeDef".
|
||||
* @note This function configures the ADC within 2 scopes: scope of entire
|
||||
* ADC and scope of regular group. For parameters details, see comments
|
||||
* of structure "ADC_InitTypeDef".
|
||||
* @note For devices with several ADCs: parameters related to common ADC
|
||||
* registers (ADC clock mode) are set only if all ADCs sharing the
|
||||
* same common group are disabled.
|
||||
* If this is not the case, these common parameters setting are
|
||||
* bypassed without error reporting: it can be the intended behaviour in
|
||||
* case of update of a parameter of ADC_InitTypeDef on the fly,
|
||||
* without disabling the other ADCs sharing the same common group.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitialize the ADC peripheral registers to their default reset
|
||||
* values, with deinitialization of the ADC MSP.
|
||||
* @note For devices with several ADCs: reset of ADC common registers is done
|
||||
* only if all ADCs sharing the same common group are disabled.
|
||||
* If this is not the case, reset of these common parameters reset is
|
||||
* bypassed without error reporting: it can be the intended behaviour in
|
||||
* case of reset of a single ADC while the other ADCs sharing the same
|
||||
* common group is still running.
|
||||
* @note For devices with several ADCs: Global reset of all ADCs sharing a
|
||||
* common group is possible.
|
||||
* As this function is intended to reset a single ADC, to not impact
|
||||
* other ADCs, instructions for global reset of multiple ADCs have been
|
||||
* let commented below.
|
||||
* If needed, the example code can be copied and uncommented into
|
||||
* function HAL_ADC_MspDeInit().
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the ADC MSP.
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_MspInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the ADC MSP.
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_MspDeInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion of regular group.
|
||||
(+) Stop conversion of regular group.
|
||||
(+) Poll for conversion complete on regular group.
|
||||
(+) Poll for conversion event.
|
||||
(+) Get result of regular channel conversion.
|
||||
(+) Start conversion of regular group and enable interruptions.
|
||||
(+) Stop conversion of regular group and disable interruptions.
|
||||
(+) Handle ADC interrupt request
|
||||
(+) Start conversion of regular group and enable DMA transfer.
|
||||
(+) Stop conversion of regular group and disable ADC DMA transfer.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables ADC, starts conversion of regular group.
|
||||
* Interruptions enabled in this function: None.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC slave first, then ADC master.
|
||||
* For ADC slave, ADC is enabled only (conversion is not started).
|
||||
* For ADC master, ADC is enabled and multimode conversion is started.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop ADC conversion of regular group (and injected group in
|
||||
* case of auto_injection mode), disable ADC peripheral.
|
||||
* @note: ADC peripheral disable is forcing interruption of potential
|
||||
* conversion on injected group. If injected group is under use, it
|
||||
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC master first, then ADC slave.
|
||||
* For ADC master, converson is stopped and ADC is disabled.
|
||||
* For ADC slave, ADC is disabled only (conversion stop of ADC master
|
||||
* has already stopped conversion of ADC slave).
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for regular group conversion to be completed.
|
||||
* @param hadc: ADC handle
|
||||
* @param Timeout: Timeout value in millisecond.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Poll for conversion event.
|
||||
* @param hadc: ADC handle
|
||||
* @param EventType: the ADC event type.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
|
||||
* @arg AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
|
||||
* @arg AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
|
||||
* @arg OVR_EVENT: ADC Overrun event
|
||||
* @arg JQOVF_EVENT: ADC Injected context queue overflow event
|
||||
* @param Timeout: Timeout value in millisecond.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables ADC, starts conversion of regular group with interruption.
|
||||
* Interruptions enabled in this function: EOC (end of conversion),
|
||||
* overrun (if available).
|
||||
* Each of these interruptions has its dedicated callback function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC slave first, then ADC master.
|
||||
* For ADC slave, ADC is enabled only (conversion is not started).
|
||||
* For ADC master, ADC is enabled and multimode conversion is started.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop ADC conversion of regular group (and injected group in
|
||||
* case of auto_injection mode), disable interruption of
|
||||
* end-of-conversion, disable ADC peripheral.
|
||||
* @note: ADC peripheral disable is forcing interruption of potential
|
||||
* conversion on injected group. If injected group is under use, it
|
||||
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC master first, then ADC slave.
|
||||
* For ADC master, conversion is stopped and ADC is disabled.
|
||||
* For ADC slave, ADC is disabled only (conversion stop of ADC master
|
||||
* has already stopped conversion of ADC slave).
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables ADC, starts conversion of regular group and transfers result
|
||||
* through DMA.
|
||||
* Interruptions enabled in this function:
|
||||
* overrun (if available), DMA half transfer, DMA transfer complete.
|
||||
* Each of these interruptions has its dedicated callback function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function is for single-ADC mode only. For multimode, use the
|
||||
* dedicated MultimodeStart function.
|
||||
* @param hadc: ADC handle
|
||||
* @param pData: The destination Buffer address.
|
||||
* @param Length: The length of data to be transferred from ADC peripheral to memory.
|
||||
* @retval None
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop ADC conversion of regular group (and injected group in
|
||||
* case of auto_injection mode), disable ADC DMA transfer, disable
|
||||
* ADC peripheral.
|
||||
* @note: ADC peripheral disable is forcing interruption of potential
|
||||
* conversion on injected group. If injected group is under use, it
|
||||
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function is for single-ADC mode only. For multimode, use the
|
||||
* dedicated MultimodeStop function.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ADC regular group conversion result.
|
||||
* @param hadc: ADC handle
|
||||
* @retval Converted value
|
||||
*/
|
||||
__weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return ADC converted value */
|
||||
return hadc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles ADC interrupt request.
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion DMA half-transfer callback in non blocking mode
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Analog watchdog callback in non blocking mode.
|
||||
* @note: In case of several analog watchdog enabled, if needed to know
|
||||
which one triggered and on which ADCx, check Analog Watchdog flag
|
||||
ADC_FLAG_AWD1/2/3 into HAL_ADC_LevelOutOfWindowCallback() function.
|
||||
For example:"if (__HAL_ADC_GET_FLAG(hadc1, ADC_FLAG_AWD1) != RESET)"
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC error callback in non blocking mode
|
||||
* (ADC conversion with interruption or transfer by DMA)
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_ErrorCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure channels on regular group
|
||||
(+) Configure the analog watchdog
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the the selected channel to be linked to the regular
|
||||
* group.
|
||||
* @note In case of usage of internal measurement channels:
|
||||
* Vbat/VrefInt/TempSensor.
|
||||
* The recommended sampling time is at least:
|
||||
* - For devices STM32F37x: 17.1us for temperature sensor
|
||||
* - For the other STM32F3 devices: 2.2us for each of channels
|
||||
* Vbat/VrefInt/TempSensor.
|
||||
* These internal paths can be be disabled using function
|
||||
* HAL_ADC_DeInit().
|
||||
* @note Possibility to update parameters on the fly:
|
||||
* This function initializes channel into regular group, following
|
||||
* calls to this function can be used to reconfigure some parameters
|
||||
* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
|
||||
* the ADC.
|
||||
* The setting of these parameters is conditioned to ADC state.
|
||||
* For parameters constraints, see comments of structure
|
||||
* "ADC_ChannelConfTypeDef".
|
||||
* @param hadc: ADC handle
|
||||
* @param sConfig: Structure of ADC channel for regular group.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the analog watchdog.
|
||||
* @note Possibility to update parameters on the fly:
|
||||
* This function initializes the selected analog watchdog, following
|
||||
* calls to this function can be used to reconfigure some parameters
|
||||
* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
|
||||
* the ADC.
|
||||
* The setting of these parameters is conditioned to ADC state.
|
||||
* For parameters constraints, see comments of structure
|
||||
* "ADC_AnalogWDGConfTypeDef".
|
||||
* @param hadc: ADC handle
|
||||
* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group4 ADC Peripheral State functions
|
||||
* @brief ADC Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral state and errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions to get in run-time the status of the
|
||||
peripheral.
|
||||
(+) Check the ADC state
|
||||
(+) Check the ADC error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the ADC state
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Return ADC state */
|
||||
return hadc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the ADC error code
|
||||
* @param hadc: ADC handle
|
||||
* @retval ADC Error Code
|
||||
*/
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
return hadc->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file containing functions prototypes of ADC HAL library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_ADC_H
|
||||
#define __STM32F3xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
#include "stm32f3xx_hal_adc_ex.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL ADC state machine: ADC States structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
|
||||
HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
|
||||
HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
|
||||
HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
|
||||
HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
|
||||
HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
|
||||
HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
|
||||
HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
|
||||
HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
|
||||
HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
|
||||
HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
|
||||
HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog (main analog watchdog, present on all STM32 devices) */
|
||||
HAL_ADC_STATE_AWD2 = 0x07, /*!< ADC state analog watchdog (additional analog watchdog, present only on STM32F3 devices) */
|
||||
HAL_ADC_STATE_AWD3 = 0x08, /*!< ADC state analog watchdog (additional analog watchdog, present only on STM32F3 devices) */
|
||||
}HAL_ADC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
typedef struct __ADC_HandleTypeDef
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
ADC_InitTypeDef Init; /*!< ADC required parameters */
|
||||
|
||||
__IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
|
||||
__IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
}ADC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Macro
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset ADC handle state
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Include ADC HAL Extension module */
|
||||
#include "stm32f3xx_hal_adc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* Non-blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||||
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F3xx_ADC_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,782 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_CAN_H
|
||||
#define __STM32F3xx_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8) || \
|
||||
defined(STM32F328xx) || defined(STM32F358xx) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
|
||||
HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
|
||||
|
||||
}HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CAN Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_CAN_ERROR_EWG = 0x01, /*!< EWG error */
|
||||
HAL_CAN_ERROR_EPV = 0x02, /*!< EPV error */
|
||||
HAL_CAN_ERROR_BOF = 0x04, /*!< BOF error */
|
||||
HAL_CAN_ERROR_STF = 0x08, /*!< Stuff error */
|
||||
HAL_CAN_ERROR_FOR = 0x10, /*!< Form error */
|
||||
HAL_CAN_ERROR_ACK = 0x20, /*!< Acknowledgment error */
|
||||
HAL_CAN_ERROR_BR = 0x40, /*!< Bit recessive */
|
||||
HAL_CAN_ERROR_BD = 0x80, /*!< LEC dominant */
|
||||
HAL_CAN_ERROR_CRC = 0x100 /*!< LEC transfer error */
|
||||
}HAL_CAN_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
}CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t BankNumber; /*!< Select the start slave bank filter
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
|
||||
|
||||
}CAN_FilterConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Data[8]; /*!< Contains the data to be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
}CanTxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Data[8]; /*!< Contains the data to be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
|
||||
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
|
||||
|
||||
}CanRxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
|
||||
|
||||
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CAN locking object */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
__IO HAL_CAN_ErrorTypeDef ErrorCode; /*!< CAN Error code */
|
||||
|
||||
}CAN_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
|
||||
#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
|
||||
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
|
||||
#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
|
||||
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
|
||||
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_RQCP1) || \
|
||||
((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_FF0) || \
|
||||
((FLAG) == CAN_FLAG_FOV0) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_WKU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Time out for INAK bit */
|
||||
#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
|
||||
/* Time out for SLAK bit */
|
||||
#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
|
||||
|
||||
/* Mailboxes definition */
|
||||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
|
||||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
|
||||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __INTERRUPT__: CAN Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __INTERRUPT__: CAN Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Return the number of pending received messages.
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval The number of pending message.
|
||||
*/
|
||||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
|
||||
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
|
||||
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check the transmission status of a CAN Frame.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval The new status of transmission (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
|
||||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Release the specified receive FIFO.
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
|
||||
|
||||
/**
|
||||
* @brief Cancel a transmit request.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
|
||||
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
|
||||
|
||||
/**
|
||||
* @brief Enable or disables the DBG Freeze for CAN.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __NEWSTATE__: new state of the CAN peripheral.
|
||||
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||
* or DISABLE (CAN is working during debug).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||
|
||||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || */
|
||||
/* defined(STM32F334x8) || */
|
||||
/* defined(STM32F328xx) || defined(STM32F358xx) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_CAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,562 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CEC_H
|
||||
#define __STM32F3xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of @ref CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
|
||||
or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
|
||||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
|
||||
there is no error-bit generation in case of Short Bit Period Error detection in
|
||||
a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
|
||||
|
||||
uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
|
||||
own address (OAR). Messages addressed to different destination are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
|
||||
address (OAR) with positive acknowledge. Messages addressed to different destination
|
||||
are received, but without interfering with the CEC bus: no acknowledge sent. */
|
||||
|
||||
uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
|
||||
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
|
||||
HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
|
||||
HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
|
||||
HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
|
||||
HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
|
||||
HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
|
||||
}HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Error structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */
|
||||
HAL_CEC_ERROR_RXOVR = CEC_ISR_RXOVR, /*!< CEC Rx-Overrun */
|
||||
HAL_CEC_ERROR_BRE = CEC_ISR_BRE, /*!< CEC Rx Bit Rising Error */
|
||||
HAL_CEC_ERROR_SBPE = CEC_ISR_SBPE, /*!< CEC Rx Short Bit period Error */
|
||||
HAL_CEC_ERROR_LBPE = CEC_ISR_LBPE, /*!< CEC Rx Long Bit period Error */
|
||||
HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE, /*!< CEC Rx Missing Acknowledge */
|
||||
HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST, /*!< CEC Arbitration Lost */
|
||||
HAL_CEC_ERROR_TXUDR = CEC_ISR_TXUDR, /*!< CEC Tx-Buffer Underrun */
|
||||
HAL_CEC_ERROR_TXERR = CEC_ISR_TXERR, /*!< CEC Tx-Error */
|
||||
HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
}
|
||||
HAL_CEC_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CEC_TypeDef *Instance; /* CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /* CEC communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /* CEC Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef State; /* CEC communication state */
|
||||
|
||||
}CEC_HandleTypeDef;
|
||||
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
|
||||
#define IS_CEC_SIGNALFREETIME(SFT) ((SFT) <= CEC_CFGR_SFT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
#define IS_CEC_TOLERANCE(RXTOL) (((RXTOL) == CEC_STANDARD_TOLERANCE) || \
|
||||
((RXTOL) == CEC_EXTENDED_TOLERANCE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
#define IS_CEC_BRERXSTOP(BRERXSTOP) (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((BRERXSTOP) == CEC_RX_STOP_ON_BRE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
#define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
#define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
#define IS_CEC_SFTOP(SFTOP) (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((SFTOP) == CEC_SFT_START_ON_TX_RX_END))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
#define IS_CEC_LISTENING_MODE(MODE) (((MODE) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((MODE) == CEC_FULL_LISTENING_MODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle state
|
||||
* @param __HANDLE__: CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_ISR_RXBR : Rx-Byte Received
|
||||
* @arg CEC_ISR_RXEND : End of Reception
|
||||
* @arg CEC_ISR_RXOVR : Rx Overrun
|
||||
* @arg CEC_ISR_BRE : Rx Bit Rising Error
|
||||
* @arg CEC_ISR_SBPE : Rx Short Bit Period Error
|
||||
* @arg CEC_ISR_LBPE : Rx Long Bit Period Error
|
||||
* @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
|
||||
* @arg CEC_ISR_ARBLST : Arbitration lost
|
||||
* @arg CEC_ISR_TXBR : Tx-Byte Request
|
||||
* @arg CEC_ISR_TXEND : End of Transmission
|
||||
* @arg CEC_ISR_TXUDR : Tx-buffer Underrun
|
||||
* @arg CEC_ISR_TXERR : Tx Error
|
||||
* @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __FLAG__: specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_ISR_RXBR : Rx-Byte Received
|
||||
* @arg CEC_ISR_RXEND : End of Reception
|
||||
* @arg CEC_ISR_RXOVR : Rx Overrun
|
||||
* @arg CEC_ISR_BRE : Rx Bit Rising Error
|
||||
* @arg CEC_ISR_SBPE : Rx Short Bit Period Error
|
||||
* @arg CEC_ISR_LBPE : Rx Long Bit Period Error
|
||||
* @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
|
||||
* @arg CEC_ISR_ARBLST : Arbitration lost
|
||||
* @arg CEC_ISR_TXBR : Tx-Byte Request
|
||||
* @arg CEC_ISR_TXEND : End of Transmission
|
||||
* @arg CEC_ISR_TXUDR : Tx-buffer Underrun
|
||||
* @arg CEC_ISR_TXERR : Tx Error
|
||||
* @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
|
||||
* @arg CEC_IER_RXENDIE : End Of Reception IT Enable
|
||||
* @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
|
||||
* @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
|
||||
* @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
|
||||
* @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
|
||||
* @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
|
||||
* @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
|
||||
* @arg CEC_IER_TXENDIE : End of Transmission IT Enable
|
||||
* @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IER_TXERRIE : Tx-Error IT Enable
|
||||
* @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
|
||||
* @arg CEC_IER_RXENDIE : End Of Reception IT Enable
|
||||
* @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
|
||||
* @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
|
||||
* @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
|
||||
* @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
|
||||
* @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
|
||||
* @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
|
||||
* @arg CEC_IER_TXENDIE : End of Transmission IT Enable
|
||||
* @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IER_TXERRIE : Tx-Error IT Enable
|
||||
* @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
|
||||
* @arg CEC_IER_RXENDIE : End Of Reception IT Enable
|
||||
* @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
|
||||
* @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
|
||||
* @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
|
||||
* @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
|
||||
* @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
|
||||
* @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
|
||||
* @arg CEC_IER_TXENDIE : End of Transmission IT Enable
|
||||
* @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IER_TXERRIE : Tx-Error IT Enable
|
||||
* @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__: CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__: CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__: CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CEC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,663 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief COMP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + I/O operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### COMP Peripheral features #####
|
||||
================================================================================
|
||||
|
||||
[..]
|
||||
The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
|
||||
(#) The non inverting input and inverting input can be set to GPIO pins
|
||||
as shown in table1. COMP Inputs below for STM32F303xB/STM32F303xC as example.
|
||||
For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
|
||||
Reference Manual.
|
||||
|
||||
(#) The COMP output is available using HAL_COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins. Refer to table 2. COMP Outputs below for STM32F303xB/STM32F303xC as example.
|
||||
For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
|
||||
Reference Manual.
|
||||
|
||||
(#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
|
||||
Refer to table 3. COMP Outputs redirection to embedded timers below for STM32F303xB/STM32F303xC as example.
|
||||
For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
|
||||
Reference Manual.
|
||||
|
||||
(#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
|
||||
mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
|
||||
|
||||
(#) The seven comparators have interrupt capability with wake-up
|
||||
from Sleep and Stop modes (through the EXTI controller):
|
||||
(++) COMP1 is internally connected to EXTI Line 21
|
||||
(++) COMP2 is internally connected to EXTI Line 22
|
||||
(++) COMP3 is internally connected to EXTI Line 29
|
||||
(++) COMP4 is internally connected to EXTI Line 30
|
||||
(++) COMP5 is internally connected to EXTI Line 31
|
||||
(++) COMP6 is internally connected to EXTI Line 32
|
||||
(++) COMP7 is internally connected to EXTI Line 33
|
||||
From the corresponding IRQ handler, the right interrupt source can be retrieved with the
|
||||
macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are:
|
||||
(++) COMP_EXTI_LINE_COMP1_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP2_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP3_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP4_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP5_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP6_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP7_EVENT
|
||||
|
||||
[..] Table 1. COMP Inputs for the STM32F303xB/STM32F303xC devices
|
||||
+------------------------------------------------------------------------------------------+
|
||||
| | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-----------------|----------------|---------------|---------------------------------------|
|
||||
| | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
|
||||
| | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
|
||||
|-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
|
||||
| Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
|
||||
| Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
|
||||
+------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 2. COMP Outputs for the STM32F303xB/STM32F303xC devices
|
||||
+-------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-------|-------|-------|-------|-------|-------|-------|
|
||||
| PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
|
||||
| PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
|
||||
| PA6 | PA12 | --- | --- | --- | --- | --- |
|
||||
| PA11 | PB9 | --- | --- | --- | --- | --- |
|
||||
| PB8 | --- | --- | --- | --- | --- | --- |
|
||||
+-------------------------------------------------------+
|
||||
|
||||
[..] Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| + | + | + | + | + | + | + |
|
||||
| TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
|
||||
| | | | | | | |
|
||||
| TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
|
||||
| | | | | | | |
|
||||
| TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
|
||||
| | | | | | | |
|
||||
| TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 4. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC devices
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
|
||||
| | | | | | | |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators of all STM32F3xx devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Fill in the HAL_COMP_MspInit() to
|
||||
(++) Configure the comparator input in analog mode using HAL_GPIO_Init()
|
||||
(++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
|
||||
output to the GPIO pin
|
||||
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
|
||||
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
|
||||
interrupt vector using HAL_NVIC_EnableIRQ() function.
|
||||
|
||||
(#) Configure the comparator using HAL_COMP_Init() function:
|
||||
(++) Select the inverting input
|
||||
(++) Select the non-inverting input
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
(++) Select the event/interrupt mode
|
||||
|
||||
(#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode
|
||||
|
||||
(#) Read the comparator output level with HAL_COMP_GetOutputLevel()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions to initialize and de-initialize comparators
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP according to the specified
|
||||
* parameters in the COMP_InitTypeDef and create the associated handle.
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
|
||||
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
|
||||
assert_param(IS_COMP_MODE(hcomp->Init.Mode));
|
||||
assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
|
||||
assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
|
||||
|
||||
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED)
|
||||
{
|
||||
assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
|
||||
}
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
/* Init SYSCFG and the low level hardware to access comparators */
|
||||
__SYSCFG_CLK_ENABLE();
|
||||
|
||||
HAL_COMP_MspInit(hcomp);
|
||||
}
|
||||
|
||||
/* Set COMP parameters */
|
||||
/* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
|
||||
/* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
|
||||
/* Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value */
|
||||
/* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
|
||||
/* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
|
||||
/* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
|
||||
/* Set COMPxMODE bits according to hcomp->Init.Mode value */
|
||||
COMP_INIT(hcomp);
|
||||
|
||||
/* Initialize the COMP state*/
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the COMP peripheral
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set COMP_CSR register to reset value */
|
||||
COMP_DEINIT(hcomp);
|
||||
|
||||
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
|
||||
HAL_COMP_MspDeInit(hcomp);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP MSP.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes COMP MSP.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspDeInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_READY)
|
||||
{
|
||||
/* Enable the selected comparator */
|
||||
COMP_START(hcomp);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_BUSY)
|
||||
{
|
||||
/* Disable the selected comparator */
|
||||
COMP_STOP(hcomp);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the interrupt and starts the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t extiline = 0;
|
||||
|
||||
status = HAL_COMP_Start(hcomp);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Check the Exti Line output configuration */
|
||||
extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
/* Configure the rising edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
|
||||
{
|
||||
__HAL_COMP_EXTI_RISING_IT_ENABLE(extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_COMP_EXTI_RISING_IT_DISABLE(extiline);
|
||||
}
|
||||
/* Configure the falling edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
|
||||
{
|
||||
__HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline);
|
||||
}
|
||||
/* Enable Exti interrupt mode */
|
||||
__HAL_COMP_EXTI_ENABLE_IT(extiline);
|
||||
/* Clear COMP Exti pending bit */
|
||||
__HAL_COMP_EXTI_CLEAR_FLAG(extiline);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt and Stop the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Disable the Exti Line interrupt mode */
|
||||
__HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance));
|
||||
|
||||
status = HAL_COMP_Stop(hcomp);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator IRQ Handler
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
|
||||
/* Check COMP Exti flag */
|
||||
if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET)
|
||||
{
|
||||
/* Clear COMP Exti pending bit */
|
||||
__HAL_COMP_EXTI_CLEAR_FLAG(extiline);
|
||||
|
||||
/* COMP trigger user callback */
|
||||
HAL_COMP_TriggerCallback(hcomp);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator configuration.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set lock flag */
|
||||
hcomp->State |= COMP_STATE_BIT_LOCK;
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
COMP_LOCK(hcomp);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param hcomp: COMP handle
|
||||
* @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
|
||||
*
|
||||
*/
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t level=0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
|
||||
|
||||
if(level != 0)
|
||||
{
|
||||
return(COMP_OUTPUTLEVEL_HIGH);
|
||||
}
|
||||
return(COMP_OUTPUTLEVEL_LOW);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator callback.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_TriggerCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the COMP state
|
||||
* @param hcomp : COMP handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the COMP handle allocation */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
return HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->State;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_COMP_H
|
||||
#define __STM32F3xx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_InvertingInput */
|
||||
|
||||
uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_NonInvertingInput
|
||||
Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
|
||||
|
||||
uint32_t Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_Output */
|
||||
|
||||
uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_Hysteresis
|
||||
Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
|
||||
|
||||
uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_BlankingSrce
|
||||
Note: Not available on STM32F373xB/C and STM32F378xx devices */
|
||||
|
||||
uint32_t Mode; /*!< Selects the operating comsumption mode of the comparator
|
||||
to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMPEx_Mode
|
||||
Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
|
||||
|
||||
uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2, 4 or 6 if available).
|
||||
This parameter can be a value of @ref COMPEx_WindowMode */
|
||||
|
||||
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
|
||||
This parameter can be a value of @ref COMP_TriggerMode */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */
|
||||
HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
|
||||
HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */
|
||||
HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
|
||||
HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
|
||||
}HAL_COMP_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PPP Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
||||
|
||||
}COMP_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
|
||||
#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((POL) == COMP_OUTPUTPOL_INVERTED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_TriggerMode
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \
|
||||
((MODE) == COMP_TRIGGERMODE_IT_RISING) || \
|
||||
((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \
|
||||
((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
|
||||
#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
|
||||
|
||||
#define COMP_STATE_BIT_LOCK ((uint32_t)0x10)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset COMP handle state
|
||||
* @param __HANDLE__: COMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
|
||||
/* Include COMP HAL Extension module */
|
||||
#include "stm32f3xx_hal_comp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Callback in Interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_COMP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,311 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CONF_H
|
||||
#define __STM32F3xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_HRTIM_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_OPAMP_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SDADC_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_TSC_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
#if !defined (HSI_STARTUP_TIMEOUT)
|
||||
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
|
||||
#endif /* HSI_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)40000)
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
|
||||
* - External clock not generated on EVAL 373
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0
|
||||
#define PREFETCH_ENABLE 1
|
||||
#define INSTRUCTION_CACHE_ENABLE 0
|
||||
#define DATA_CACHE_ENABLE 0
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/*#define USE_FULL_ASSERT 1*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HRTIM_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_hrtim.h"
|
||||
#endif /* HAL_HRTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDADC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_sdadc.h"
|
||||
#endif /* HAL_SDADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_tsc.h"
|
||||
#endif /* HAL_TSC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,446 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CORTEX HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using Cortex HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
|
||||
@brief CORTEX_NVIC_Priority_Table
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority.
|
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority):
|
||||
(+@) Lowest pre-emption priority
|
||||
(+@) Lowest sub priority
|
||||
(+@) Lowest hardware priority (IRQ number)
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using Cortex HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
|
||||
inside the stm32f3xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_CORTEX_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provide the Cortex HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (pre-emption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup: The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn: External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority: the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CORTEX_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @param None
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn: External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @param PriorityGroup: the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if active else 0 */
|
||||
return NVIC_GetActive(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLKSOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,164 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CORTEX_H
|
||||
#define __STM32F3xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLKSOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Configures the SysTick clock source.
|
||||
* @param __CLKSRC__: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
|
||||
do { \
|
||||
if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
|
||||
{ \
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
|
||||
} \
|
||||
else \
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
|
||||
} while(0)
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,495 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CRC HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CRC peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable CRC AHB clock using __CRC_CLK_ENABLE();
|
||||
(+) Initialize CRC calculator
|
||||
- specify generating polynomial (IP default or non-default one)
|
||||
- specify initialization value (IP default or non-default one)
|
||||
- specify input data format
|
||||
- specify input or output data inversion mode if any
|
||||
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
|
||||
input data buffer starting with the previously computed CRC as
|
||||
initialization value
|
||||
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
|
||||
input data buffer starting with the defined initialization value
|
||||
(default or non-default) to initiate CRC calculation
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP
|
||||
(+) DeInitialize CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and creates the associated handle.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if(hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* check whether or not non-default generating polynomial has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
||||
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
||||
{
|
||||
/* initialize IP with default generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* initialize CRC IP with generating polynomial defined by user */
|
||||
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* check whether or not non-default CRC initial value has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
||||
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
||||
}
|
||||
|
||||
|
||||
/* set input data inversion mode */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
||||
|
||||
/* set output data inversion mode */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
||||
|
||||
/* makes sure the input data format (bytes, halfwords or words stream)
|
||||
* is properly specified by user */
|
||||
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC peripheral.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Check the CRC peripheral state */
|
||||
if(hcrc->State == HAL_CRC_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC MSP.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
using combination of the previous CRC value and the new one.
|
||||
|
||||
or
|
||||
|
||||
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with the previously computed CRC as initialization value.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0; /* CRC input data buffer index */
|
||||
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter Data to the CRC calculator */
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with hcrc->Instance->INIT as initialization value.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0; /* CRC input data buffer index */
|
||||
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
|
||||
* written in hcrc->Instance->DR) */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter 32-bit input data to the CRC calculator */
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
/* Specific 8-bit input data handling */
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
/* Specific 16-bit input data handling */
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i = 0; /* input data buffer index */
|
||||
|
||||
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
|
||||
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
|
||||
* handling by the IP */
|
||||
for(i = 0; i < (BufferLength/4); i++)
|
||||
{
|
||||
hcrc->Instance->DR = (pBuffer[4*i]<<24) | (pBuffer[4*i+1]<<16) | (pBuffer[4*i+2]<<8) | pBuffer[4*i+3];
|
||||
}
|
||||
/* last bytes specific handling */
|
||||
if ((BufferLength%4) != 0)
|
||||
{
|
||||
if (BufferLength%4 == 1)
|
||||
{
|
||||
*(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
|
||||
}
|
||||
if (BufferLength%4 == 2)
|
||||
{
|
||||
*(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1];
|
||||
}
|
||||
if (BufferLength%4 == 3)
|
||||
{
|
||||
*(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1];
|
||||
*(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enter 16-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i = 0; /* input data buffer index */
|
||||
|
||||
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
|
||||
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
|
||||
* a correct type handling by the IP */
|
||||
for(i = 0; i < (BufferLength/2); i++)
|
||||
{
|
||||
hcrc->Instance->DR = (pBuffer[2*i]<<16) | pBuffer[2*i+1];
|
||||
}
|
||||
if ((BufferLength%2) != 0)
|
||||
{
|
||||
*(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC state.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CRC_H
|
||||
#define __STM32F3xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
|
||||
}HAL_CRC_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Size_Definitions and indicates CRC length.
|
||||
Value can be either one of
|
||||
CRC_POLYLENGTH_32B (32-bit CRC)
|
||||
CRC_POLYLENGTH_16B (16-bit CRC)
|
||||
CRC_POLYLENGTH_8B (8-bit CRC)
|
||||
CRC_POLYLENGTH_7B (7-bit CRC) */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or
|
||||
CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
}CRC_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
}CRC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
|
||||
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
|
||||
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
|
||||
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32
|
||||
#define HAL_CRC_LENGTH_16B 16
|
||||
#define HAL_CRC_LENGTH_8B 8
|
||||
#define HAL_CRC_LENGTH_7B 7
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state
|
||||
* @param __HANDLE__: CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @param __INIT__ : 32-bit initial value
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Include CRC HAL Extension module */
|
||||
#include "stm32f3xx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/* Aliases for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended CRC HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CRC peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + I/O operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### <Product specific features/integration> #####
|
||||
================================================================================
|
||||
|
||||
[..] < This section can contain:
|
||||
(#) Description of the product specific implementation; all features
|
||||
that is specific to this IP: separate clock for RTC/LCD/IWDG/ADC,
|
||||
power domain (backup domain for the RTC)...
|
||||
(#) IP main features, only when needed and not mandatory for all IPs,
|
||||
ex. for xWDG, GPIO, COMP...
|
||||
>
|
||||
|
||||
[..] < You can add as much sections as needed.>
|
||||
|
||||
[..] < You can add as much sections as needed.>
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(+) Enable CRC AHB clock using __CRC_CLK_ENABLE();
|
||||
(+) Initialize CRC calculator
|
||||
- specify generating polynomial (IP default or non-default one)
|
||||
- specify initialization value (IP default or non-default one)
|
||||
- specify input data format
|
||||
- specify input or output data inversion mode if any
|
||||
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
|
||||
input data buffer starting with the previously computed CRC as
|
||||
initialization value
|
||||
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
|
||||
input data buffer starting with the defined initialization value
|
||||
(default or non-default) to initiate CRC calculation
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx
|
||||
* @brief CRC Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP
|
||||
(+) DeInitialize CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC polynomial if different from default one.
|
||||
* @param hcrc: CRC handle
|
||||
* @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
|
||||
* This parameter is written in normal representation, e.g.
|
||||
* for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
|
||||
* @param PolyLength: CRC polynomial length
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
|
||||
* @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
|
||||
* @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
|
||||
* @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
|
||||
{
|
||||
uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_POL_LENGTH(PolyLength));
|
||||
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while (((Pol & (0x1 << msb)) == 0) && (msb-- > 0));
|
||||
|
||||
switch (PolyLength)
|
||||
{
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B) return HAL_ERROR;
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B) return HAL_ERROR;
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B) return HAL_ERROR;
|
||||
break;
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
}
|
||||
|
||||
/* set generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, Pol);
|
||||
|
||||
/* set generating polynomial size */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Input data mode.
|
||||
* @param hcrc: CRC handle
|
||||
* @param InputReverseMode: Input Data inversion mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
|
||||
* @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
|
||||
* @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
|
||||
* @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set input data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Output data mode.
|
||||
* @param hcrc: CRC handle
|
||||
* @param OutputReverseMode: Output Data inversion mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value)
|
||||
* @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set output data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CRC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CRC_EX_H
|
||||
#define __STM32F3xx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
|
||||
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000)
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT)
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CRC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,707 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channels configuration: trigger, output buffer, data format
|
||||
* + DMA management
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
*** DAC Channels ***
|
||||
====================
|
||||
[..]
|
||||
The device integrates up to 3 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
|
||||
(#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
|
||||
(for STM32F3 devices having 2 channels on DAC1)
|
||||
(#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
|
||||
(for STM32F3 devices having 2 DAC)
|
||||
|
||||
*** DAC Triggers ***
|
||||
====================
|
||||
[..]
|
||||
Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
|
||||
[..]
|
||||
Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
|
||||
|
||||
(#) Software using DAC_Trigger_Software
|
||||
|
||||
*** DAC Buffer mode feature ***
|
||||
===============================
|
||||
[..]
|
||||
Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
[..]
|
||||
(@) Refer to the device datasheet for more details about output
|
||||
impedance value with and without output buffer.
|
||||
|
||||
*** DAC wave generation feature ***
|
||||
===================================
|
||||
[..]
|
||||
Both DAC channels of DAC1 can be used to generate
|
||||
note that wave generation is not available in DAC2.
|
||||
(#) Noise wave
|
||||
(#) Triangle wave
|
||||
|
||||
Wave generation is NOT available in DAC2.
|
||||
|
||||
*** DAC data format ***
|
||||
=======================
|
||||
[..]
|
||||
The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_ALIGN_8B_R
|
||||
(#) 12-bit left alignment using DAC_ALIGN_12B_L
|
||||
(#) 12-bit right alignment using DAC_ALIGN_12B_R
|
||||
|
||||
*** DAC data value to voltage correspondence ***
|
||||
================================================
|
||||
[..]
|
||||
The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation:
|
||||
DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
*** DMA requests ***
|
||||
=====================
|
||||
[..]
|
||||
A DMA1 or DMA2 request can be generated when an external trigger
|
||||
(but not a software trigger) occurs if DMA1 or DMA2 requests are
|
||||
enabled using HAL_DAC_Start_DMA()
|
||||
[..]
|
||||
DMA1 requests are mapped as following:
|
||||
(#) DAC1 channel1: mapped either on
|
||||
- DMA1 channel3
|
||||
- or DMA2 channel3 (for STM32F3 devices having 2 DMA)
|
||||
which must be already configured
|
||||
(#) DAC1 channel2:
|
||||
(for STM32F3 devices having 2 channels on DAC1)
|
||||
mapped either on
|
||||
- DMA1 channel4
|
||||
- or DMA2 channel4 (for STM32F3 devices having 2 DMA)
|
||||
which must be already configured
|
||||
|
||||
(#) DAC2 channel1: mapped either on
|
||||
(for STM32F3 devices having 2 DAC)
|
||||
- DMA1 channel4
|
||||
- or DMA2 channel4 (for STM32F3 devices having 2 DMA)
|
||||
which must be already configured
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) DAC APB clock must be enabled to get write access to DAC
|
||||
registers using HAL_DAC_Init()
|
||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
|
||||
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA
|
||||
functions
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start()
|
||||
(+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop()
|
||||
|
||||
*** DMA mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
|
||||
of data to be transfered at each end of conversion
|
||||
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
|
||||
function is executed and user can add his own code by customization of function pointer
|
||||
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
|
||||
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
|
||||
|
||||
*** Dual mode operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) When Dual mode is enabled
|
||||
(i.e DAC1 Channel1 and DAC1 Channel2 are used simultaneously)
|
||||
(for STM32F3 devices having 2 channels on DAC1).
|
||||
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously
|
||||
in Channel 1 and Channel 2.
|
||||
|
||||
*** Wave generation operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Use HAL_DACEx_TriangleWaveGenerate to generate Triangle signal.
|
||||
(+) Use HAL_DACEx_NoiseWaveGenerate to generate Noise signal.
|
||||
|
||||
Wave generation is NOT available in DAC2.
|
||||
|
||||
*** DAC HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DAC HAL driver.
|
||||
|
||||
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
|
||||
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
|
||||
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
|
||||
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DAC HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the DAC.
|
||||
(+) De-initialize the DAC.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified parameters
|
||||
* in the DAC_InitStruct.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
if(hdac->State == HAL_DAC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_DAC_MspInit(hdac);
|
||||
}
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_DAC_MspDeInit(hdac);
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
(+) Get result of dual mode conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << channel);
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, channel);
|
||||
|
||||
/* Disable the DMA Channel */
|
||||
/* Channel1 is used */
|
||||
if (channel == DAC1_CHANNEL_1)
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle1);
|
||||
}
|
||||
else /* Channel2 is used for */
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle2);
|
||||
}
|
||||
|
||||
/* Check if DMA Channel effectively disabled */
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
__weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure channels.
|
||||
(+) Configure Triangle wave generation.
|
||||
(+) Configure Noise wave generation.
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
(+) Set the specified data holding register value for Dual DAC channels.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param sConfig: DAC configuration structure.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = hdac->Instance->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << channel;
|
||||
/* Write to DAC CR */
|
||||
hdac->Instance->CR = tmpreg1;
|
||||
/* Disable wave generation */
|
||||
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group4 DAC Peripheral State functions
|
||||
* @brief DAC Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DAC state.
|
||||
(+) Check the DAC Errors.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the DAC state
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Return DAC state */
|
||||
return hdac->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DAC error code
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval DAC Error Code
|
||||
*/
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
return hdac->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallback1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for Channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DAC_H
|
||||
#define __STM32F3xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
|
||||
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DACEx_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
}DAC_ChannelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Error_Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
|
||||
#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
|
||||
#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
|
||||
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
|
||||
((WAVE) == DAC_WAVEGENERATION_NOISE) || \
|
||||
((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
|
||||
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
|
||||
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
|
||||
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
|
||||
((FLAG) == DAC_FLAG_DMAUDR2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
|
||||
|
||||
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
|
||||
((IT) == DAC_IT_DMAUDR2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
* @param __HANDLE__: DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
|
||||
/* Enable the DAC peripheral */
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/* Disable the DAC peripheral */
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/* Set DHR12R1 alignment */
|
||||
#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
|
||||
|
||||
/* Set DHR12R2 alignment */
|
||||
#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
|
||||
|
||||
/* Set DHR12RD alignment */
|
||||
#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
|
||||
|
||||
/* Enable the DAC interrupt */
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/* Disable the DAC interrupt */
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/* Get the selected DAC's flag status */
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/* Clear the DAC's flag */
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
#include "stm32f3xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F3xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,987 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended DAC HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (DAC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
@verbatim
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @brief DAC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC channel 2 is available on top of DAC channel 1 */
|
||||
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
#endif /* STM32F303xC STM32F358xx STM32F303x8 STM32F328xx STM32F302xC STM32F334x8 STM32F373xC STM32F378xx */
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* @param alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param data: Data to be loaded in the selected data holding register.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
assert_param(IS_DAC_DATA(data));
|
||||
|
||||
tmp = (uint32_t) (hdac->Instance);
|
||||
|
||||
/* DAC 1 has 1 or 2 channels - no DAC2 */
|
||||
#if defined(STM32F302xC) || defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F328xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp += __HAL_DHR12R1_ALIGNEMENT(alignment);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
else /* channel = DAC_CHANNEL_2 */
|
||||
{
|
||||
tmp += __HAL_DHR12R2_ALIGNEMENT(alignment);
|
||||
}
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || \
|
||||
defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 */
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripharal */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Check if software trigger enabled */
|
||||
if(((hdac->Instance->CR & DAC_CR_TEN1) == DAC_CR_TEN1) && ((hdac->Instance->CR & DAC_CR_TSEL1) == DAC_CR_TSEL1))
|
||||
{
|
||||
/* Enable the selected DAC software conversion */
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check if software trigger enabled */
|
||||
if(((hdac->Instance->CR & DAC_CR_TEN2) == DAC_CR_TEN2) && ((hdac->Instance->CR & DAC_CR_TSEL2) == DAC_CR_TSEL2))
|
||||
{
|
||||
/* Enable the selected DAC software conversion*/
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx)
|
||||
/* DAC 1 has 1 channels 1 */
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripharal */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
/* Check if software trigger enabled */
|
||||
if(((hdac->Instance->CR & DAC_CR_TEN1) == DAC_CR_TEN1) && ((hdac->Instance->CR & DAC_CR_TSEL1) == DAC_CR_TSEL1))
|
||||
{
|
||||
/* Enable the selected DAC software conversion */
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F328xx) || \
|
||||
defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 */
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @param pData: The destination peripheral Buffer address.
|
||||
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||
* @param alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||
|
||||
/* Set the DMA error callback for channel1 */
|
||||
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
|
||||
|
||||
/* Set the DMA error callback for channel2 */
|
||||
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
|
||||
}
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN1;
|
||||
|
||||
/* Case of use of channel 1 */
|
||||
switch(alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the selected DAC channel2 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN2;
|
||||
|
||||
/* Case of use of channel 2 */
|
||||
switch(alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx)
|
||||
/* DAC 1 has 1 channels 1 */
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @param pData: The destination peripheral Buffer address.
|
||||
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||
* @param alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Set the DMA transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||
|
||||
/* Set the DMA error callback for channel1 */
|
||||
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||
|
||||
/* Enable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN1;
|
||||
|
||||
/* Case of use of channel 1 */
|
||||
switch(alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 */
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
return hdac->Instance->DOR1;
|
||||
}
|
||||
else /* channel = DAC_CHANNEL_2 */
|
||||
{
|
||||
return hdac->Instance->DOR2;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx)
|
||||
/* DAC 1 has 1 channel (channel 1) */
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return hdac->Instance->DOR1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
/* DAC channel 2 is NOT available. Only DAC channel 1 is available */
|
||||
|
||||
/**
|
||||
* @brief Handles DAC interrupt request
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check Overrun flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to chanel1 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||
}
|
||||
}
|
||||
#endif /* STM32F301x8 STM32F302x8 STM32F318xx */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303x8) || defined(STM32F328xx)|| defined(STM32F302xC) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC channel 2 is available on top of DAC channel 1 */
|
||||
|
||||
/**
|
||||
* @brief Handles DAC interrupt request
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check Overrun flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to chanel1 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to channel2 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* STM32F303xC STM32F358xx STM32F303x8 STM32F328xx STM32F302xC STM32F334x8 STM32F373xC STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx
|
||||
* @brief DACEx Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC channel 2 is present in DAC 1 */
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param alignment: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param data2: Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @param data1: Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
assert_param(IS_DAC_DATA(data1));
|
||||
assert_param(IS_DAC_DATA(data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (alignment == DAC_ALIGN_8B_R)
|
||||
{
|
||||
data = ((uint32_t)data2 << 8) | data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)data2 << 16) | data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t) (hdac->Instance);
|
||||
tmp += __HAL_DHR12RD_ALIGNEMENT(alignment);
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC channel 2 is present in DAC 1 */
|
||||
tmp |= hdac->Instance->DOR2 << 16;
|
||||
#endif
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @param Amplitude: Select max triangle amplitude.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
|
||||
* @note Wave generation is not available in DAC2.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << channel;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << channel;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DAC_ConvCpltCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DAC_ErrorCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC channel 2 is available on top of DAC channel 1 */
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DACEx_ErrorCallbackCh2(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
#endif /* STM32F303xC STM32F358xx STM32F303x8 STM32F328xx STM32F334x8 STM32F373xC STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,313 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DAC_EX_H
|
||||
#define __STM32F3xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F318xx)
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F301x8 STM32F318xx */
|
||||
|
||||
#if defined(STM32F302x8)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F302x8 */
|
||||
|
||||
#if defined(STM32F302xC)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F302xC */
|
||||
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
|
||||
#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
|
||||
#if defined (STM32F303x8) || defined (STM32F328xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F303x8 || STM32F328xx */
|
||||
|
||||
|
||||
#if defined (STM32F373xC) || defined (STM32F378xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
|
||||
#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F334x8)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
|
||||
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
|
||||
#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
|
||||
|
||||
#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
|
||||
#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F334x8 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
|
||||
/* Aliases for compatibility */
|
||||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC1 Channel 1 */
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx) || defined(STM32F302xC)
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
|
||||
/* Aliases for compatibility */
|
||||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC1 Channel 1 */
|
||||
#define DAC1_CHANNEL_2 DAC_CHANNEL_2 /*!< DAC1 Channel 2 */
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#endif /* STM32F303xC STM32F358xx STM32F302xC */
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC)|| defined (STM32F378xx) || defined (STM32F328xx)
|
||||
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
|
||||
|
||||
/* Aliases for compatibility */
|
||||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC1 Channel 1 */
|
||||
#define DAC1_CHANNEL_2 DAC_CHANNEL_2 /*!< DAC1 Channel 2 */
|
||||
#define DAC2_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC2 Channel 1 */
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Extension features functions ***********************************************/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2);
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_HAL_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DEF
|
||||
#define __STM32F3xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL (void *) 0
|
||||
#endif
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFF
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
|
||||
(__DMA_HANDLE_).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F3xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,679 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary) please refer to Reference manual for connection between peripherals
|
||||
and DMA requests .
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Transfer Direction, Source and Destination data formats,
|
||||
Circular, Normal or peripheral flow control mode, Channel Priority level,
|
||||
Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
|
||||
Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred. In this
|
||||
case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DMA HAL driver.
|
||||
|
||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
|
||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
|
||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_IT_STATUS: Check whether the specified DMA Channel interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and create the associated handle.
|
||||
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DMA peripheral
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma->State == HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0;
|
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */
|
||||
hdma->Instance->CNDTR = 0;
|
||||
|
||||
/* Reset DMA Channel peripheral address register */
|
||||
hdma->Instance->CPAR = 0;
|
||||
|
||||
/* Reset DMA Channel memory address register */
|
||||
hdma->Instance->CMAR = 0;
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
|
||||
|
||||
/* Enable the Half transfer complete interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
|
||||
|
||||
/* Enable the transfer Error interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @note After disabling a DMA Channel, a check for wait until the DMA Channel is
|
||||
* effectively disabled is added. If a Channel is disabled
|
||||
* while a data transfer is ongoing, the current data will be transferred
|
||||
* and the Channel will be effectively disabled only after the transfer of
|
||||
* this single data is finished.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tickstart = 0x00;
|
||||
|
||||
/* Disable the channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if the DMA Channel is effectively disabled */
|
||||
while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if((HAL_GetTick()-tickstart) > HAL_TIMEOUT_DMA_ABORT)
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Change the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel: Specifies the DMA level complete.
|
||||
* @param Timeout: Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart = 0x00;
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
|
||||
}
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
|
||||
{
|
||||
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
|
||||
{
|
||||
/* Clear the transfer error flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DMA interrupt request.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Transfer Error Interrupt management ***************************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
|
||||
{
|
||||
/* Disable the transfer error interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
|
||||
|
||||
/* Clear the transfer error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF;
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
|
||||
{
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable the transfer complete interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
|
||||
}
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the DMA Transfer parameter.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,420 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DMA_H
|
||||
#define __STM32F3xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration enumeration values definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
|
||||
DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
|
||||
|
||||
} DMA_ControlTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
|
||||
HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
|
||||
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
|
||||
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
|
||||
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
} DMA_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_buffer_size
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Memory_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__: DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt has occurred or not.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f3xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DMA_EX_H
|
||||
#define __STM32F3xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
|
||||
/** @defgroup STM32F302xC_STM32F303xC_STM32F373xC Product devices
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
||||
(DMA1->ISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
||||
(DMA1->IFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#else
|
||||
|
||||
/** @defgroup STM32F301x8_STM32F302x8_STM32F303x8_STM32F334x8 Product devices
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,694 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F3xx devices. These functions are split in 3 groups:
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page, erase all pages
|
||||
(++) Program functions: half word and word
|
||||
|
||||
(#) Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Erase Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Program the data Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the half cycle access
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Erase operations */
|
||||
void FLASH_PageErase(uint32_t PageAddress);
|
||||
|
||||
/* Program operations */
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations (write/erase).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: Specifies the address to be programmed.
|
||||
* @param Data: Specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint8_t index = 0;
|
||||
uint8_t nbiterations = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
nbiterations = 1;
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_WORD)
|
||||
{
|
||||
/* Program word (32-bit = 2*16-bit) at a specified address. */
|
||||
nbiterations = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */
|
||||
nbiterations = 4;
|
||||
}
|
||||
|
||||
for (index = 0; index < nbiterations; index++)
|
||||
{
|
||||
FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: Specifies the address to be programmed.
|
||||
* @param Data: Specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.Data = Data;
|
||||
|
||||
if(TypeProgram == TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
pFlash.DataRemaining = 1;
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_WORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
|
||||
/*Program word (32-bit : 2*16-bit) at a specified address.*/
|
||||
pFlash.DataRemaining = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
|
||||
/*Program double word (64-bit : 4*16-bit) at a specified address.*/
|
||||
pFlash.DataRemaining = 4;
|
||||
}
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t)Data);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp;
|
||||
/* If the operation is completed, disable the PG, PER and MER Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Indicate user which page address has been erased*/
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
|
||||
/* Check if there are still pages to erase*/
|
||||
if(pFlash.DataRemaining != 0)
|
||||
{
|
||||
/* Increment page address to next page */
|
||||
pFlash.Address += FLASH_PAGE_SIZE;
|
||||
addresstmp = pFlash.Address;
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*No more pages to Erase*/
|
||||
|
||||
/*Reset Address and stop Erase pages procedure*/
|
||||
pFlash.Address = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/*MassErase ended. Return the selected bank*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(0);
|
||||
|
||||
/* Stop Mass Erase procedure*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nb of 16-bit data to program can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still 16-bit data to program */
|
||||
if(pFlash.DataRemaining != 0)
|
||||
{
|
||||
/* Increment address to 16-bit */
|
||||
pFlash.Address += 2;
|
||||
addresstmp = pFlash.Address;
|
||||
|
||||
/* Shift to have next 16-bit data */
|
||||
pFlash.Data = (pFlash.Data >> 16);
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program ended. Return the selected address*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
|
||||
}
|
||||
|
||||
/* Reset Address and stop Program procedure*/
|
||||
pFlash.Address = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the Error code*/
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(pFlash.Address);
|
||||
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Reset address and stop the procedure ongoing*/
|
||||
pFlash.Address = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
if((READ_BIT(FLASH->CR, FLASH_CR_LOCK)) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if((READ_BIT(FLASH->CR, FLASH_CR_OPTWRE)) == RESET)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the bit to force the option byte reloading */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_FLASH_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @param None
|
||||
* @retval FLASH_ErrorCode: The returned value can be:
|
||||
* @arg FLASH_ERROR_PG: FLASH Programming error flag
|
||||
* @arg FLASH_ERROR_WRP: FLASH Write protected error flag
|
||||
*/
|
||||
FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Proceed to program the new data */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout: maximum flash operationtimeout
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* If there is an error flag set */
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erase the specified FLASH memory page
|
||||
* @param PageAddress: FLASH page to erase
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t PageAddress)
|
||||
{
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
WRITE_REG(FLASH->AR, PageAddress);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode = FLASH_ERROR_WRP;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_PG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,504 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_FLASH_H
|
||||
#define __STM32F3xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Error source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_ERROR_PG = 0x01,
|
||||
FLASH_ERROR_WRP = 0x02
|
||||
} FLASH_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASH_Type_Erase */
|
||||
|
||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
||||
This parameter must be a value of @ref FLASHEx_Address */
|
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
||||
This parameter must be a value between 1 and (max number of pages - value of initial page)*/
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Options bytes program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASH_OB_Type */
|
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASH_OB_WRP_State */
|
||||
|
||||
uint32_t WRPPage; /*!< WRPSector: specifies the page(s) to be write protected
|
||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
|
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
||||
This parameter can be a value of @ref FLASH_OB_Read_Protection */
|
||||
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
|
||||
This parameter can be a combination of @ref FLASH_OB_IWatchdog, @ref FLASH_OB_nRST_STOP,
|
||||
@ref FLASH_OB_nRST_STDBY, @ref FLASH_OB_BOOT1, @ref FLASH_OB_VDDA_Analog_Monitoring,
|
||||
@ref FLASH_OB_SRAM_Parity_Enable and @ref FLASH_OB_SDADC12_VDD_MONITOR */
|
||||
|
||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed
|
||||
This parameter can be a value of @ref FLASH_OB_Data_Address */
|
||||
|
||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
||||
This parameter can have any value */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0,
|
||||
FLASH_PROC_PAGEERASE = 1,
|
||||
FLASH_PROC_MASSERASE = 2,
|
||||
FLASH_PROC_PROGRAMHALFWORD = 3,
|
||||
FLASH_PROC_PROGRAMWORD = 4,
|
||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t DataRemaining; /* Internal variable to save the remaining pages to erase or half-word to program in IT context */
|
||||
|
||||
__IO uint32_t Address; /* Internal variable to save address selected for program or erase */
|
||||
|
||||
__IO uint64_t Data; /* Internal variable to save data to be programmed */
|
||||
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
|
||||
__IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
|
||||
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
|
||||
#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
|
||||
|
||||
#define IS_TYPEERASE(VALUE) (((VALUE) == TYPEERASE_PAGES) || \
|
||||
((VALUE) == TYPEERASE_MASSERASE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
|
||||
|
||||
#define IS_TYPEPROGRAM(VALUE) (((VALUE) == TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == TYPEPROGRAM_DOUBLEWORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
|
||||
#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == WRPSTATE_DISABLE) || \
|
||||
((VALUE) == WRPSTATE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) < (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Data_Address
|
||||
* @{
|
||||
*/
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1))/*||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_BOOT1
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_VDDA_Analog_Monitoring
|
||||
* @{
|
||||
*/
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_SRAM_Parity_Enable
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_SDADC12_VDD_MONITOR
|
||||
* @{
|
||||
*/
|
||||
#define OB_SDADC12_VDD_MONITOR_SET ((uint8_t)0x80) /*!< SDADC12_VDD power supply supervisor set */
|
||||
#define OB_SDADC12_VDD_MONITOR_RESET ((uint8_t)0x00) /*!< SDADC12_VDD power supply supervisor reset */
|
||||
#define IS_OB_SDADC12_VDD_MONITOR(MONITOR) (((MONITOR) == OB_SDADC12_VDD_MONITOR_SET) || ((MONITOR) == OB_SDADC12_VDD_MONITOR_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && ((IT) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Timeout_definition
|
||||
* @brief FLASH Timeout definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__: FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH half cycle access.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH half cycle access.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__: specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGERR : FLASH Programming error flag
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__: specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGERR : FLASH Programming error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32f3xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,805 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH peripheral:
|
||||
* + Extended Initialization/de-initialization functions
|
||||
* + Extended I/O operation functions
|
||||
* + Extended Peripheral Control functions
|
||||
* + Extended Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flash peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the FLASH memory
|
||||
of all STM32F3xxx devices. It includes
|
||||
|
||||
(++) Set/Reset the write protection
|
||||
(++) Program the user Option Bytes
|
||||
(++) Get the Read protection Level
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Erase operations */
|
||||
extern void FLASH_PageErase(uint32_t PageAddress);
|
||||
static void FLASH_MassErase(void);
|
||||
|
||||
/* Option bytes control */
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
|
||||
static uint32_t FLASH_OB_GetWRP(void);
|
||||
static FlagStatus FLASH_OB_GetRDP(void);
|
||||
static uint8_t FLASH_OB_GetUser(void);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
* @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @param[out] PageError: pointer to variable that
|
||||
* contains the configuration information on faulty page in case of error
|
||||
* (0xFFFFFFFF means that all the pages have been correctly erased)
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t address = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
FLASH_MassErase();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If the erase operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
/*Initialization of PageError variable*/
|
||||
*PageError = 0xFFFFFFFF;
|
||||
|
||||
/* Erase by page by page to be done*/
|
||||
for(address = pEraseInit->PageAddress;
|
||||
address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
|
||||
address += FLASH_PAGE_SIZE)
|
||||
{
|
||||
FLASH_PageErase(address);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* In case of error, stop erase procedure and return the faulty address */
|
||||
*PageError = address;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
|
||||
|
||||
if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
|
||||
FLASH_MassErase();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Erase by page to be done*/
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.DataRemaining = pEraseInit->NbPages;
|
||||
pFlash.Address = pEraseInit->PageAddress;
|
||||
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Erases the FLASH option bytes.
|
||||
* @note This functions erases all option bytes except the Read protection (RDP).
|
||||
* The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
|
||||
{
|
||||
uint8_t rdptmp = OB_RDP_LEVEL_0;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
FLASH_OBProgramInitTypeDef optionsbytes;
|
||||
|
||||
/* Get the actual read protection Option Byte value */
|
||||
HAL_FLASHEx_OBGetConfig(&optionsbytes);
|
||||
if(optionsbytes.RDPLevel != RESET)
|
||||
{
|
||||
rdptmp = OB_RDP_LEVEL_1;
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Restore the last read protection Option Byte value */
|
||||
optionsbytes.OptionType = OPTIONBYTE_RDP;
|
||||
optionsbytes.RDPLevel = rdptmp;
|
||||
status = HAL_FLASHEx_OBProgram(&optionsbytes);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
*
|
||||
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
|
||||
|
||||
/* Write protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
|
||||
{
|
||||
assert_param(IS_WRPSTATE(pOBInit->WRPState));
|
||||
if (pOBInit->WRPState == WRPSTATE_ENABLE)
|
||||
{
|
||||
/* Enable of Write protection on the selected page */
|
||||
status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable of Write protection on the selected page */
|
||||
status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
}
|
||||
|
||||
/* Read protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
|
||||
{
|
||||
status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
|
||||
}
|
||||
|
||||
/* USER configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
|
||||
{
|
||||
status = FLASH_OB_UserConfig(pOBInit->USERConfig);
|
||||
}
|
||||
|
||||
/* DATA configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
|
||||
{
|
||||
status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
|
||||
|
||||
/*Get WRP*/
|
||||
pOBInit->WRPPage = FLASH_OB_GetWRP();
|
||||
|
||||
/*Get RDP Level*/
|
||||
pOBInit->RDPLevel = FLASH_OB_GetRDP();
|
||||
|
||||
/*Get USER*/
|
||||
pOBInit->USERConfig = FLASH_OB_GetUser();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Mass erase of FLASH memory
|
||||
* @param None
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_MassErase(void)
|
||||
{
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Proceed to erase all sectors */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection of the desired pages
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if CortexM4
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage: specifies the page(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
uint16_t WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
WriteProtectPage = (uint32_t)(~WriteProtectPage);
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
if(WRP0_Data != 0xFF)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFF))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFF))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFF))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection of the desired pages
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if CortexM4
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage: specifies the page(s) to be write unprotected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
uint16_t WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
if(WRP0_Data != 0xFF)
|
||||
{
|
||||
OB->WRP0 |= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFF))
|
||||
{
|
||||
OB->WRP1 |= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFF))
|
||||
{
|
||||
OB->WRP2 |= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFF))
|
||||
{
|
||||
OB->WRP3 |= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the read protection level.
|
||||
* @param ReadProtectLevel: specifies the read protection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_RDP_LEVEL_0: No protection
|
||||
* @arg OB_RDP_LEVEL_1: Read protection of the memory
|
||||
* @arg OB_RDP_LEVEL_2: Full chip protection
|
||||
*
|
||||
* @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
WRITE_REG(OB->RDP, ReadProtectLevel);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program the FLASH User Option Byte.
|
||||
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
|
||||
assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
|
||||
assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
|
||||
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
|
||||
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
|
||||
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET)));
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F358xx)
|
||||
OB->USER = (UserConfig | 0x88);
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F303xC || STM32F318xx || STM32F334x8 || STM32F358xx */
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
OB->USER = (UserConfig | 0x08);
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs a half word at a specified Option Byte Data address.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_DATA_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enables the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
/* Return the Option Byte Data Program Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH Write Protection Option Bytes value.
|
||||
* @param None
|
||||
* @retval The FLASH Write Protection Option Bytes value
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetWRP(void)
|
||||
{
|
||||
/* Return the FLASH write protection Register value */
|
||||
return (uint32_t)(READ_REG(FLASH->WRPR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Read Protection level.
|
||||
* @param None
|
||||
* @retval FLASH ReadOut Protection Status:
|
||||
* - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
|
||||
* - RESET, when OB_RDP_Level_0 is set
|
||||
*/
|
||||
static FlagStatus FLASH_OB_GetRDP(void)
|
||||
{
|
||||
FlagStatus readstatus = RESET;
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
if ((uint8_t)READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT) != RESET)
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
if ((uint8_t)READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)) != RESET)
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
{
|
||||
readstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
readstatus = RESET;
|
||||
}
|
||||
return readstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH User Option Byte value.
|
||||
* @param None
|
||||
* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return (uint8_t)(READ_REG(FLASH->OBR) >> 8);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of Flash HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_FLASH_EX_H
|
||||
#define __STM32F3xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7CC)
|
||||
#define FLASH_PAGE_SIZE 0x800
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Address
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
|
||||
((ADDRESS) <= 0x0803FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
|
||||
((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
|
||||
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
|
||||
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF))))
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Nb_Pages
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)))
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
|
||||
#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
|
||||
#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
|
||||
#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
|
||||
#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all pages */
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR
|
||||
* @{
|
||||
*/
|
||||
#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00) /*!< SDADC VDD Monitor reset */
|
||||
#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80) /*!< SDADC VDD Monitor set */
|
||||
|
||||
#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
|
||||
((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,536 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief GPIO HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO specific features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(+) Input mode
|
||||
(+) Analog mode
|
||||
(+) Output mode
|
||||
(+) Alternate function mode
|
||||
(+) External interrupt/event lines
|
||||
|
||||
[..]
|
||||
During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
[..]
|
||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
[..]
|
||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
[..]
|
||||
The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral’s alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
[..]
|
||||
All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
[..]
|
||||
The external interrupt/event controller consists of up to 23 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure,
|
||||
the speed is configurable: 2 MHz, 10 MHz and 50 MHz.
|
||||
(++) If alternate mode is selected, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose Px0 and Px1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
#define GET_GPIO_SOURCE(__GPIOx__) \
|
||||
(((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? 0U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? 1U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? 2U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? 3U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1000)))? 4U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1400)))? 5U : 6U)
|
||||
|
||||
#define GPIO_MODE ((uint32_t)0x00000003)
|
||||
#define EXTI_MODE ((uint32_t)0x10000000)
|
||||
#define GPIO_MODE_IT ((uint32_t)0x00010000)
|
||||
#define GPIO_MODE_EVT ((uint32_t)0x00020000)
|
||||
#define RISING_EDGE ((uint32_t)0x00100000)
|
||||
#define FALLING_EDGE ((uint32_t)0x00200000)
|
||||
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
|
||||
|
||||
#define GPIO_NUMBER ((uint32_t)16)
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GPIO_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
|
||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t temp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
for (position = 0; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
||||
|
||||
if (iocurrent == ioposition)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Alternate function parameter */
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3];
|
||||
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
|
||||
GPIOx->AFR[position >> 3] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
temp |= (GPIO_Init->Speed << (position * 2));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2));
|
||||
GPIOx->PUPDR = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2];
|
||||
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
|
||||
temp |= ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
|
||||
SYSCFG->EXTICR[position >> 2] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Configure the port pins */
|
||||
for (position = 0; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (GPIO_Pin) & ioposition;
|
||||
|
||||
if (iocurrent == ioposition)
|
||||
{
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floting Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
|
||||
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
|
||||
SYSCFG->EXTICR[position >> 2] &= ~tmp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GPIO_Group2 IO operation functions
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_BIT_RESET: to clear the port pin
|
||||
* @arg GPIO_BIT_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pin
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request.
|
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks.
|
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_GPIO_H
|
||||
#define __STM32F3xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO_mode_define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO_speed_define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
|
||||
#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
|
||||
#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
|
||||
((SPEED) == GPIO_SPEED_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO_pull_define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
|
||||
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32f3xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_GPIO_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,973 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_GPIO_EX_H
|
||||
#define __STM32F3xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx_Alternate_function_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F302xC) || defined (STM32F303xC)
|
||||
/*------------------------- STM32F302xC/STM32F303xC---------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
|
||||
#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F302xC || STM32F303xC */
|
||||
|
||||
#if defined (STM32F358xx)
|
||||
/*---------------------------------- STM32F358xx -------------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F358xx */
|
||||
|
||||
#if defined (STM32F373xC)
|
||||
/*---------------------------------- STM32F373xC--------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F373xC */
|
||||
|
||||
|
||||
#if defined (STM32F378xx)
|
||||
/*---------------------------------------- STM32F378xx--------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F378xx */
|
||||
|
||||
#if defined (STM32F303x8)
|
||||
/*---------------------------------- STM32F303x8--------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F303x8 */
|
||||
|
||||
#if defined (STM32F334x8) || defined (STM32F328xx)
|
||||
/*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
|
||||
#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined (STM32F301x8) || defined (STM32F318xx)
|
||||
/*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F301x8 || STM32F318xx */
|
||||
|
||||
#if defined (STM32F302x8)
|
||||
/*---------------------------------- STM32F302x8------------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F302x8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,494 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2C_H
|
||||
#define __STM32F3xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
|
||||
HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
|
||||
HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
|
||||
|
||||
}HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
|
||||
HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
|
||||
HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
|
||||
HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
|
||||
HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
|
||||
HAL_I2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */
|
||||
HAL_I2C_ERROR_SIZE = 0x40 /*!< Size Management error */
|
||||
}HAL_I2C_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2C handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
|
||||
|
||||
}I2C_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
|
||||
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_dual_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
|
||||
#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_general_call_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
|
||||
#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_nostretch_mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Memory_Address_Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
|
||||
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
|
||||
#define I2C_GENERATE_STOP I2C_CR2_STOP
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE I2C_CR2_START
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Flag_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset I2C handle state
|
||||
* @param __HANDLE__: I2C handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
|
||||
/** @brief Enables or disables the specified I2C interrupts.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_ERRI: Errors interrupt enable
|
||||
* @arg I2C_IT_TCI: Transfer complete interrupt enable
|
||||
* @arg I2C_IT_STOPI: STOP detection interrupt enable
|
||||
* @arg I2C_IT_NACKI: NACK received interrupt enable
|
||||
* @arg I2C_IT_ADDRI: Address match interrupt enable
|
||||
* @arg I2C_IT_RXI: RX interrupt enable
|
||||
* @arg I2C_IT_TXI: TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_ERRI: Errors interrupt enable
|
||||
* @arg I2C_IT_TCI: Transfer complete interrupt enable
|
||||
* @arg I2C_IT_STOPI: STOP detection interrupt enable
|
||||
* @arg I2C_IT_NACKI: NACK received interrupt enable
|
||||
* @arg I2C_IT_ADDRI: Address match interrupt enable
|
||||
* @arg I2C_IT_RXI: RX interrupt enable
|
||||
* @arg I2C_IT_TXI: TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_FLAG_TXE: Transmit data register empty
|
||||
* @arg I2C_FLAG_TXIS: Transmit interrupt status
|
||||
* @arg I2C_FLAG_RXNE: Receive data register not empty
|
||||
* @arg I2C_FLAG_ADDR: Address matched (slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure received flag
|
||||
* @arg I2C_FLAG_STOPF: STOP detection flag
|
||||
* @arg I2C_FLAG_TC: Transfer complete (master mode)
|
||||
* @arg I2C_FLAG_TCR: Transfer complete reload
|
||||
* @arg I2C_FLAG_BERR: Bus error
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun
|
||||
* @arg I2C_FLAG_PECERR: PEC error in reception
|
||||
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
|
||||
* @arg I2C_FLAG_ALERT: SMBus alert
|
||||
* @arg I2C_FLAG_BUSY: Bus busy
|
||||
* @arg I2C_FLAG_DIR: Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg I2C_FLAG_ADDR: Address matched (slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_STOPF: STOP detection flag
|
||||
* @arg I2C_FLAG_BERR: Bus error
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun
|
||||
* @arg I2C_FLAG_PECERR: PEC error in reception
|
||||
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
|
||||
* @arg I2C_FLAG_ALERT: SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
|
||||
|
||||
#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
|
||||
#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
|
||||
|
||||
#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/* Include I2C HAL Extension module */
|
||||
#include "stm32f3xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Peripheral State functions **************************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief I2C Extension HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C extension peripheral:
|
||||
* + Extension features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral extension features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F3XX
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_AnalogFilter_Config()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_DigitalFilter_Config()
|
||||
(#) Configure the enabling or disabling of I2C Wake Up Mode using the functions :
|
||||
+ HAL_I2CEx_EnableWakeUp()
|
||||
+ HAL_I2CEx_DisableWakeUp()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2CEx_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extension features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures I2C Analog noise filter.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter : new state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures I2C Digital noise filter.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DFN);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables I2C wakeup from stop mode.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables I2C wakeup from stop mode.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2C HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2C_EX_H
|
||||
#define __STM32F3xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2C_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,440 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2S_H
|
||||
#define __STM32F3xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F318xx) || \
|
||||
defined(STM32F358xx) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
|
||||
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
|
||||
This parameter can be a value of @ref I2S_Clock_Source */
|
||||
|
||||
uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
|
||||
This parameter can be a value of @ref I2S_FullDuplex_Mode */
|
||||
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
|
||||
|
||||
}HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_I2S_ERROR_TIMEOUT = 0x01, /*!< Timeout error */
|
||||
HAL_I2S_ERROR_OVR = 0x02, /*!< OVR error */
|
||||
HAL_I2S_ERROR_UDR = 0x04, /*!< UDR error */
|
||||
HAL_I2S_ERROR_DMA = 0x08, /*!< DMA transfer error */
|
||||
HAL_I2S_ERROR_UNKNOW = 0x10 /*!< Unknow Error error */
|
||||
}HAL_I2S_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SPI_TypeDef *Instance; /* I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /* I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /* I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /* I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /* I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
|
||||
|
||||
__IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
|
||||
|
||||
}I2S_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2S_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
|
||||
#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
|
||||
((CLOCK) == I2S_CLOCK_SYSCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
|
||||
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
|
||||
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
|
||||
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
|
||||
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
|
||||
((MODE) == I2S_MODE_SLAVE_RX) || \
|
||||
((MODE) == I2S_MODE_MASTER_TX)|| \
|
||||
((MODE) == I2S_MODE_MASTER_RX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
|
||||
#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
|
||||
#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
|
||||
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
|
||||
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
|
||||
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
|
||||
((STANDARD) == I2S_STANDARD_MSB) || \
|
||||
((STANDARD) == I2S_STANDARD_LSB) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_LONG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
|
||||
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
|
||||
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_24B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_32B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
|
||||
#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
|
||||
#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
|
||||
#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
|
||||
#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
|
||||
#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
|
||||
#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
|
||||
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
|
||||
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
|
||||
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
|
||||
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_FullDuplex_Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
|
||||
#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
|
||||
|
||||
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
|
||||
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
|
||||
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
|
||||
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
|
||||
((CPOL) == I2S_CPOL_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupt_configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flag_definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__: I2S handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
|
||||
|
||||
/** @brief Enable or disable the specified I2S interrupts.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
|
||||
(__HANDLE__)->Instance->SR;}while(0)
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
|
||||
|
||||
/* Include I2S HAL Extension module */
|
||||
#include "stm32f3xx_hal_i2s_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F301x8) || */
|
||||
/* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) || */
|
||||
/* defined(STM32F318xx) || */
|
||||
/* defined(STM32F358xx) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2S_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,171 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2S HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2S_EX_H
|
||||
#define __STM32F3xx_HAL_I2S_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F318xx) || \
|
||||
defined(STM32F358xx) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2SEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
|
||||
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
|
||||
|
||||
/** @brief Enable or disable the specified I2SExt peripheral.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
|
||||
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
|
||||
|
||||
/** @brief Enable or disable the specified I2SExt interrupts.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2SExt flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2SExt OVR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
|
||||
(I2SxEXT((__HANDLE__)->Instance)->SR;}while(0)
|
||||
/** @brief Clears the I2SExt UDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
|
||||
#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
|
||||
/* Extended features functions ************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
|
||||
|
||||
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F301x8) || */
|
||||
/* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) || */
|
||||
/* defined(STM32F318xx) || */
|
||||
/* defined(STM32F358xx) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2S_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,590 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_IRDA_H
|
||||
#define __STM32F3xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
||||
|
||||
uint16_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
}IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
|
||||
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
|
||||
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
|
||||
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
|
||||
}HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
|
||||
HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
|
||||
HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
|
||||
HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
|
||||
HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
|
||||
}HAL_IRDA_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
|
||||
}IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /* USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /* IRDA communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* IRDA Tx Transfer size */
|
||||
|
||||
uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* IRDA Rx Transfer size */
|
||||
|
||||
uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /* USART RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
HAL_IRDA_StateTypeDef State; /* IRDA communication state */
|
||||
|
||||
HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
|
||||
|
||||
}IRDA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA Configuration enumeration values definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_BAUDRATE = 0x00,
|
||||
IRDA_PARITY = 0x01,
|
||||
IRDA_WORDLENGTH = 0x02,
|
||||
IRDA_MODE = 0x03,
|
||||
IRDA_PRESCALER = 0x04,
|
||||
IRDA_POWERMODE = 0x05
|
||||
}IRDA_ControlTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE ((uint16_t)0x0000)
|
||||
#define IRDA_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
|
||||
#define IRDA_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
|
||||
((PARITY) == IRDA_PARITY_EVEN) || \
|
||||
((PARITY) == IRDA_PARITY_ODD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX ((uint16_t)USART_CR1_RE)
|
||||
#define IRDA_MODE_TX ((uint16_t)USART_CR1_TE)
|
||||
#define IRDA_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
#define IS_IRDA_TX_RX_MODE(MODE) ((((MODE) & (~((uint16_t)(IRDA_MODE_TX_RX)))) == (uint16_t)0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL ((uint16_t)0x0000)
|
||||
#define IRDA_POWERMODE_LOWPOWER ((uint16_t)USART_CR3_IRLP)
|
||||
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((MODE) == IRDA_POWERMODE_NORMAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE ((uint16_t)0x0000)
|
||||
#define IRDA_STATE_ENABLE ((uint16_t)USART_CR1_UE)
|
||||
#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \
|
||||
((STATE) == IRDA_STATE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE ((uint16_t)0x0000)
|
||||
#define IRDA_MODE_ENABLE ((uint16_t)USART_CR3_IREN)
|
||||
#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \
|
||||
((STATE) == IRDA_MODE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint16_t)0x00000000)
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint16_t)USART_CR3_ONEBIT)
|
||||
#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \
|
||||
((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE ((uint16_t)0x00000000)
|
||||
#define IRDA_DMA_TX_ENABLE ((uint16_t)USART_CR3_DMAT)
|
||||
#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \
|
||||
((DMATX) == IRDA_DMA_TX_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE ((uint16_t)0x0000)
|
||||
#define IRDA_DMA_RX_ENABLE ((uint16_t)USART_CR3_DMAR)
|
||||
#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \
|
||||
((DMARX) == IRDA_DMA_RX_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK ((uint32_t)0x00400000)
|
||||
#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)
|
||||
#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)
|
||||
#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)
|
||||
#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)
|
||||
#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
|
||||
#define IRDA_FLAG_TC ((uint32_t)0x00000040)
|
||||
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
|
||||
#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
|
||||
#define IRDA_FLAG_NE ((uint32_t)0x00000004)
|
||||
#define IRDA_FLAG_FE ((uint32_t)0x00000002)
|
||||
#define IRDA_FLAG_PE ((uint32_t)0x00000001)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE ((uint16_t)0x0028)
|
||||
#define IRDA_IT_TXE ((uint16_t)0x0727)
|
||||
#define IRDA_IT_TC ((uint16_t)0x0626)
|
||||
#define IRDA_IT_RXNE ((uint16_t)0x0525)
|
||||
#define IRDA_IT_IDLE ((uint16_t)0x0424)
|
||||
|
||||
|
||||
|
||||
/** Elements values convention: 000000000XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
*/
|
||||
#define IRDA_IT_ERR ((uint16_t)0x0060)
|
||||
|
||||
/** Elements values convention: 0000ZZZZ00000000b
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
*/
|
||||
#define IRDA_IT_ORE ((uint16_t)0x0300)
|
||||
#define IRDA_IT_NE ((uint16_t)0x0200)
|
||||
#define IRDA_IT_FE ((uint16_t)0x0100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
||||
#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((PARAM) == IRDA_SENDBREAK_REQUEST) || \
|
||||
((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
|
||||
((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK ((uint16_t)0x001F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state
|
||||
* @param __HANDLE__: IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
|
||||
|
||||
/** @brief Checks whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_FLAG_REACK: Receive enable ackowledge flag
|
||||
* @arg IRDA_FLAG_TEACK: Transmit enable ackowledge flag
|
||||
* @arg IRDA_FLAG_BUSY: Busy flag
|
||||
* @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
|
||||
* @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
|
||||
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg IRDA_FLAG_ORE: OverRun Error flag
|
||||
* @arg IRDA_FLAG_NE: Noise Error flag
|
||||
* @arg IRDA_FLAG_FE: Framing Error flag
|
||||
* @arg IRDA_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enables the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disables the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
|
||||
/** @brief Checks whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ORE: OverRun Error interrupt
|
||||
* @arg IRDA_IT_NE: Noise Error interrupt
|
||||
* @arg IRDA_IT_FE: Framing Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
|
||||
|
||||
/** @brief Checks whether the specified IRDA interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ORE: OverRun Error interrupt
|
||||
* @arg IRDA_IT_NE: Noise Error interrupt
|
||||
* @arg IRDA_IT_FE: Framing Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
|
||||
|
||||
|
||||
/** @brief Clears the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
|
||||
* @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
|
||||
* @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
|
||||
* @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
|
||||
* @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __REQ__: specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
|
||||
* @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
|
||||
* @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
|
||||
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0
|
||||
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extension module */
|
||||
#include "stm32f3xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_IRDA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,410 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of IRDA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_IRDA_EX_H
|
||||
#define __STM32F3xx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDAEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F301x8) || defined (STM32F302x8) || defined (STM32F334x8) \
|
||||
|| defined (STM32F318xx)
|
||||
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
#else
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reports the IRDA clock source.
|
||||
* @param __HANDLE__: specifies the IRDA Handle
|
||||
* @param __CLOCKSOURCE__ : output variable
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F303xE) \
|
||||
|| defined(STM32F318xC) || defined(STM32F358xx)
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F334x8) || defined(STM32F303x8) || defined(STM32F328xx)
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#endif /* defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F318xC) || defined(STM32F358xx) */
|
||||
|
||||
|
||||
/** @brief Computes the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__: specifies the IRDA Handle
|
||||
* @retval none
|
||||
*/
|
||||
#if defined (STM32F301x8) || defined (STM32F302x8) || defined (STM32F334x8) \
|
||||
|| defined (STM32F318xx)
|
||||
#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#endif /* defined (STM32F301x8) || defined (STM32F302x8) || defined (STM32F334x8)
|
||||
|| defined (STM32F318xx) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_IRDA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,407 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief IWDG HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and Configuration functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
================================================================================
|
||||
##### IWDG specific features #####
|
||||
================================================================================
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
|
||||
thus stays active even if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
(LSI cannot be disabled too), and the counter starts counting down from
|
||||
the reset value of 0xFFF. When it reaches the end of count value (0x000)
|
||||
a system reset is generated.
|
||||
|
||||
(+) The IWDG counter should be refreshed at regular intervals, otherwise the
|
||||
watchdog generates an MCU reset when the counter reaches 0.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
|
||||
(+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM16 CH1 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
For more information, please refer to the STM32F3xx Reference manual.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) if Window option is disabled
|
||||
(+) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable write access to IWDG_PR, IWDG_RLR.
|
||||
(++) Configure the IWDG prescaler, counter reload value.
|
||||
This reload value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
(+) Use IWDG using HAL_IWDG_Start() function to :
|
||||
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
|
||||
(++) Start the IWDG, when the IWDG is used in software mode (no need
|
||||
to enable the LSI, it will be enabled by hardware).
|
||||
(+) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
(#) if Window option is enabled:
|
||||
(+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
|
||||
(+) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
(++) Configure the IWDG prescaler, reload value and window value.
|
||||
(+) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver.
|
||||
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
|
||||
(+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
(+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 1000
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group1 Initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters
|
||||
in the IWDG_InitTypeDef and create the associated handle
|
||||
(+) Manage Window option
|
||||
(+) Initialize the IWDG MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the IWDG according to the specified
|
||||
* parameters in the IWDG_InitTypeDef and creates the associated handle.
|
||||
* @param hiwdg: IWDG handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Check the IWDG handle allocation */
|
||||
if(hiwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
|
||||
|
||||
/* Check pending flag, if previous update not done, return error */
|
||||
if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) &&
|
||||
(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) &&
|
||||
(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hiwdg->State == HAL_IWDG_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_IWDG_MspInit(hiwdg);
|
||||
}
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
|
||||
/* by writing 0x5555 in KR */
|
||||
__HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
|
||||
MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
|
||||
MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
|
||||
|
||||
/* check if window option is enabled */
|
||||
if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
|
||||
{
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while((uint32_t)(hiwdg->Instance->SR) != RESET)
|
||||
{
|
||||
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write to IWDG WINR the IWDG_Window value to compare with */
|
||||
MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window);
|
||||
|
||||
}
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the IWDG MSP.
|
||||
* @param hiwdg: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_IWDG_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start the IWDG.
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the IWDG.
|
||||
* @param hiwdg: IWDG handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
/* Reload IWDG counter with value defined in the RLR register */
|
||||
if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
|
||||
{
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
}
|
||||
|
||||
/* Enable the IWDG peripheral */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until PVU, RVU, WVU flag are RESET */
|
||||
while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) &&
|
||||
(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) &&
|
||||
(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )
|
||||
{
|
||||
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Refreshes the IWDG.
|
||||
* @param hiwdg: IWDG handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until RVU flag is RESET */
|
||||
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
|
||||
{
|
||||
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the IWDG state.
|
||||
* @param hiwdg: IWDG handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
return hiwdg->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_IWDG_H
|
||||
#define __STM32F3xx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief IWDG HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
|
||||
HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
|
||||
HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
|
||||
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
|
||||
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
|
||||
|
||||
}HAL_IWDG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< IWDG Locking object */
|
||||
|
||||
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
|
||||
|
||||
}IWDG_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Registers_BitMask
|
||||
* @brief IWDG registers bit mask
|
||||
* @{
|
||||
*/
|
||||
/* --- KR Register ---*/
|
||||
/* KR register bit mask */
|
||||
#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
|
||||
#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
|
||||
#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
|
||||
#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
|
||||
|
||||
#define IS_IWDG_KR(KR) (((KR) == KR_KEY_RELOAD) || \
|
||||
((KR) == KR_KEY_ENABLE))|| \
|
||||
((KR) == KR_KEY_EWA)) || \
|
||||
((KR) == KR_KEY_DWA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag_definition
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update Flag */
|
||||
#define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update Flag */
|
||||
#define IWDG_FLAG_WVU ((uint32_t)0x0004) /*!< Watchdog counter window value update Flag */
|
||||
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
|
||||
((FLAG) == IWDG_FLAG_RVU) || \
|
||||
((FLAG) == IWDG_FLAG_WVU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 ((uint8_t)0x01) /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 ((uint8_t)0x02) /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 ((uint8_t)0x03) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 ((uint8_t)0x04) /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 ((uint8_t)0x05) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 ((uint8_t)0x06) /*!< IWDG prescaler set to 256 */
|
||||
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
|
||||
((PRESCALER) == IWDG_PRESCALER_8) || \
|
||||
((PRESCALER) == IWDG_PRESCALER_16) || \
|
||||
((PRESCALER) == IWDG_PRESCALER_32) || \
|
||||
((PRESCALER) == IWDG_PRESCALER_64) || \
|
||||
((PRESCALER) == IWDG_PRESCALER_128)|| \
|
||||
((PRESCALER) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Reload_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_CounterWindow_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(VALUE) ((VALUE) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup IWDG_Window option disable
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE 0xFFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IWDG handle state
|
||||
* @param __HANDLE__: IWDG handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enables the IWDG peripheral.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) ((__HANDLE__)->Instance->KR |= KR_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_EWA)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_DWA)
|
||||
|
||||
/**
|
||||
* @brief Gets the selected IWDG's flag status.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
|
||||
* @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
|
||||
* @arg IWDG_FLAG_WVU: Watchdog counter window value flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
|
||||
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,888 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief OPAMP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
|
||||
* peripheral:
|
||||
* + OPAMP Configuration
|
||||
* + OPAMP calibration
|
||||
*
|
||||
* Thanks to
|
||||
* + Initialization/de-initialization functions
|
||||
* + I/O operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### OPAMP Peripheral Features #####
|
||||
================================================================================
|
||||
|
||||
[..] The device integrates up to 4 operational amplifiers OPAMP1, OPAMP2,
|
||||
OPAMP3 and OPAMP4:
|
||||
|
||||
(#) The OPAMP(s) provides several exclusive running modes.
|
||||
(+) Standalone mode
|
||||
(+) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
|
||||
(+) Follower mode
|
||||
|
||||
(#) The OPAMP(s) provide(s) calibration capabilities.
|
||||
(+) Calibration aims at correcting some offset for running mode.
|
||||
(+) The OPAMP uses either factory calibration settings OR user defined
|
||||
calibration (trimming) settings (i.e. trimming mode).
|
||||
(+) The user defined settings can be figured out using self calibration
|
||||
handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrate2opamp
|
||||
or HAL_OPAMPEx_SelfCalibrate4opamp
|
||||
(+) HAL_OPAMP_SelfCalibrate:
|
||||
(++) Runs automatically the calibration in 2 steps.
|
||||
(90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
|
||||
(As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
|
||||
appropriate and enough in most cases).
|
||||
(++) Enables the user trimming mode
|
||||
(++) Updates the init structure with trimming values with fresh calibration
|
||||
results.
|
||||
The user may store the calibration results for larger
|
||||
(ex monitoring the trimming as a function of temperature
|
||||
for instance)
|
||||
(++) for STM32F3 devices having 2 or 4 OPAMPs
|
||||
HAL_OPAMPEx_SelfCalibrate2opamp, HAL_OPAMPEx_SelfCalibrate4opamp
|
||||
runs calibration of 2 or 4 OPAMPs in parallel.
|
||||
|
||||
(#) For any running mode, an additional Timer-controlled Mux (multiplexer)
|
||||
mode can be set on top.
|
||||
(+) Timer-controlled Mux mode allows Automatic switching between inverting
|
||||
and non-inverting input.
|
||||
(+) Hence on top of defaults (primary) inverting and non-inverting inputs,
|
||||
the user shall select secondary inverting and non inverting inputs.
|
||||
(+) TIM1 CC6 provides the alternate switching tempo between defaults
|
||||
(primary) and secondary inputs.
|
||||
|
||||
(#) Running mode: Standalone mode
|
||||
(+) Gain is set externally (gain depends on external loads).
|
||||
(+) Follower mode also possible externally by connecting the inverting input to
|
||||
the output.
|
||||
|
||||
(#) Running mode: Follower mode
|
||||
(+) No Inverting Input is connected.
|
||||
|
||||
(#) Running mode: Programmable Gain Amplifier (PGA) mode
|
||||
(Resistor feedback output)
|
||||
(+) The OPAMP(s) output(s) can be internally connected to resistor feedback
|
||||
output.
|
||||
(+) OPAMP gain is either 2, 4, 8 or 16.
|
||||
|
||||
(#) The OPAMPs non inverting input (both default and secondary) can be
|
||||
selected among the list shown by table below.
|
||||
|
||||
(#) The OPAMPs non inverting input (both default and secondary) can be
|
||||
selected among the list shown by table below.
|
||||
|
||||
[..] Table 1. OPAMPs inverting/non-inverting inputs for the STM32F3 devices:
|
||||
|
||||
+--------------------------------------------------------------+
|
||||
| | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
|
||||
|-----------------|--------|--------|--------|--------|--------|
|
||||
| | No conn| X | X | X | X |
|
||||
| Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 |
|
||||
| (1) | VM1 | PA3 | PA5 | PB2 | PD8 |
|
||||
|-----------------|--------|--------|--------|--------|--------|
|
||||
| | VP0 | PA1 | PA7 | PB0 | PB13 |
|
||||
| Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 |
|
||||
| Input | VP2 | PA3 | PB0 | PA1 | PA4 |
|
||||
| | VP3 | PA5 | PB14 | PA5 | PB11 |
|
||||
+--------------------------------------------------------------+
|
||||
(1): NA in follower mode.
|
||||
|
||||
[..] Table 2. OPAMPs outputs for the STM32F3 devices:
|
||||
|
||||
+--------------------------------------------------------------+
|
||||
| | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
|
||||
|-----------------|--------|--------|--------|--------|--------|
|
||||
| Output | | PA2 | PA6 | PB1 | PB12 |
|
||||
|-----------------|--------|--------|--------|--------|--------|
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
|
||||
*** Calibration ***
|
||||
============================================
|
||||
To run the opamp calibration self calibration:
|
||||
|
||||
(#) Start calibration using HAL_OPAMP_SelfCalibrate.
|
||||
Store the calibration results.
|
||||
|
||||
*** Running mode ***
|
||||
============================================
|
||||
|
||||
To use the opamp, perform the following steps:
|
||||
|
||||
(#) Fill in the HAL_COMP_MspInit() to
|
||||
(+) Configure the opamp input AND output in analog mode using
|
||||
HAL_GPIO_Init() to map the opamp output to the GPIO pin.
|
||||
|
||||
(#) Configure the opamp using HAL_OPAMP_Init() function:
|
||||
(+) Select the mode
|
||||
(+) Select the inverting input
|
||||
(+) Select the non-inverting input
|
||||
(+) Select if the Timer controlled Mux mode is enabled/disabled
|
||||
(+) If the Timer controlled Mux mode is enabled, select the secondary inverting input
|
||||
(+) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
|
||||
(+) If PGA mode is enabled, Select if inverting input is connected.
|
||||
(+) Select either factory or user defined trimming mode.
|
||||
(+) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
|
||||
(typ. settings returned by HAL_OPAMP_SelfCalibrate function).
|
||||
|
||||
(#) Enable the opamp using HAL_OPAMP_Start() function.
|
||||
|
||||
(#) Disable the opamp using HAL_OPAMP_Stop() function.
|
||||
|
||||
(#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. From then The configuration
|
||||
can only be modified after HW reset.
|
||||
|
||||
*** Running mode: change of configuration while OPAMP ON ***
|
||||
============================================
|
||||
To Re-configure OPAMP when OPAMP is ON (change on the fly)
|
||||
(#) If needed, Fill in the HAL_OPAMP_MspInit()
|
||||
(+) This is the case for instance if youu wish to use new OPAMP I/O
|
||||
|
||||
(#) Configure the opamp using HAL_OPAMP_Init() function:
|
||||
(+) As in configure case, selects first the parameters you wish to modify.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP
|
||||
* @brief OPAMP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx) || defined (STM32F302xC) || \
|
||||
defined (STM32F303x8) || defined (STM32F328xx) || defined (STM32F302x8) || \
|
||||
defined (STM32F301x8) || defined (STM32F318xx) || defined (STM32F334x8)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* CSR register reset value */
|
||||
#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_OPAMP_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the OPAMP according to the specified
|
||||
* parameters in the OPAMP_InitTypeDef and create the associated handle.
|
||||
* @note If the selected opamp is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
|
||||
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the OPAMP handle allocation and lock status */
|
||||
/* Init not allowed if calibration is ongoing */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
/* Set OPAMP parameters */
|
||||
assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
|
||||
assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
|
||||
if (((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE) || ((hopamp->Init.Mode) == OPAMP_PGA_MODE))
|
||||
{
|
||||
assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
|
||||
}
|
||||
|
||||
assert_param(IS_OPAMP_TIMERCONTROLLED_MUXMODE(hopamp->Init.TimerControlledMuxmode));
|
||||
|
||||
if ((hopamp->Init.TimerControlledMuxmode) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE)
|
||||
{
|
||||
assert_param(IS_OPAMP_SEC_NONINVERTINGINPUT(hopamp->Init.NonInvertingInputSecondary));
|
||||
if (((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE) || ((hopamp->Init.Mode) == OPAMP_PGA_MODE))
|
||||
{
|
||||
assert_param(IS_OPAMP_SEC_INVERTINGINPUT(hopamp->Init.InvertingInputSecondary));
|
||||
}
|
||||
}
|
||||
|
||||
if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
|
||||
{
|
||||
assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
|
||||
assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
|
||||
}
|
||||
|
||||
assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
|
||||
if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
|
||||
{
|
||||
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
|
||||
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
|
||||
}
|
||||
|
||||
/* Init SYSCFG and the low level hardware to access opamp */
|
||||
__SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Call MSP init function */
|
||||
HAL_OPAMP_MspInit(hopamp);
|
||||
|
||||
/* Set OPAMP parameters */
|
||||
/* Set bits according to hopamp->hopamp->Init.Mode value */
|
||||
/* Set bits according to hopamp->hopamp->Init.InvertingInput value */
|
||||
/* Set bits according to hopamp->hopamp->Init.NonInvertingInput value */
|
||||
/* Set bits according to hopamp->hopamp->Init.TimerControlledMuxmode value */
|
||||
/* Set bits according to hopamp->hopamp->Init.InvertingInputSecondary value */
|
||||
/* Set bits according to hopamp->hopamp->Init.NonInvertingInputSecondary value */
|
||||
/* Set bits according to hopamp->hopamp->Init.PgaConnect value */
|
||||
/* Set bits according to hopamp->hopamp->Init.PgaGain value */
|
||||
/* Set bits according to hopamp->hopamp->Init.UserTrimming value */
|
||||
/* Set bits according to hopamp->hopamp->Init.TrimmingValueP value */
|
||||
/* Set bits according to hopamp->hopamp->Init.TrimmingValueN value */
|
||||
|
||||
|
||||
/* check if OPAMP_PGA_MODE & in Follower mode */
|
||||
/* - InvertingInput */
|
||||
/* - InvertingInputSecondary */
|
||||
/* are Not Applicable */
|
||||
|
||||
if ((hopamp->Init.Mode == OPAMP_PGA_MODE) || (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE))
|
||||
{
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
|
||||
hopamp->Init.Mode | \
|
||||
hopamp->Init.NonInvertingInput | \
|
||||
hopamp->Init.TimerControlledMuxmode | \
|
||||
hopamp->Init.NonInvertingInputSecondary | \
|
||||
hopamp->Init.PgaConnect | \
|
||||
hopamp->Init.PgaGain | \
|
||||
hopamp->Init.UserTrimming | \
|
||||
(hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
|
||||
(hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
|
||||
hopamp->Init.Mode | \
|
||||
hopamp->Init.InvertingInput | \
|
||||
hopamp->Init.NonInvertingInput | \
|
||||
hopamp->Init.TimerControlledMuxmode | \
|
||||
hopamp->Init.InvertingInputSecondary | \
|
||||
hopamp->Init.NonInvertingInputSecondary | \
|
||||
hopamp->Init.PgaConnect | \
|
||||
hopamp->Init.PgaGain | \
|
||||
hopamp->Init.UserTrimming | \
|
||||
(hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
|
||||
(hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
|
||||
}
|
||||
/* Update the OPAMP state*/
|
||||
if (hopamp->State == HAL_OPAMP_STATE_RESET)
|
||||
{
|
||||
/* From RESET state to READY State */
|
||||
hopamp->State = HAL_OPAMP_STATE_READY;
|
||||
}
|
||||
/* else: remain in READY or BUSY state (no update) */
|
||||
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the OPAMP peripheral
|
||||
* @note Deinitialization can't be performed if the OPAMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the OPAMP handle allocation */
|
||||
/* Check if OPAMP locked */
|
||||
/* DeInit not allowed if calibration is ongoing */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
/* Set OPAMP_CSR register to reset value */
|
||||
WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
|
||||
|
||||
/* DeInit the low level hardware: GPIO, CLOCK and NVIC */
|
||||
HAL_OPAMP_MspDeInit(hopamp);
|
||||
|
||||
/* Update the OPAMP state*/
|
||||
hopamp->State = HAL_OPAMP_STATE_RESET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the OPAMP MSP.
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_OPAMP_MspInit could be implemented in the user file
|
||||
*/
|
||||
|
||||
/* Example */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes OPAMP MSP.
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_OPAMP_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_OPAMP_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the OPAMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the opamp
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the OPAMP handle allocation */
|
||||
/* Check if OPAMP locked */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
|
||||
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
if(hopamp->State == HAL_OPAMP_STATE_READY)
|
||||
{
|
||||
/* Enable the selected opamp */
|
||||
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Update the OPAMP state*/
|
||||
/* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
|
||||
hopamp->State = HAL_OPAMP_STATE_BUSY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the opamp
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the OPAMP handle allocation */
|
||||
/* Check if OPAMP locked */
|
||||
/* Check if OPAMP calibration ongoing */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
if(hopamp->State == HAL_OPAMP_STATE_BUSY)
|
||||
{
|
||||
/* Disable the selected opamp */
|
||||
CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Update the OPAMP state*/
|
||||
/* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
|
||||
hopamp->State = HAL_OPAMP_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Run the self calibration of one OPAMP
|
||||
* @param hopamp handle
|
||||
* @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
|
||||
* @retval HAL status
|
||||
* @note Calibration runs about 25 ms.
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
uint32_t trimmingvaluen = 0;
|
||||
uint32_t trimmingvaluep = 0;
|
||||
uint32_t delta;
|
||||
|
||||
/* Check the OPAMP handle allocation */
|
||||
/* Check if OPAMP locked */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
/* Check if OPAMP in calibration mode and calibration not yet enable */
|
||||
if(hopamp->State == HAL_OPAMP_STATE_READY)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
/* Set Calibration mode */
|
||||
/* Non-inverting input connected to calibration reference voltage. */
|
||||
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* user trimming values are used for offset calibration */
|
||||
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
|
||||
/* Enable calibration */
|
||||
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
|
||||
|
||||
/* 1st calibration - N */
|
||||
/* Select 90% VREF */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
|
||||
/* Enable the selected opamp */
|
||||
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Init trimming counter */
|
||||
/* Medium value */
|
||||
trimmingvaluen = 16;
|
||||
delta = 8;
|
||||
|
||||
while (delta != 0)
|
||||
{
|
||||
/* Set candidate trimming */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen -= delta;
|
||||
}
|
||||
|
||||
delta >>= 1;
|
||||
}
|
||||
|
||||
/* Still need to check if righ calibration is current value or un step below */
|
||||
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
/* 2nd calibration - P */
|
||||
/* Select 10% VREF */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
|
||||
/* Init trimming counter */
|
||||
/* Medium value */
|
||||
trimmingvaluep = 16;
|
||||
delta = 8;
|
||||
|
||||
while (delta != 0)
|
||||
{
|
||||
/* Set candidate trimming */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep -= delta;
|
||||
}
|
||||
|
||||
delta >>= 1;
|
||||
}
|
||||
|
||||
/* Still need to check if righ calibration is current value or un step below */
|
||||
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
|
||||
/* Set candidate trimming */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
/* Disable calibration */
|
||||
CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
|
||||
|
||||
/* Disable the OPAMP */
|
||||
CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Set normale operating mode */
|
||||
/* Non-inverting input connected to calibration reference voltage. */
|
||||
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* Set normale operating mode */
|
||||
/* Non-inverting input connected to calibration reference voltage. */
|
||||
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* Self calibration is successful */
|
||||
/* Store calibration(user timming) results in init structure. */
|
||||
|
||||
/* Write calibration result N */
|
||||
hopamp->Init.TrimmingValueN = trimmingvaluen;
|
||||
|
||||
/* Write calibration result P */
|
||||
hopamp->Init.TrimmingValueP = trimmingvaluep;
|
||||
|
||||
/* Select user timming mode */
|
||||
/* And updated with calibrated settings */
|
||||
hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* OPAMP can not be calibrated from this mode */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_OPAMP_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the OPAMP data
|
||||
transfers.
|
||||
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected opamp configuration.
|
||||
* @param hopamp: OPAMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the OPAMP handle allocation */
|
||||
/* Check if OPAMP locked */
|
||||
/* OPAMP can be locked when enabled and running in normal mode */
|
||||
/* It is meaningless otherwise */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_READY) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
|
||||
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
/* Lock OPAMP */
|
||||
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_LOCK);
|
||||
|
||||
/* OPAMP state changed to locked */
|
||||
hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_OPAMP_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the OPAMP state
|
||||
* @param hopamp : OPAMP handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
|
||||
{
|
||||
/* Check the OPAMP handle allocation */
|
||||
if(hopamp == NULL)
|
||||
{
|
||||
return HAL_OPAMP_STATE_RESET;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
|
||||
return hopamp->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the OPAMP factory trimming value
|
||||
* @param hopamp : OPAMP handle
|
||||
* @param trimmingoffset : Trimming offset (P or N)
|
||||
* @retval Trimming value (P or N): range: 0->31
|
||||
* or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
|
||||
*/
|
||||
|
||||
OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
|
||||
{
|
||||
uint32_t oldusertrimming = 0;
|
||||
OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0, oldtrimmingvaluen = 0, trimmingvalue = 0;
|
||||
|
||||
/* Check the OPAMP handle allocation */
|
||||
/* Value can be retrieved in HAL_OPAMP_STATE_READY state */
|
||||
if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_BUSY) \
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
|
||||
|| (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
|
||||
{
|
||||
return OPAMP_FACTORYTRIMMING_DUMMY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
|
||||
assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
|
||||
|
||||
/* Check the trimming mode */
|
||||
if ((READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)) != RESET)
|
||||
{
|
||||
/* User trimming is used */
|
||||
oldusertrimming = OPAMP_TRIMMING_USER;
|
||||
/* Store the TrimmingValueP & TrimmingValueN */
|
||||
oldtrimmingvaluep = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
|
||||
oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING;
|
||||
}
|
||||
|
||||
/* Set factory timming mode */
|
||||
CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
|
||||
/* Get factory trimming */
|
||||
if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
|
||||
{
|
||||
/* Return TrimOffsetP */
|
||||
trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return TrimOffsetN */
|
||||
trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
/* Restore user trimming configuration if it was formerly set */
|
||||
/* Check if user trimming was used */
|
||||
if (oldusertrimming == OPAMP_TRIMMING_USER)
|
||||
{
|
||||
/* Restore user trimming */
|
||||
SET_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM);
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, oldtrimmingvaluep<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, oldtrimmingvaluen<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
}
|
||||
return trimmingvalue;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F303xC STM32F358xx STM32F302xC STM32F303x8 STM32F328xx
|
||||
STM32F302x8 STM32F301x8 STM32F318xx STM32F334x8 */
|
||||
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,450 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of OPAMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_OPAMP_H
|
||||
#define __STM32F3xx_HAL_OPAMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx) || defined (STM32F302xC) || \
|
||||
defined (STM32F303x8) || defined (STM32F328xx) || defined (STM32F302x8) || \
|
||||
defined (STM32F301x8) || defined (STM32F318xx) || defined (STM32F334x8)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief OPAMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the OPAMP mode
|
||||
This parameter must be a value of @ref OPAMP_Mode
|
||||
mode is either Standalone, - Follower or PGA */
|
||||
|
||||
uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
|
||||
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
|
||||
This parameter must be a value of @ref OPAMP_InvertingInput
|
||||
InvertingInput is either VM0 or VM1
|
||||
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
|
||||
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
|
||||
This parameter is Not Applicable */
|
||||
|
||||
uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
|
||||
This parameter must be a value of @ref OPAMP_NonInvertingInput
|
||||
NonInvertingInput is either VP0, VP1, VP3 or VP4 */
|
||||
|
||||
uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
|
||||
This parameter must be a value of @ref OPAMP_TimerControlledMuxmode */
|
||||
|
||||
uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
|
||||
TimerControlledMuxmode is enabled
|
||||
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
|
||||
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
|
||||
This parameter must be a value of @ref OPAMP_InvertingInputSecondary
|
||||
InvertingInputSecondary is either VM0 or VM1
|
||||
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
|
||||
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
|
||||
This parameter is Not Applicable */
|
||||
|
||||
uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
|
||||
TimerControlledMuxmode is enabled
|
||||
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
|
||||
This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
|
||||
NonInvertingInput is either VP0, VP1, VP3 or VP3 */
|
||||
|
||||
uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
|
||||
i.e. when mode is OPAMP_PGA_MODE
|
||||
This parameter must be a value of @ref OPAMP_PgaConnect
|
||||
Either: not connected, connected to VM0, connected to VM1
|
||||
(VM0 or VM1 are typically used for external filtering) */
|
||||
|
||||
uint32_t PgaGain; /*!< Specifies the gain in PGA mode
|
||||
i.e. when mode is OPAMP_PGA_MODE.
|
||||
This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */
|
||||
|
||||
uint32_t UserTrimming; /*!< Specifies the trimming mode
|
||||
This parameter must be a value of @ref OPAMP_UserTrimming
|
||||
UserTrimming is either factory or user timming */
|
||||
|
||||
uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
|
||||
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
|
||||
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
}OPAMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPMAP is not yet Initialized */
|
||||
|
||||
HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */
|
||||
HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
|
||||
|
||||
HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
|
||||
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005, /*!< OPAMP is locked
|
||||
only system reset allows reconfiguring the opamp. */
|
||||
|
||||
}HAL_OPAMP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief PPP Handle Structure definition to @brief OPAMP Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
|
||||
OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
|
||||
HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
|
||||
|
||||
} OPAMP_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief OPAMP_TrimmingValueTypeDef @brief definition
|
||||
*/
|
||||
|
||||
typedef uint32_t OPAMP_TrimmingValueTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup OPAMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* CSR register Mask
|
||||
*/
|
||||
/* Used for Init phase */
|
||||
#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
|
||||
| OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
|
||||
| OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
|
||||
| OPAMP_CSR_VPSEL | OPAMP_CSR_FORCEVP)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Mode
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */
|
||||
#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
|
||||
#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
|
||||
|
||||
|
||||
#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
|
||||
((INPUT) == OPAMP_PGA_MODE) || \
|
||||
((INPUT) == OPAMP_FOLLOWER_MODE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NONINVERTINGINPUT_VP1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_CSR_VPSEL_0 /*!< vp3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
|
||||
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_VP0) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_VP1) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_VP2) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_VP3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IOPAMP_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< inverting input connected to VM0 */
|
||||
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
|
||||
|
||||
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == IOPAMP_INVERTINGINPUT_VM0) || \
|
||||
((INPUT) == IOPAMP_INVERTINGINPUT_VM1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_TimerControlledMuxmode
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE ((uint32_t)0x00000000) /*!< Timer controlled Mux mode disabled */
|
||||
#define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */
|
||||
|
||||
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
|
||||
((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_NonInvertingInputSecondary
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
|
||||
#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP0) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP1) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP2) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_InvertingInputSecondary
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_SEC_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
|
||||
connected to OPAMPx inverting input */
|
||||
#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
|
||||
connected to OPAMPx inverting input */
|
||||
|
||||
#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_VM0) || \
|
||||
((INPUT) == OPAMP_SEC_INVERTINGINPUT_VM1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PgaConnect
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_PGACONNECT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the non inverting input is not connected */
|
||||
#define OPAMP_PGACONNECT_VM0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
|
||||
#define OPAMP_PGACONNECT_VM1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
|
||||
|
||||
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGACONNECT_NO) || \
|
||||
((CONNECT) == OPAMP_PGACONNECT_VM0) || \
|
||||
((CONNECT) == OPAMP_PGACONNECT_VM1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup OPAMP_PgaGain
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000) /*!< PGA gain = 2 */
|
||||
#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */
|
||||
#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */
|
||||
#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */
|
||||
|
||||
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_4) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_8) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_UserTrimming
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
|
||||
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
|
||||
|
||||
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
|
||||
((TRIMMING) == OPAMP_TRIMMING_USER))
|
||||
|
||||
/** @defgroup OPAMP_FactoryTrimming
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy trimming value */
|
||||
|
||||
#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */
|
||||
#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */
|
||||
|
||||
#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
|
||||
((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup OPAMP_TrimmingValue
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup OPAMP_Input
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_INPUT_INVERTING ((uint32_t) 24) /*!< Inverting input */
|
||||
#define OPAMP_INPUT_NONINVERTING ((uint32_t) 19) /*!< Non inverting input */
|
||||
|
||||
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
|
||||
((INPUT) == OPAMP_INPUT_NONINVERTING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup OPAMP_VREF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
|
||||
#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
|
||||
#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
|
||||
#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
|
||||
|
||||
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
|
||||
((VREF) == OPAMP_VREF_10VDDA) || \
|
||||
((VREF) == OPAMP_VREF_50VDDA) || \
|
||||
((VREF) == OPAMP_VREF_90VDDA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Vref2ADCforCalib
|
||||
*/
|
||||
|
||||
#define OPAMP_VREF_NOTCONNECTEDTO_ADC ((uint32_t)0x00000000) /*!< VREF not connected to ADC */
|
||||
#define OPAMP_VREF_CONNECTEDTO_ADC ((uint32_t)0x00000001) /*!< VREF not connected to ADC */
|
||||
|
||||
#define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
|
||||
((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset OPAMP handle state
|
||||
* @param __HANDLE__: OPAMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
|
||||
|
||||
/* Include OPAMP HAL Extension module */
|
||||
#include "stm32f3xx_hal_opamp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
|
||||
void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
|
||||
void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
|
||||
OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F303xC STM32F358xx STM32F302xC STM32F303x8 STM32F328xx
|
||||
STM32F302x8 STM32F301x8 STM32F318xx STM32F334x8 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_OPAMP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,725 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended OPAMP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (OPAMP) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMPEx
|
||||
* @brief OPAMP Extended HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMPEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMPEx_Group1 Extended I/O operation functions
|
||||
* @brief Extended Self calibration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F302xC)
|
||||
/* 2 OPAMPS available */
|
||||
/* 2 OPAMPS can be calibrated in parallel */
|
||||
|
||||
/**
|
||||
* @brief Run the self calibration of 2 OPAMPs in parallel.
|
||||
* @param hopamp1 handle
|
||||
* @param hopamp2 handle
|
||||
* @retval HAL status
|
||||
* @note Updated offset trimming values (PMOS & NMOS), user trimming is enabled
|
||||
* @note Calibration runs about 25 ms.
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
uint32_t trimmingvaluen1 = 0;
|
||||
uint32_t trimmingvaluep1 = 0;
|
||||
uint32_t trimmingvaluen2 = 0;
|
||||
uint32_t trimmingvaluep2 = 0;
|
||||
|
||||
uint32_t delta;
|
||||
|
||||
if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
|
||||
(hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Check if OPAMP in calibration mode and calibration not yet enable */
|
||||
if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY))
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
|
||||
|
||||
/* Set Calibration mode */
|
||||
/* Non-inverting input connected to calibration reference voltage. */
|
||||
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* user trimming values are used for offset calibration */
|
||||
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
|
||||
/* Enable calibration */
|
||||
SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
|
||||
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
|
||||
|
||||
/* 1st calibration - N */
|
||||
/* Select 90% VREF */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
|
||||
/* Enable the opamps */
|
||||
SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Init trimming counter */
|
||||
/* Medium value */
|
||||
trimmingvaluen1 = 16;
|
||||
trimmingvaluen2 = 16;
|
||||
delta = 8;
|
||||
|
||||
while (delta != 0)
|
||||
{
|
||||
// Set candidate trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen1 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen1 -= delta;
|
||||
}
|
||||
|
||||
if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen2 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen2 -= delta;
|
||||
}
|
||||
|
||||
delta >>= 1;
|
||||
}
|
||||
|
||||
// Still need to check if righ calibration is current value or un step below
|
||||
// Indeed the first value that causes the OUTCAL bit to change from 1 to 0
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen1++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen2++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
|
||||
/* 2nd calibration - P */
|
||||
/* Select 10% VREF */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
|
||||
/* Init trimming counter */
|
||||
/* Medium value */
|
||||
trimmingvaluep1 = 16;
|
||||
trimmingvaluep2 = 16;
|
||||
delta = 8;
|
||||
|
||||
while (delta != 0)
|
||||
{
|
||||
// Set candidate trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep1 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep1 -= delta;
|
||||
}
|
||||
|
||||
if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep2 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep2 -= delta;
|
||||
}
|
||||
|
||||
delta >>= 1;
|
||||
}
|
||||
|
||||
// Still need to check if righ calibration is current value or un step below
|
||||
// Indeed the first value that causes the OUTCAL bit to change from 1 to 0
|
||||
// Set candidate trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep1++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep2++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
/* Disable calibration */
|
||||
CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
|
||||
CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
|
||||
|
||||
/* Disable the OPAMPs */
|
||||
CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Set normale operating mode back */
|
||||
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* Self calibration is successful */
|
||||
/* Store calibration(user timming) results in init structure. */
|
||||
/* Select user timming mode */
|
||||
|
||||
/* Write calibration result N */
|
||||
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
|
||||
hopamp2->Init.TrimmingValueN = trimmingvaluen2;
|
||||
|
||||
/* Write calibration result P */
|
||||
hopamp1->Init.TrimmingValueP = trimmingvaluep1;
|
||||
hopamp2->Init.TrimmingValueP = trimmingvaluep2;
|
||||
|
||||
/* Calibration */
|
||||
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
|
||||
/* Select user timming mode */
|
||||
/* And updated with calibrated settings */
|
||||
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* At least one OPAMP can not be calibrated */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif /* STM32F302xC */
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx)
|
||||
/* 4 OPAMPS available */
|
||||
/* 4 OPAMPS can be calibrated in parallel */
|
||||
|
||||
/**
|
||||
* @brief Run the self calibration of 4 OPAMPs in parallel.
|
||||
* @param hopamp1 handle
|
||||
* @param hopamp2 handle
|
||||
* @param hopamp3 handle
|
||||
* @param hopamp4 handle
|
||||
* @retval HAL status
|
||||
* @note Updated offset trimming values (PMOS & NMOS), user trimming is enabled
|
||||
* @note Calibration runs about 25 ms.
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
uint32_t trimmingvaluen1 = 0;
|
||||
uint32_t trimmingvaluep1 = 0;
|
||||
uint32_t trimmingvaluen2 = 0;
|
||||
uint32_t trimmingvaluep2 = 0;
|
||||
uint32_t trimmingvaluen3 = 0;
|
||||
uint32_t trimmingvaluep3 = 0;
|
||||
uint32_t trimmingvaluen4 = 0;
|
||||
uint32_t trimmingvaluep4 = 0;
|
||||
|
||||
uint32_t delta;
|
||||
|
||||
if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
|
||||
(hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
|
||||
(hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
|
||||
(hopamp4 == NULL) || (hopamp4->State == HAL_OPAMP_STATE_BUSYLOCKED))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Check if OPAMP in calibration mode and calibration not yet enable */
|
||||
if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY) && \
|
||||
(hopamp3->State == HAL_OPAMP_STATE_READY) && (hopamp4->State == HAL_OPAMP_STATE_READY))
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
|
||||
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance));
|
||||
|
||||
/* Set Calibration mode */
|
||||
/* Non-inverting input connected to calibration reference voltage. */
|
||||
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* user trimming values are used for offset calibration */
|
||||
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM);
|
||||
|
||||
/* Enable calibration */
|
||||
SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
|
||||
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
|
||||
SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
|
||||
SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
|
||||
|
||||
/* 1st calibration - N */
|
||||
/* Select 90% VREF */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
|
||||
|
||||
/* Enable the opamps */
|
||||
SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Init trimming counter */
|
||||
/* Medium value */
|
||||
trimmingvaluen1 = 16;
|
||||
trimmingvaluen2 = 16;
|
||||
trimmingvaluen3 = 16;
|
||||
trimmingvaluen4 = 16;
|
||||
delta = 8;
|
||||
|
||||
while (delta != 0)
|
||||
{
|
||||
/* Set candidate trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen1 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen1 -= delta;
|
||||
}
|
||||
|
||||
if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen2 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen2 -= delta;
|
||||
}
|
||||
|
||||
if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen3 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen3 -= delta;
|
||||
}
|
||||
|
||||
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluen4 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is LOW try lower trimming */
|
||||
trimmingvaluen4 -= delta;
|
||||
}
|
||||
|
||||
delta >>= 1;
|
||||
}
|
||||
|
||||
/* Still need to check if righ calibration is current value or un step below */
|
||||
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen1++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen2++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen3++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluen4++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
|
||||
}
|
||||
|
||||
/* 2nd calibration - P */
|
||||
/* Select 10% VREF */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
|
||||
|
||||
/* Init trimming counter */
|
||||
/* Medium value */
|
||||
trimmingvaluep1 = 16;
|
||||
trimmingvaluep2 = 16;
|
||||
trimmingvaluep3 = 16;
|
||||
trimmingvaluep4 = 16;
|
||||
|
||||
delta = 8;
|
||||
|
||||
while (delta != 0)
|
||||
{
|
||||
/* Set candidate trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep1 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep1 -= delta;
|
||||
}
|
||||
|
||||
if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep2 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep2 -= delta;
|
||||
}
|
||||
|
||||
if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep3 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep3 -= delta;
|
||||
}
|
||||
|
||||
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
|
||||
trimmingvaluep4 += delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
trimmingvaluep4 -= delta;
|
||||
}
|
||||
|
||||
delta >>= 1;
|
||||
}
|
||||
|
||||
/* Still need to check if righ calibration is current value or un step below */
|
||||
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
|
||||
/* Set candidate trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
|
||||
/* Offset trim time: during calibration, minimum time needed between */
|
||||
/* two steps to have 1 mV accuracy */
|
||||
HAL_Delay(2);
|
||||
|
||||
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep1++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep2++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep3++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
|
||||
{
|
||||
/* OPAMP_CSR_OUTCAL is actually one value more */
|
||||
trimmingvaluep4++;
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
|
||||
}
|
||||
|
||||
/* Disable calibration */
|
||||
CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
|
||||
CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
|
||||
CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
|
||||
CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
|
||||
|
||||
/* Disable the OPAMPs */
|
||||
CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
|
||||
|
||||
/* Set normale operating mode back */
|
||||
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
|
||||
|
||||
/* Self calibration is successful */
|
||||
/* Store calibration(user timming) results in init structure. */
|
||||
/* Select user timming mode */
|
||||
|
||||
/* Write calibration result N */
|
||||
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
|
||||
hopamp2->Init.TrimmingValueN = trimmingvaluen2;
|
||||
hopamp3->Init.TrimmingValueN = trimmingvaluen3;
|
||||
hopamp4->Init.TrimmingValueN = trimmingvaluen4;
|
||||
|
||||
/* Write calibration result P */
|
||||
hopamp1->Init.TrimmingValueP = trimmingvaluep1;
|
||||
hopamp2->Init.TrimmingValueP = trimmingvaluep2;
|
||||
hopamp3->Init.TrimmingValueP = trimmingvaluep3;
|
||||
hopamp4->Init.TrimmingValueP = trimmingvaluep4;
|
||||
|
||||
/* Select user timming mode */
|
||||
/* And updated with calibrated settings */
|
||||
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER;
|
||||
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<<OPAMP_INPUT_INVERTING);
|
||||
|
||||
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<<OPAMP_INPUT_NONINVERTING);
|
||||
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<<OPAMP_INPUT_NONINVERTING);
|
||||
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* At least one OPAMP can not be calibrated */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_opamp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of OPAMP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_OPAMP_EX_H
|
||||
#define __STM32F3xx_HAL_OPAMP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMPEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMPEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
|
||||
#if defined (STM32F302xC)
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
|
||||
|
||||
#endif /* STM32F302xC */
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx)
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4);
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_OPAMP_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,710 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_PCD_H
|
||||
#define __STM32F3xx_HAL_PCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief PCD State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PCD_READY = 0x00,
|
||||
PCD_ERROR = 0x01,
|
||||
PCD_BUSY = 0x02,
|
||||
PCD_TIMEOUT = 0x03
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/* double buffered endpoint direction */
|
||||
PCD_EP_DBUF_OUT,
|
||||
PCD_EP_DBUF_IN,
|
||||
PCD_EP_DBUF_ERR,
|
||||
}PCD_EP_DBUF_DIR;
|
||||
|
||||
/* endpoint buffer number */
|
||||
typedef enum
|
||||
{
|
||||
PCD_EP_NOBUF,
|
||||
PCD_EP_BUF0,
|
||||
PCD_EP_BUF1
|
||||
}PCD_EP_BUF_NUM;
|
||||
|
||||
/**
|
||||
* @brief PCD Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||
This parameter depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed */
|
||||
|
||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
|
||||
This parameter can be any value of @ref USB_EP0_MPS */
|
||||
|
||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref USB_Core_PHY */
|
||||
|
||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
|
||||
|
||||
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
}PCD_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t num; /*!< Endpoint number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t is_stall; /*!< Endpoint stall condition
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t type; /*!< Endpoint type
|
||||
This parameter can be any value of @ref USB_EP_Type */
|
||||
|
||||
uint16_t pmaadress; /*!< PMA Address
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
|
||||
uint16_t pmaaddr0; /*!< PMA Address0
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
|
||||
uint16_t pmaaddr1; /*!< PMA Address1
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
|
||||
uint8_t doublebuffer; /*!< Double buffer enable
|
||||
This parameter can be 0 or 1 */
|
||||
|
||||
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||
|
||||
}PCD_EPTypeDef;
|
||||
|
||||
typedef USB_TypeDef PCD_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_EPTypeDef IN_ep[5]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[5]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
#include "stm32f3xx_hal_pcd_ex.h"
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_HIGH 0 /* Not Supported */
|
||||
#define PCD_SPEED_FULL 2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_PHY
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_EMBEDDED 2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_EP0_MPS
|
||||
* @{
|
||||
*/
|
||||
#define DEP0CTL_MPS_64 0
|
||||
#define DEP0CTL_MPS_32 1
|
||||
#define DEP0CTL_MPS_16 2
|
||||
#define DEP0CTL_MPS_8 3
|
||||
|
||||
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
|
||||
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
|
||||
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
|
||||
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_EP_Type
|
||||
* @{
|
||||
*/
|
||||
#define PCD_EP_TYPE_CTRL 0
|
||||
#define PCD_EP_TYPE_ISOC 1
|
||||
#define PCD_EP_TYPE_BULK 2
|
||||
#define PCD_EP_TYPE_INTR 3
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define PCD_ENDP0 ((uint8_t)0)
|
||||
#define PCD_ENDP1 ((uint8_t)1)
|
||||
#define PCD_ENDP2 ((uint8_t)2)
|
||||
#define PCD_ENDP3 ((uint8_t)3)
|
||||
#define PCD_ENDP4 ((uint8_t)4)
|
||||
#define PCD_ENDP5 ((uint8_t)5)
|
||||
#define PCD_ENDP6 ((uint8_t)6)
|
||||
#define PCD_ENDP7 ((uint8_t)7)
|
||||
|
||||
/* Endpoint Kind */
|
||||
#define PCD_SNG_BUF 0
|
||||
#define PCD_DBL_BUF 1
|
||||
|
||||
#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCD_Interrupt_Clock
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) = ~(__INTERRUPT__))
|
||||
|
||||
#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
||||
|
||||
#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP
|
||||
#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP)
|
||||
#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
|
||||
|
||||
/* Internal macros -----------------------------------------------------------*/
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&USBx->EP0R + bEpNum * 2)= (uint16_t)wRegValue)
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&USBx->EP0R + bEpNum * 2))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wType: Endpoint Type.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT(USBx, bEpNum,\
|
||||
((PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_T_MASK) | wType )))
|
||||
|
||||
/**
|
||||
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint Type
|
||||
*/
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_T_FIELD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief free buffer used from the application realizing it to the line
|
||||
toggles bit SW_BUF in the double buffered endpoint register
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDir: Direction
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
|
||||
{\
|
||||
if (bDir == PCD_EP_DBUF_OUT)\
|
||||
{ /* OUT double buffered endpoint */\
|
||||
PCD_TX_DTOG(USBx, bEpNum);\
|
||||
}\
|
||||
else if (bDir == PCD_EP_DBUF_IN)\
|
||||
{ /* IN double buffered endpoint */\
|
||||
PCD_RX_DTOG(USBx, bEpNum);\
|
||||
}\
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief gets direction of the double buffered endpoint
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval EP_DBUF_OUT, EP_DBUF_IN,
|
||||
* EP_DBUF_ERR if the endpoint counter not yet programmed.
|
||||
*/
|
||||
#define PCD_GET_DB_DIR(USBx, bEpNum)\
|
||||
{\
|
||||
if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00) != 0)\
|
||||
return(PCD_EP_DBUF_OUT);\
|
||||
else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FF) != 0)\
|
||||
return(PCD_EP_DBUF_IN);\
|
||||
else\
|
||||
return(PCD_EP_DBUF_ERR);\
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wState: new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_DTOGMASK;\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPTX_DTOG1 & wState)!= 0) \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPTX_DTOG2 & wState)!= 0) \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||
} /* PCD_SET_EP_TX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wState: new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_DTOGMASK;\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPRX_DTOG1 & wState)!= 0) \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPRX_DTOG2 & wState)!= 0) \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||
} /* PCD_SET_EP_RX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wStaterx: new state.
|
||||
* @param wStatetx: new state.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
|
||||
register uint32_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPRX_DTOG1 & wStaterx)!= 0) \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPRX_DTOG2 & wStaterx)!= 0) \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPTX_DTOG1 & wStatetx)!= 0) \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPTX_DTOG2 & wStatetx)!= 0) \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
PCD_SET_ENDPOINT(USBx, bEpNum, _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
|
||||
} /* PCD_SET_EP_TXRX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval status
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_STAT)
|
||||
|
||||
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_STAT)
|
||||
|
||||
/**
|
||||
* @brief sets directly the VALID tx/rx-status into the endpoint register
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS(USBx, bEpNum, USB_EP_TX_VALID))
|
||||
|
||||
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS(USBx, bEpNum, USB_EP_RX_VALID))
|
||||
|
||||
/**
|
||||
* @brief checks stall condition in an endpoint.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval TRUE = endpoint in stall condition.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS(USBx, bEpNum) \
|
||||
== USB_EP_TX_STALL)
|
||||
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS(USBx, bEpNum) \
|
||||
== USB_EP_RX_STALL)
|
||||
|
||||
/**
|
||||
* @brief set & clear EP_KIND bit.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum, \
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT(USBx, bEpNum) | USB_EP_KIND) & USB_EPREG_MASK))))
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum, \
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPKIND_MASK))))
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND(USBx, bEpNum)
|
||||
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND(USBx, bEpNum)
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND(USBx, bEpNum)
|
||||
#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND(USBx, bEpNum)
|
||||
|
||||
/**
|
||||
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum,\
|
||||
PCD_GET_ENDPOINT(USBx, bEpNum) & 0x7FFF & USB_EPREG_MASK))
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum,\
|
||||
PCD_GET_ENDPOINT(USBx, bEpNum) & 0xFF7F & USB_EPREG_MASK))
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum, \
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPREG_MASK)))
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum, \
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPREG_MASK)))
|
||||
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_DTOG_RX) != 0)\
|
||||
PCD_RX_DTOG(USBx, bEpNum)
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_DTOG_TX) != 0)\
|
||||
PCD_TX_DTOG(USBx, bEpNum)
|
||||
|
||||
/**
|
||||
* @brief Sets address in an endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bAddr: Address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT(USBx, bEpNum,\
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPREG_MASK) | bAddr)
|
||||
|
||||
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPADDR_FIELD))
|
||||
|
||||
/**
|
||||
* @brief sets address of the tx/rx buffer.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wAddr: address to be set (must be word aligned).
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1) << 1))
|
||||
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1) << 1))
|
||||
|
||||
/**
|
||||
* @brief Gets address of the tx/rx buffer.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval address of the buffer.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS(USBx, bEpNum))
|
||||
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS(USBx, bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Sets counter of rx buffer with no. of blocks.
|
||||
* @param dwReg: Register
|
||||
* @param wCount: Counter.
|
||||
* @param wNBlocks: no. of Blocks.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
|
||||
wNBlocks = wCount >> 5;\
|
||||
if((wCount & 0x1f) == 0)\
|
||||
wNBlocks--;\
|
||||
*pdwReg = (uint16_t)((wNBlocks << 10) | 0x8000);\
|
||||
}/* PCD_CALC_BLK32 */
|
||||
|
||||
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
|
||||
wNBlocks = wCount >> 1;\
|
||||
if((wCount & 0x1) != 0)\
|
||||
wNBlocks++;\
|
||||
*pdwReg = (uint16_t)(wNBlocks << 10);\
|
||||
}/* PCD_CALC_BLK2 */
|
||||
|
||||
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
|
||||
uint16_t wNBlocks;\
|
||||
if(wCount > 62){PCD_CALC_BLK32(dwReg,wCount,wNBlocks);}\
|
||||
else {PCD_CALC_BLK2(dwReg,wCount,wNBlocks);}\
|
||||
}/* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
|
||||
uint16_t *pdwReg = PCD_EP_TX_CNT(USBx, bEpNum); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
|
||||
}
|
||||
/**
|
||||
* @brief sets counter for the tx/rx buffer.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wCount: Counter value.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT(USBx, bEpNum) = wCount)
|
||||
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x3ff)
|
||||
#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum)) & 0x3ff)
|
||||
|
||||
/**
|
||||
* @brief Sets buffer 0/1 address in a double buffer endpoint.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wBuf0Addr: buffer 0 address.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wBuf0Addr);}
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wBuf1Addr);}
|
||||
|
||||
/**
|
||||
* @brief Sets addresses in a double buffer endpoint.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wBuf0Addr: buffer 0 address.
|
||||
* @param wBuf1Addr = buffer 1 address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
|
||||
PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr);\
|
||||
PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr);\
|
||||
} /* PCD_SET_EP_DBUF_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS(USBx, bEpNum))
|
||||
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS(USBx, bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDir: endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* @param wCount: Counter value
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
|
||||
if(bDir == PCD_EP_DBUF_OUT)\
|
||||
/* OUT endpoint */ \
|
||||
{PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount);} \
|
||||
else if(bDir == PCD_EP_DBUF_IN)\
|
||||
/* IN endpoint */ \
|
||||
*PCD_EP_TX_CNT(USBx, bEpNum) = (uint32_t)wCount; \
|
||||
} /* SetEPDblBuf0Count*/
|
||||
|
||||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
|
||||
if(bDir == PCD_EP_DBUF_OUT)\
|
||||
/* OUT endpoint */ \
|
||||
{PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount);}\
|
||||
else if(bDir == PCD_EP_DBUF_IN)\
|
||||
/* IN endpoint */\
|
||||
*PCD_EP_RX_CNT(USBx, bEpNum) = (uint32_t)wCount; \
|
||||
} /* SetEPDblBuf1Count */
|
||||
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
|
||||
PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount); \
|
||||
PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount); \
|
||||
} /* PCD_SET_EP_DBUF_CNT */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT(USBx, bEpNum))
|
||||
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT(USBx, bEpNum))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
/* Peripheral State functions **************************************************/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_PCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended PCD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
* + Configururation of the PMA for EP
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx
|
||||
* @brief PCD HAL Extended module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup PCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral extended features methods #####
|
||||
===============================================================================
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure PMA for EP
|
||||
* @param hpcd : PCD handle
|
||||
* @param ep_addr: endpoint address
|
||||
* @param ep_kind: endpoint Kind
|
||||
* @arg USB_SNG_BUF: Single Buffer used
|
||||
* @arg USB_DBL_BUF: Double Buffer used
|
||||
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
|
||||
* this parameter is 16-bit value providing the address
|
||||
* in PMA allocated to endpoint.
|
||||
* In case of double buffer endpoint this parameter
|
||||
* is a 32-bit value providing the endpoint buffer 0 address
|
||||
* in the LSB part of 32-bit value and endpoint buffer 1 address
|
||||
* in the MSB part of 32-bit value.
|
||||
* @retval : status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||
uint16_t ep_addr,
|
||||
uint16_t ep_kind,
|
||||
uint32_t pmaadress)
|
||||
|
||||
{
|
||||
PCD_EPTypeDef *ep;
|
||||
|
||||
/* initialize ep structure*/
|
||||
if ((0x80 & ep_addr) == 0x80)
|
||||
{
|
||||
ep = &hpcd->IN_ep[ep_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &hpcd->OUT_ep[ep_addr];
|
||||
}
|
||||
|
||||
/* Here we check if the endpoint is single or double Buffer*/
|
||||
if (ep_kind == PCD_SNG_BUF)
|
||||
{
|
||||
/*Single Buffer*/
|
||||
ep->doublebuffer = 0;
|
||||
/*Configure te PMA*/
|
||||
ep->pmaadress = (uint16_t)pmaadress;
|
||||
}
|
||||
else /*USB_DBL_BUF*/
|
||||
{
|
||||
/*Double Buffer Endpoint*/
|
||||
ep->doublebuffer = 1;
|
||||
/*Configure the PMA*/
|
||||
ep->pmaaddr0 = pmaadress & 0xFFFF;
|
||||
ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from user memory area to packet memory area (PMA)
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param pbUsrBuf: pointer to user memory area.
|
||||
* @param wPMABufAddr: address into PMA.
|
||||
* @param wNBytes: no. of bytes to be copied.
|
||||
* @retval None
|
||||
*/
|
||||
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
|
||||
uint32_t i, temp1, temp2;
|
||||
uint16_t *pdwVal;
|
||||
pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
temp1 = (uint16_t) * pbUsrBuf;
|
||||
pbUsrBuf++;
|
||||
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
|
||||
*pdwVal++ = temp2;
|
||||
pdwVal++;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from user memory area to packet memory area (PMA)
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param pbUsrBuf = pointer to user memory area.
|
||||
* @param wPMABufAddr: address into PMA.
|
||||
* @param wNBytes: no. of bytes to be copied.
|
||||
* @retval None
|
||||
*/
|
||||
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1;/* /2*/
|
||||
uint32_t i;
|
||||
uint32_t *pdwVal;
|
||||
pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
*(uint16_t*)pbUsrBuf++ = *pdwVal++;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC)
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from user memory area to packet memory area (PMA)
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param pbUsrBuf: pointer to user memory area.
|
||||
* @param wPMABufAddr: address into PMA.
|
||||
* @param wNBytes: no. of bytes to be copied.
|
||||
* @retval None
|
||||
*/
|
||||
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1;
|
||||
uint32_t i;
|
||||
uint16_t temp1, temp2;
|
||||
uint16_t *pdwVal;
|
||||
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
|
||||
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
temp1 = (uint16_t) * pbUsrBuf;
|
||||
pbUsrBuf++;
|
||||
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
|
||||
*pdwVal++ = temp2;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from user memory area to packet memory area (PMA)
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param pbUsrBuf = pointer to user memory area.
|
||||
* @param wPMABufAddr: address into PMA.
|
||||
* @param wNBytes: no. of bytes to be copied.
|
||||
* @retval None
|
||||
*/
|
||||
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1;
|
||||
uint32_t i;
|
||||
uint16_t *pdwVal;
|
||||
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
*(uint16_t*)pbUsrBuf++ = *pdwVal++;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Software Device Connection
|
||||
* @param hpcd: PCD handle
|
||||
* @param state: Device state
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_SetConnectionState could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) */
|
||||
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_PCD_EX_H
|
||||
#define __STM32F3xx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Gets address in an endpoint register.
|
||||
* @param USBx: USB peripheral instance register address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
|
||||
|
||||
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8)*2+ ((uint32_t)USBx + 0x400)))
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+2)*2+ ((uint32_t)USBx + 0x400)))
|
||||
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+4)*2+ ((uint32_t)USBx + 0x400)))
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+6)*2+ ((uint32_t)USBx + 0x400)))
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
|
||||
uint32_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
|
||||
}
|
||||
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F373xC */
|
||||
|
||||
|
||||
#if defined(STM32F302x8)
|
||||
|
||||
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8)+ ((uint32_t)USBx + 0x400)))
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+2)+ ((uint32_t)USBx + 0x400)))
|
||||
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+4)+ ((uint32_t)USBx + 0x400)))
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+6)+ ((uint32_t)USBx + 0x400)))
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
|
||||
uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
|
||||
}
|
||||
|
||||
#endif /* STM32F302x8 */
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||
uint16_t ep_addr,
|
||||
uint16_t ep_kind,
|
||||
uint32_t pmaadress);
|
||||
|
||||
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_PCD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,450 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief PWR HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers and backup SRAM) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__PWR_FORCE_RESET();
|
||||
__PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
(+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
|
||||
forced in input pull down configuration and is active on rising edges.
|
||||
(+) There are up to three WakeUp pins:
|
||||
WakeUp Pin 1 on PA.00.
|
||||
WakeUp Pin 2 on PC.13 (STM32F303xC, only).
|
||||
WakeUp Pin 3 on PE.06.
|
||||
|
||||
*** Main and Backup Regulators configuration ***
|
||||
================================================
|
||||
[..]
|
||||
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
|
||||
the backup SRAM is powered from VDD which replaces the VBAT power supply to
|
||||
save battery life.
|
||||
|
||||
(+) The backup SRAM is not mass erased by an tamper event. It is read
|
||||
protected to prevent confidential data, such as cryptographic private
|
||||
key, from being accessed. The backup SRAM can be erased only through
|
||||
the Flash interface when a protection level change from level 1 to
|
||||
level 0 is requested.
|
||||
-@- Refer to the description of Read protection (RDP) in the Flash
|
||||
programming manual.
|
||||
|
||||
Refer to the datasheets for more details.
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 3 low-power modes:
|
||||
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator
|
||||
in low power mode
|
||||
(+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
|
||||
(++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
(++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||||
when programmed in wakeup mode (the peripheral must be
|
||||
programmed in wakeup mode and the corresponding interrupt vector
|
||||
must be enabled in the NVIC)
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
|
||||
The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers, backup SRAM and Standby
|
||||
circuitry.
|
||||
The voltage regulator is OFF.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
|
||||
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||||
(+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
tmp = CSR_EWUP1_BB + (WakeUpPinx << 2);
|
||||
*(__IO uint32_t *) (tmp) = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
tmp = CSR_EWUP1_BB + (WakeUpPinx << 2);
|
||||
*(__IO uint32_t *) (tmp) = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator: Specifies the regulator state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||||
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Select the regulator state in SLEEP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||||
|
||||
/* Set LPDS bit according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator: Specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||||
* @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||||
|
||||
/* Set LPDS bit according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
|
||||
* - WKUP pin 1 (PA0) if enabled.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_PWR_H
|
||||
#define __STM32F3xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* ------------- PWR registers bit address in the alias region ---------------*/
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||
/* Alias word address of DBP bit */
|
||||
#define DBP_BitNumber POSITION_VAL(PWR_CR_DBP)
|
||||
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BitNumber POSITION_VAL(PWR_CR_PVDE)
|
||||
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||
/* Alias word address of EWUP1 bit */
|
||||
#define EWUP1_BitNumber POSITION_VAL(PWR_CSR_EWUP1)
|
||||
#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
|
||||
|
||||
/* Alias word address of EWUP2 bit */
|
||||
#define EWUP2_BitNumber POSITION_VAL(PWR_CSR_EWUP2)
|
||||
#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
|
||||
|
||||
/* Alias word address of EWUP3 bit */
|
||||
#define EWUP3_BitNumber POSITION_VAL(PWR_CSR_EWUP3)
|
||||
#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP3_BitNumber * 4))
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)0x01)
|
||||
#define PWR_WAKEUP_PIN3 ((uint32_t)0x02)
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm (Alarm A
|
||||
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
||||
* An additional wakeup event is detected if the WKUP pin is enabled
|
||||
* (by setting the EWUP bit) when the WKUP pin level is already high.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
|
||||
* voltage VREFINT is ready.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32f3xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended PWR HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx
|
||||
* @brief PWR Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Group1 Extended Peripheral Initialization and de-initialization functions
|
||||
* @brief Extended Peripheral Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Peripheral Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Group2 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Extended Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
*** PVD configuration (present on all other devices than STM32F3x8 devices) ***
|
||||
=========================
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PVD_EXTI_ENABLE_IT() macro
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
(+) Note: PVD is not available on STM32F3x8 Product Line
|
||||
|
||||
|
||||
*** Voltage regulator ***
|
||||
=========================
|
||||
(+) The voltage regulator is always enabled after Reset. It works in three different
|
||||
modes:
|
||||
In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
|
||||
and digital peripherals).
|
||||
In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
|
||||
contents of registers and SRAM.
|
||||
In Stop mode, the regulator is powered off. The contents of the registers and SRAM
|
||||
are lost except for the Standby circuitry and the Backup Domain.
|
||||
Note: In the STM32F3x8xx devices, the voltage regulator is bypassed and the
|
||||
microcontroller must be powered from a nominal VDD = 1.8V +/-8% voltage.
|
||||
|
||||
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PVD_EXTI_ENABLE_IT() macro
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
|
||||
*** SDADC power configuration ***
|
||||
================================
|
||||
(+) On STM32F373xC/STM32F378xx devices, there are up to
|
||||
3 SDADC instances that can be enabled/disabled.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8)
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Configure the EXTI 16 interrupt */
|
||||
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
|
||||
(sConfigPVD->Mode == PWR_MODE_IT_FALLING) ||\
|
||||
(sConfigPVD->Mode == PWR_MODE_IT_RISING))
|
||||
{
|
||||
__HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD);
|
||||
}
|
||||
/* Configure the rising edge */
|
||||
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
|
||||
(sConfigPVD->Mode == PWR_MODE_IT_RISING))
|
||||
{
|
||||
EXTI->RTSR |= PWR_EXTI_LINE_PVD;
|
||||
}
|
||||
/* Configure the falling edge */
|
||||
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
|
||||
(sConfigPVD->Mode == PWR_MODE_IT_FALLING))
|
||||
{
|
||||
EXTI->FTSR |= PWR_EXTI_LINE_PVD;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler().
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303x8 || STM32F303xC */
|
||||
/* STM32F373xC || STM32F334x8 */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
/**
|
||||
* @brief Enables the SDADC peripheral functionaliy
|
||||
* @param Analogx: specifies the SDADC peripheral instance.
|
||||
* This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableSDADCAnalog(uint32_t Analogx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_SDADC_ANALOG(Analogx));
|
||||
|
||||
/* Enable PWR clock interface for SDADC use */
|
||||
__PWR_CLK_ENABLE();
|
||||
|
||||
PWR->CR |= Analogx;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the SDADC peripheral functionaliy
|
||||
* @param Analogx: specifies the SDADC peripheral instance.
|
||||
* This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableSDADCAnalog(uint32_t Analogx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_SDADC_ANALOG(Analogx));
|
||||
|
||||
PWR->CR &= ~Analogx;
|
||||
}
|
||||
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_PWR_EX_H
|
||||
#define __STM32F3xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8)
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
|
||||
This parameter can be a value of @ref PWREx_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303x8 || STM32F303xC */
|
||||
/* STM32F373xC || STM32F334x8 */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8)
|
||||
/** @defgroup PWREx_PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVD_Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
|
||||
#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
|
||||
((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303x8 || STM32F303xC */
|
||||
/* STM32F373xC || STM32F334x8 */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/** @defgroup PWREx_SDADC_ANALOGx
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_SDADC1EN)
|
||||
#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_SDADC2EN)
|
||||
#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_SDADC3EN)
|
||||
#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
|
||||
((SDADC) == PWR_SDADC_ANALOG2) || \
|
||||
((SDADC) == PWR_SDADC_ANALOG3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8)
|
||||
/**
|
||||
* @brief Enable the PVD Exti Line.
|
||||
* @param __EXTILINE__: specifies the PVD EXTI sources to be enabled.
|
||||
* This parameter can be:
|
||||
* @arg PWR_EXTI_LINE_PVD
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD EXTI Line.
|
||||
* @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
|
||||
* This parameter can be:
|
||||
* @arg PWR_EXTI_LINE_PVD
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
|
||||
* This parameter can be:
|
||||
* @arg PWR_EXTI_LINE_PVD
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
|
||||
* @param __EXTILINE__: specifies the PVD EXTI sources to be cleared.
|
||||
* This parameter can be:
|
||||
* @arg PWR_EXTI_LINE_PVD
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag.
|
||||
* @param __EXTILINE__: specifies the PVD EXTI sources to be cleared.
|
||||
* This parameter can be:
|
||||
* @arg PWR_EXTI_LINE_PVD
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303x8 || STM32F303xC */
|
||||
/* STM32F373xC || STM32F334x8 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8)
|
||||
void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303x8 || STM32F303xC */
|
||||
/* STM32F373xC || STM32F334x8 */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
void HAL_PWREx_EnableSDADCAnalog(uint32_t Analogx);
|
||||
void HAL_PWREx_DisableSDADCAnalog(uint32_t Analogx);
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,622 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended RCC HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
* + Extended Clock Source configuration functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx
|
||||
* @brief RCC Extended HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the RCC Clocks
|
||||
frequencies.
|
||||
[..]
|
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
|
||||
select the RTC clock source; in this case the Backup domain will be reset in
|
||||
order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified
|
||||
* parameters in the RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks
|
||||
* (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
|
||||
*
|
||||
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
|
||||
* the RTC clock source; in this case the Backup domain will be reset in
|
||||
* order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
* the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
|
||||
|
||||
|
||||
/*---------------------------- RTC configuration -------------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
||||
{
|
||||
/* Enable Power Clock*/
|
||||
__PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable write access to Backup domain */
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while((PWR->CR & PWR_CR_DBP) == RESET)
|
||||
{
|
||||
if((HAL_GetTick()-tickstart) > DBP_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selction is modified */
|
||||
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
||||
{
|
||||
/* Store the content of BDCR register before the reset of Backup Domain */
|
||||
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
/* Restore the Content of BDCR register */
|
||||
RCC->BDCR = tmpreg;
|
||||
}
|
||||
|
||||
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
|
||||
if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
|
||||
{
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick()-tickstart) > LSE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------- USART1 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
||||
|
||||
/* Configure the USART1 clock source */
|
||||
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
||||
}
|
||||
|
||||
/*----------------------------- USART2 Configuration --------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
||||
|
||||
/* Configure the USART2 clock source */
|
||||
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------ USART3 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
||||
|
||||
/* Configure the USART3 clock source */
|
||||
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------ I2C1 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
||||
|
||||
/* Configure the I2C1 clock source */
|
||||
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
||||
}
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC)
|
||||
|
||||
/*------------------------------ USB Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
|
||||
|
||||
/* Configure the USB clock source */
|
||||
__HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303xC || STM32F373xC */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
/*------------------------------ I2C2 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
||||
|
||||
/* Configure the I2C2 clock source */
|
||||
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
|
||||
/*------------------------------ I2C3 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
||||
|
||||
/* Configure the I2C3 clock source */
|
||||
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
/*------------------------------ UART4 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
||||
|
||||
/* Configure the UART4 clock source */
|
||||
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------ UART5 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
||||
|
||||
/* Configure the UART5 clock source */
|
||||
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
/*------------------------------ I2S Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
|
||||
|
||||
/* Configure the I2S clock source */
|
||||
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
|
||||
/*------------------------------ ADC1 clock Configuration ------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
|
||||
|
||||
/* Configure the ADC1 clock source */
|
||||
__HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
|
||||
/*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
|
||||
|
||||
/* Configure the ADC12 clock source */
|
||||
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
/*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
|
||||
|
||||
/* Configure the ADC34 clock source */
|
||||
__HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
/*------------------------------ ADC1 clock Configuration ------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
|
||||
|
||||
/* Configure the ADC1 clock source */
|
||||
__HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
|
||||
/*------------------------------ TIM1 clock Configuration ----------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
|
||||
|
||||
/* Configure the TIM1 clock source */
|
||||
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
/*------------------------------ TIM8 clock Configuration ----------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
|
||||
|
||||
/* Configure the TIM8 clock source */
|
||||
__HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
|
||||
/*------------------------------ TIM15 clock Configuration ----------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
|
||||
|
||||
/* Configure the TIM15 clock source */
|
||||
__HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------ TIM16 clock Configuration ----------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
|
||||
|
||||
/* Configure the TIM16 clock source */
|
||||
__HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------ TIM17 clock Configuration ----------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
|
||||
|
||||
/* Configure the TIM17 clock source */
|
||||
__HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
#if defined(STM32F334x8)
|
||||
|
||||
/*------------------------------ HRTIM1 clock Configuration ----------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
|
||||
|
||||
/* Configure the HRTIM1 clock source */
|
||||
__HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F334x8 */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
/*------------------------------ SDADC clock Configuration -------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
|
||||
|
||||
/* Configure the SDADC clock prescaler */
|
||||
__HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
|
||||
}
|
||||
|
||||
/*------------------------------ CEC clock Configuration -------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
||||
|
||||
/* Configure the CEC clock source */
|
||||
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
||||
}
|
||||
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the RCC_ClkInitStruct according to the internal
|
||||
* RCC configuration registers.
|
||||
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* returns the configuration information for the Extended Peripherals clocks
|
||||
* (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
/* Set all possible values for the extended clock type parameter------------*/
|
||||
/* Common part first */
|
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
|
||||
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
|
||||
|
||||
/* Get the RTC configuration --------------------------------------------*/
|
||||
PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
|
||||
/* Get the USART1 clock configuration --------------------------------------------*/
|
||||
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
|
||||
/* Get the USART2 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
|
||||
/* Get the USART3 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
|
||||
/* Get the I2C1 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
|
||||
/* Get the USB clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
|
||||
|
||||
#endif /* STM32F302x8 || STM32F302xC || */
|
||||
/* STM32F303xC || STM32F373xC */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
|
||||
/* Get the I2C2 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
|
||||
/* Get the I2C3 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
|
||||
/* Get the UART4 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
|
||||
/* Get the UART5 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
|
||||
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
|
||||
/* Get the I2S clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
|
||||
/* Get the ADC1 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
|
||||
/* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
|
||||
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
|
||||
/* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
|
||||
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
|
||||
/* Get the TIM1 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
|
||||
/* Get the TIM15 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
|
||||
/* Get the TIM16 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
|
||||
/* Get the TIM17 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
|
||||
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
|
||||
/* Get the TIM8 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
|
||||
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F334x8)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
|
||||
/* Get the HRTIM1 clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
|
||||
|
||||
#endif /* STM32F334x8 */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
|
||||
/* Get the SDADC clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
|
||||
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
|
||||
/* Get the CEC clock configuration -----------------------------------------*/
|
||||
PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
|
||||
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,751 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_RTC_H
|
||||
#define __STM32F3xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
|
||||
|
||||
}HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Time Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
}RTC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
|
||||
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
|
||||
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
|
||||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
|
||||
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
|
||||
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
|
||||
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
|
||||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000
|
||||
|
||||
/** @defgroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
|
||||
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
||||
((FORMAT) == RTC_HOURFORMAT_24))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
|
||||
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
|
||||
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
|
||||
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
|
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
|
||||
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
|
||||
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
|
||||
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define FORMAT_BIN ((uint32_t)0x000000000)
|
||||
#define FORMAT_BCD ((uint32_t)0x000000001)
|
||||
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
|
||||
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
|
||||
|
||||
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
||||
#define RTC_ALARM_B RTC_CR_ALRBE
|
||||
|
||||
#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_IT_WUT ((uint32_t)0x00004000)
|
||||
#define RTC_IT_ALRB ((uint32_t)0x00002000)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
|
||||
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__: RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCA; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFF; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @arg RTC_FLAG_ALRAWF
|
||||
* @arg RTC_FLAG_ALRBWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
|
||||
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Exti line.
|
||||
* @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_EXTI_LINE_ALARM_EVENT
|
||||
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
|
||||
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
|
||||
|
||||
/* alias define maintained for legacy */
|
||||
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Exti line.
|
||||
* @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_EXTI_LINE_ALARM_EVENT
|
||||
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
|
||||
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
|
||||
|
||||
/* alias define maintained for legacy */
|
||||
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_EXTI_LINE_ALARM_EVENT
|
||||
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
|
||||
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Exti flags.
|
||||
* @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_EXTI_LINE_ALARM_EVENT
|
||||
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
|
||||
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
|
||||
|
||||
/* alias define maintained for legacy */
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
|
||||
/* Include RTC HAL Extension module */
|
||||
#include "stm32f3xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
|
||||
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_RTC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,660 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of RTC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_RTC_EX_H
|
||||
#define __STM32F3xx_HAL_RTC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief RTC Tamper structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Tamper; /*!< Specifies the Tamper Pin.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
|
||||
|
||||
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
|
||||
|
||||
uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
|
||||
|
||||
uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
|
||||
|
||||
uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
|
||||
|
||||
uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
|
||||
|
||||
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
|
||||
}RTC_TamperTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
|
||||
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
|
||||
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
|
||||
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
|
||||
((OUTPUT) == RTC_OUTPUT_WAKEUP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Backup_Registers_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
|
||||
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
|
||||
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
|
||||
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
|
||||
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
|
||||
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
|
||||
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
|
||||
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
|
||||
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
|
||||
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
|
||||
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
|
||||
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define RTC_BKP_DR16 ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_DR17 ((uint32_t)0x00000011)
|
||||
#define RTC_BKP_DR18 ((uint32_t)0x00000012)
|
||||
#define RTC_BKP_DR19 ((uint32_t)0x00000013)
|
||||
#define RTC_BKP_DR20 ((uint32_t)0x00000014)
|
||||
#define RTC_BKP_DR21 ((uint32_t)0x00000015)
|
||||
#define RTC_BKP_DR22 ((uint32_t)0x00000016)
|
||||
#define RTC_BKP_DR23 ((uint32_t)0x00000017)
|
||||
#define RTC_BKP_DR24 ((uint32_t)0x00000018)
|
||||
#define RTC_BKP_DR25 ((uint32_t)0x00000019)
|
||||
#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
|
||||
#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
|
||||
#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
|
||||
#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
|
||||
#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
|
||||
#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
|
||||
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
|
||||
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
|
||||
#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
|
||||
#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
|
||||
|
||||
#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \
|
||||
((TAMPER) == RTC_TAMPER_2) || \
|
||||
((TAMPER) == RTC_TAMPER_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_TimeStamp_Pin_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Trigger_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
|
||||
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
|
||||
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
|
||||
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
|
||||
|
||||
#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
|
||||
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
|
||||
((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
|
||||
((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Filter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
|
||||
|
||||
#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
|
||||
consecutive samples at the active level. */
|
||||
|
||||
#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
|
||||
((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
|
||||
((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
|
||||
((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
|
||||
#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
|
||||
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
|
||||
#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
|
||||
((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
|
||||
((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
|
||||
((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
|
||||
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
|
||||
|
||||
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
|
||||
((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pull_UP_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
|
||||
#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
|
||||
|
||||
#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
|
||||
((STATE) == RTC_TAMPER_PULLUP_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Wakeup_Timer_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
|
||||
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
|
||||
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
|
||||
|
||||
#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
|
||||
|
||||
#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
|
||||
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
|
||||
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0]
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0] */
|
||||
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
|
||||
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
|
||||
#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
|
||||
((SEL) == RTC_SHIFTADD1S_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
|
||||
#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
|
||||
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
|
||||
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC WakeUp Timer peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC WakeUp Timer peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC calibration output.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
|
||||
|
||||
/**
|
||||
* @brief Disable the calibration output.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
|
||||
|
||||
/**
|
||||
* @brief Enable the clock reference detection.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
|
||||
|
||||
/**
|
||||
* @brief Disable the clock reference detection.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC WakeUpTimer interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC WakeUpTimer interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC TimeStamp's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TSF
|
||||
* @arg RTC_FLAG_TSOVF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC WakeUpTimer's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_WUTF
|
||||
* @arg RTC_FLAG_WUTWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Tamper's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC shift operation's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_SHPF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Time Stamp's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Tamper's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Wake Up timer's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_WUTF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* RTC TimeStamp and Tamper functions *****************************************/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
|
||||
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
||||
/* RTC Wake-up functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
|
||||
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
||||
/* Extension Control functions ************************************************/
|
||||
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
|
||||
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Extension RTC features functions *******************************************/
|
||||
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_RTC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,531 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_sdadc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file contains all the functions prototypes for the SDADC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_SDADC_H
|
||||
#define __STM32F3xx_SDADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL SDADC States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SDADC_STATE_RESET = 0x00, /*!< SDADC not initialized */
|
||||
HAL_SDADC_STATE_READY = 0x01, /*!< SDADC initialized and ready for use */
|
||||
HAL_SDADC_STATE_CALIB = 0x02, /*!< SDADC calibration in progress */
|
||||
HAL_SDADC_STATE_REG = 0x03, /*!< SDADC regular conversion in progress */
|
||||
HAL_SDADC_STATE_INJ = 0x04, /*!< SDADC injected conversion in progress */
|
||||
HAL_SDADC_STATE_REG_INJ = 0x05, /*!< SDADC regular and injected conversions in progress */
|
||||
HAL_SDADC_STATE_ERROR = 0xFF, /*!< SDADC state error */
|
||||
}HAL_SDADC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SDADC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle.
|
||||
This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
|
||||
uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not.
|
||||
This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
|
||||
uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not.
|
||||
This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
|
||||
uint32_t ReferenceVoltage; /*!< Specifies the reference voltage.
|
||||
This parameter can be a value of @ref SDADC_Reference_Voltage */
|
||||
}SDADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SDADC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SDADC_TypeDef *Instance; /*!< SDADC registers base address */
|
||||
SDADC_InitTypeDef Init; /*!< SDADC init parameters */
|
||||
DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */
|
||||
uint32_t RegularContMode; /*!< Regular conversion continuous mode */
|
||||
uint32_t InjectedContMode; /*!< Injected conversion continuous mode */
|
||||
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
|
||||
uint32_t InjConvRemaining; /*!< Injected conversion remaining */
|
||||
uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */
|
||||
uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */
|
||||
uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
|
||||
uint32_t RegularMultimode; /*!< current type of regular multimode */
|
||||
uint32_t InjectedMultimode; /*!< Current type of injected multimode */
|
||||
HAL_SDADC_StateTypeDef State; /*!< SDADC state */
|
||||
uint32_t ErrorCode; /*!< SDADC Error code */
|
||||
}SDADC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SDADC Configuration Register Parameter Structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...)
|
||||
This parameter can be any value of @ref SDADC_InputMode */
|
||||
uint32_t Gain; /*!< Specifies the gain setting.
|
||||
This parameter can be any value of @ref SDADC_Gain */
|
||||
uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2).
|
||||
This parameter can be any value of @ref SDADC_CommonMode */
|
||||
uint32_t Offset; /*!< Specifies the 12-bit offset value.
|
||||
This parameter can be any value lower or equal to 0x00000FFF */
|
||||
}SDADC_ConfParamTypeDef;
|
||||
|
||||
/** @defgroup SDADC_Idle_Low_Power_Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_LOWPOWER_NONE ((uint32_t)0x00000000)
|
||||
#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
|
||||
#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
|
||||
#define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \
|
||||
((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
|
||||
((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Fast_Conv_Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_FAST_CONV_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
|
||||
#define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \
|
||||
((FAST) == SDADC_FAST_CONV_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Slow_Clock_Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_SLOW_CLOCK_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
|
||||
#define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
|
||||
((MODE) == SDADC_SLOW_CLOCK_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Reference_Voltage
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_VREF_EXT ((uint32_t)0x00000000) /*!< The reference voltage is forced externally using VREF pin */
|
||||
#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
|
||||
#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
|
||||
#define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
|
||||
#define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \
|
||||
((VREF) == SDADC_VREF_VREFINT1) || \
|
||||
((VREF) == SDADC_VREF_VREFINT2) || \
|
||||
((VREF) == SDADC_VREF_VDDA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_ConfIndex
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDADC_CONF_INDEX_0 ((uint32_t)0x00000000) /*!< Configuration 0 Register selected */
|
||||
#define SDADC_CONF_INDEX_1 ((uint32_t)0x00000001) /*!< Configuration 1 Register selected */
|
||||
#define SDADC_CONF_INDEX_2 ((uint32_t)0x00000002) /*!< Configuration 2 Register selected */
|
||||
|
||||
#define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \
|
||||
((CONF) == SDADC_CONF_INDEX_1) || \
|
||||
((CONF) == SDADC_CONF_INDEX_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_InputMode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_INPUT_MODE_DIFF ((uint32_t)0x00000000) /*!< Conversions are executed in differential mode */
|
||||
#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
|
||||
#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
|
||||
|
||||
#define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \
|
||||
((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
|
||||
((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Gain
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_GAIN_1 ((uint32_t)0x00000000) /*!< Gain equal to 1 */
|
||||
#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2 */
|
||||
#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4 */
|
||||
#define SDADC_GAIN_8 ((uint32_t)0x00300000) /*!< Gain equal to 8 */
|
||||
#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16 */
|
||||
#define SDADC_GAIN_32 ((uint32_t)0x00500000) /*!< Gain equal to 32 */
|
||||
#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1/2 */
|
||||
#define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \
|
||||
((GAIN) == SDADC_GAIN_2) || \
|
||||
((GAIN) == SDADC_GAIN_4) || \
|
||||
((GAIN) == SDADC_GAIN_8) || \
|
||||
((GAIN) == SDADC_GAIN_16) || \
|
||||
((GAIN) == SDADC_GAIN_32) || \
|
||||
((GAIN) == SDADC_GAIN_1_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_CommonMode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_COMMON_MODE_VSSA ((uint32_t)0x00000000) /*!< Select SDADC VSSA as common mode */
|
||||
#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
|
||||
#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
|
||||
#define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \
|
||||
((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
|
||||
((MODE) == SDADC_COMMON_MODE_VDDA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Offset
|
||||
* @{
|
||||
*/
|
||||
#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Channel_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SDADC Channels ------------------------------------------------------------*/
|
||||
/* The SDADC channels are defined as follows:
|
||||
- in 16-bit LSB the channel mask is set
|
||||
- in 16-bit MSB the channel number is set
|
||||
e.g. for channel 5 definition:
|
||||
- the channel mask is 0x00000020 (bit 5 is set)
|
||||
- the channel number 5 is 0x00050000
|
||||
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
|
||||
#define SDADC_CHANNEL_0 ((uint32_t)0x00000001)
|
||||
#define SDADC_CHANNEL_1 ((uint32_t)0x00010002)
|
||||
#define SDADC_CHANNEL_2 ((uint32_t)0x00020004)
|
||||
#define SDADC_CHANNEL_3 ((uint32_t)0x00030008)
|
||||
#define SDADC_CHANNEL_4 ((uint32_t)0x00040010)
|
||||
#define SDADC_CHANNEL_5 ((uint32_t)0x00050020)
|
||||
#define SDADC_CHANNEL_6 ((uint32_t)0x00060040)
|
||||
#define SDADC_CHANNEL_7 ((uint32_t)0x00070080)
|
||||
#define SDADC_CHANNEL_8 ((uint32_t)0x00080100)
|
||||
|
||||
/* Just one channel of the 9 channels can be selected for regular conversion */
|
||||
#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_1) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_2) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_3) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_4) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_5) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_6) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_7) || \
|
||||
((CHANNEL) == SDADC_CHANNEL_8))
|
||||
|
||||
/* Any or all of the 9 channels can be selected for injected conversion */
|
||||
#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_CalibrationSequence
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_CALIBRATION_SEQ_1 ((uint32_t)0x00000000) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
|
||||
#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
|
||||
#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
|
||||
|
||||
#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
|
||||
((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \
|
||||
((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_ContinuousMode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */
|
||||
#define SDADC_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */
|
||||
|
||||
#define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \
|
||||
((MODE) == SDADC_CONTINUOUS_CONV_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_Trigger
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_SOFTWARE_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */
|
||||
#define SDADC_SYNCHRONOUS_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
|
||||
#define SDADC_EXTERNAL_TRIGGER ((uint32_t)0x00000002) /*!< External trigger */
|
||||
|
||||
#define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
|
||||
((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
|
||||
|
||||
#define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
|
||||
((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \
|
||||
((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_InjectedExtTrigger
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_EXT_TRIG_TIM13_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC1 */
|
||||
#define SDADC_EXT_TRIG_TIM14_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC1 */
|
||||
#define SDADC_EXT_TRIG_TIM16_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC3 */
|
||||
#define SDADC_EXT_TRIG_TIM17_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC2 */
|
||||
#define SDADC_EXT_TRIG_TIM12_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC2 */
|
||||
#define SDADC_EXT_TRIG_TIM12_CC2 ((uint32_t)0x00000100) /*!< Trigger source for SDADC3 */
|
||||
#define SDADC_EXT_TRIG_TIM15_CC2 ((uint32_t)0x00000200) /*!< Trigger source for SDADC1 */
|
||||
#define SDADC_EXT_TRIG_TIM2_CC3 ((uint32_t)0x00000200) /*!< Trigger source for SDADC2 */
|
||||
#define SDADC_EXT_TRIG_TIM2_CC4 ((uint32_t)0x00000200) /*!< Trigger source for SDADC3 */
|
||||
#define SDADC_EXT_TRIG_TIM3_CC1 ((uint32_t)0x00000300) /*!< Trigger source for SDADC1 */
|
||||
#define SDADC_EXT_TRIG_TIM3_CC2 ((uint32_t)0x00000300) /*!< Trigger source for SDADC2 */
|
||||
#define SDADC_EXT_TRIG_TIM3_CC3 ((uint32_t)0x00000300) /*!< Trigger source for SDADC3 */
|
||||
#define SDADC_EXT_TRIG_TIM4_CC1 ((uint32_t)0x00000400) /*!< Trigger source for SDADC1 */
|
||||
#define SDADC_EXT_TRIG_TIM4_CC2 ((uint32_t)0x00000400) /*!< Trigger source for SDADC2 */
|
||||
#define SDADC_EXT_TRIG_TIM4_CC3 ((uint32_t)0x00000400) /*!< Trigger source for SDADC3 */
|
||||
#define SDADC_EXT_TRIG_TIM19_CC2 ((uint32_t)0x00000500) /*!< Trigger source for SDADC1 */
|
||||
#define SDADC_EXT_TRIG_TIM19_CC3 ((uint32_t)0x00000500) /*!< Trigger source for SDADC2 */
|
||||
#define SDADC_EXT_TRIG_TIM19_CC4 ((uint32_t)0x00000500) /*!< Trigger source for SDADC3 */
|
||||
#define SDADC_EXT_TRIG_EXTI11 ((uint32_t)0x00000700) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
|
||||
#define SDADC_EXT_TRIG_EXTI15 ((uint32_t)0x00000600) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
|
||||
|
||||
#define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
|
||||
((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_ExtTriggerEdge
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */
|
||||
#define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */
|
||||
#define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */
|
||||
|
||||
#define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \
|
||||
((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \
|
||||
((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_InjectedDelay
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_INJECTED_DELAY_NONE ((uint32_t)0x00000000) /*!< No delay on injected conversion */
|
||||
#define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
|
||||
|
||||
#define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
|
||||
((DELAY) == SDADC_INJECTED_DELAY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_MultimodeType
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_MULTIMODE_SDADC1_SDADC2 ((uint32_t)0x00000000) /*!< Get conversion values for SDADC1 and SDADC2 */
|
||||
#define SDADC_MULTIMODE_SDADC1_SDADC3 ((uint32_t)0x00000001) /*!< Get conversion values for SDADC1 and SDADC3 */
|
||||
|
||||
#define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
|
||||
((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDADC_ErrorCode
|
||||
* @{
|
||||
*/
|
||||
#define SDADC_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
||||
#define SDADC_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
|
||||
#define SDADC_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
|
||||
#define SDADC_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset SDADC handle state
|
||||
* @param __HANDLE__: SDADC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
|
||||
void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
|
||||
void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
|
||||
uint32_t ConfIndex,
|
||||
SDADC_ConfParamTypeDef* ConfParamStruct);
|
||||
HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
|
||||
uint32_t Channel,
|
||||
uint32_t ConfIndex);
|
||||
HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
|
||||
uint32_t Channel,
|
||||
uint32_t ContinuousMode);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
|
||||
uint32_t Channel,
|
||||
uint32_t ContinuousMode);
|
||||
HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
|
||||
uint32_t InjectedExtTrigger,
|
||||
uint32_t ExtTriggerEdge);
|
||||
HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
|
||||
uint32_t InjectedDelay);
|
||||
HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
|
||||
HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
|
||||
HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
|
||||
HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
|
||||
|
||||
HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
|
||||
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
|
||||
|
||||
HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
|
||||
|
||||
uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
|
||||
uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
|
||||
uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
|
||||
uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
|
||||
|
||||
void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
|
||||
|
||||
HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
|
||||
|
||||
void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
|
||||
void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
|
||||
void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
|
||||
void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
|
||||
void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
|
||||
void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
|
||||
uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F3xx_SDADC_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,782 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_SMARTCARD_H
|
||||
#define __STM32F3xx_HAL_SMARTCARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief SMARTCARD Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
|
||||
Only 1.5 stop bits are authorized in SmartCard mode. */
|
||||
|
||||
uint16_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Parity
|
||||
@note The parity is enabled by default (PCE is forced to 1).
|
||||
Since the WordLength is forced to 8 bits + parity, M is
|
||||
forced to 1 and the parity bit is the 9th bit. */
|
||||
|
||||
uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Mode */
|
||||
|
||||
uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
|
||||
|
||||
uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
|
||||
|
||||
uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||
|
||||
uint16_t OneBitSampling; /*!< Specifies wether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */
|
||||
|
||||
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */
|
||||
|
||||
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
|
||||
in case of parity error.
|
||||
This parameter can be a value of @ref SMARTCARD_NACK_Enable */
|
||||
|
||||
uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
|
||||
|
||||
uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
|
||||
it is used to implement the Character Wait Time (CWT) and
|
||||
Block Wait Time (BWT). It is coded over 24 bits. */
|
||||
|
||||
uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
|
||||
This parameter can be any value from 0x0 to 0xFF */
|
||||
|
||||
uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
|
||||
receive and transmit mode). When set to 0, retransmission is
|
||||
disabled. Otherwise, its maximum value is 7 (before signalling
|
||||
an error) */
|
||||
|
||||
}SMARTCARD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD advanced features initalization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
|
||||
advanced features may be initialized at the same time. This parameter
|
||||
can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
|
||||
|
||||
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
|
||||
This parameter can be a value of @ref SMARTCARD_Tx_Inv */
|
||||
|
||||
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
|
||||
This parameter can be a value of @ref SMARTCARD_Rx_Inv */
|
||||
|
||||
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
|
||||
vs negative/inverted logic).
|
||||
This parameter can be a value of @ref SMARTCARD_Data_Inv */
|
||||
|
||||
uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
|
||||
This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
|
||||
|
||||
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
|
||||
|
||||
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
|
||||
This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
|
||||
|
||||
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
|
||||
This parameter can be a value of @ref SMARTCARD_MSB_First */
|
||||
}SMARTCARD_AdvFeatureInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
|
||||
HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
|
||||
HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
|
||||
}HAL_SMARTCARD_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
|
||||
HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
|
||||
HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
|
||||
HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
|
||||
HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */
|
||||
HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */
|
||||
}HAL_SMARTCARD_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /* USART registers base address */
|
||||
|
||||
SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
|
||||
|
||||
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /* SmartCard advanced features initialization parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* SmartCard Tx Transfer size */
|
||||
|
||||
uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* SmartCard Rx Transfer size */
|
||||
|
||||
uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
|
||||
|
||||
HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */
|
||||
|
||||
}SMARTCARD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD clock sources
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
|
||||
SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
|
||||
SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
|
||||
SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
|
||||
SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
|
||||
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
|
||||
}SMARTCARD_ClockSourceTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
|
||||
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
|
||||
#define IS_SMARTCARD_STOPBITS(STOPBITS) ((STOPBITS) == SMARTCARD_STOPBITS_1_5)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
|
||||
#define SMARTCARD_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
|
||||
((PARITY) == SMARTCARD_PARITY_ODD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_MODE_RX ((uint16_t)USART_CR1_RE)
|
||||
#define SMARTCARD_MODE_TX ((uint16_t)USART_CR1_TE)
|
||||
#define SMARTCARD_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_POLARITY_LOW ((uint16_t)0x0000)
|
||||
#define SMARTCARD_POLARITY_HIGH ((uint16_t)USART_CR2_CPOL)
|
||||
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PHASE_1EDGE ((uint16_t)0x0000)
|
||||
#define SMARTCARD_PHASE_2EDGE ((uint16_t)USART_CR2_CPHA)
|
||||
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_LASTBIT_DISABLED ((uint16_t)0x0000)
|
||||
#define SMARTCARD_LASTBIT_ENABLED ((uint16_t)USART_CR2_LBCL)
|
||||
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLED) || \
|
||||
((LASTBIT) == SMARTCARD_LASTBIT_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_DISABLED ((uint16_t)0x0000)
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED ((uint16_t)USART_CR3_ONEBIT)
|
||||
#define IS_SMARTCARD_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_DISABLED) || \
|
||||
((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_NACK_ENABLED ((uint16_t)USART_CR3_NACK)
|
||||
#define SMARTCARD_NACK_DISABLED ((uint16_t)0x0000)
|
||||
#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
|
||||
((NACK) == SMARTCARD_NACK_DISABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_TIMEOUT_DISABLED ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_TIMEOUT_ENABLED ((uint32_t)USART_CR2_RTOEN)
|
||||
#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLED) || \
|
||||
((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
|
||||
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
|
||||
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
|
||||
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
|
||||
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
|
||||
#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
|
||||
SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
|
||||
SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
|
||||
SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
|
||||
SMARTCARD_ADVFEATURE_SWAP_INIT | \
|
||||
SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
|
||||
SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
|
||||
SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
|
||||
#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
|
||||
((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
|
||||
#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
|
||||
((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
|
||||
#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
|
||||
((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
|
||||
#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
|
||||
((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
|
||||
#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
|
||||
((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
|
||||
#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
|
||||
((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
|
||||
#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
|
||||
((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SmartCard_Flags SMARTCARD Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
|
||||
#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
|
||||
#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
|
||||
#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
|
||||
#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
|
||||
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
|
||||
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
|
||||
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
|
||||
#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
|
||||
#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
|
||||
#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
|
||||
#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMARTCARD_IT_PE ((uint16_t)0x0028)
|
||||
#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
|
||||
#define SMARTCARD_IT_TC ((uint16_t)0x0626)
|
||||
#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
|
||||
|
||||
#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
|
||||
#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
|
||||
#define SMARTCARD_IT_NE ((uint16_t)0x0200)
|
||||
#define SMARTCARD_IT_FE ((uint16_t)0x0100)
|
||||
|
||||
#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
|
||||
#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
|
||||
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
|
||||
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
||||
#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
||||
#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
|
||||
((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_IT_MASK ((uint16_t)0x001F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMARTCARD handle state
|
||||
* @param __HANDLE__: SMARTCARD handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
|
||||
|
||||
/** @brief Checks whether the specified Smartcard flag is set or not.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_FLAG_REACK: Receive enable ackowledge flag
|
||||
* @arg SMARTCARD_FLAG_TEACK: Transmit enable ackowledge flag
|
||||
* @arg SMARTCARD_FLAG_BUSY: Busy flag
|
||||
* @arg SMARTCARD_FLAG_EOBF: End of block flag
|
||||
* @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
|
||||
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
|
||||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg SMARTCARD_FLAG_ORE: OverRun Error flag
|
||||
* @arg SMARTCARD_FLAG_NE: Noise Error flag
|
||||
* @arg SMARTCARD_FLAG_FE: Framing Error flag
|
||||
* @arg SMARTCARD_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enables the specified SmartCard interrupt.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Disables the specified SmartCard interrupt.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __IT__: specifies the SMARTCARD interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_ORE: OverRun Error interrupt
|
||||
* @arg SMARTCARD_IT_NE: Noise Error interrupt
|
||||
* @arg SMARTCARD_IT_FE: Framing Error interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __IT__: specifies the SMARTCARD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_ORE: OverRun Error interrupt
|
||||
* @arg SMARTCARD_IT_NE: Noise Error interrupt
|
||||
* @arg SMARTCARD_IT_FE: Framing Error interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
|
||||
|
||||
|
||||
/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_CLEAR_PEF: Parity Error Clear Flag
|
||||
* @arg USART_CLEAR_FEF: Framing Error Clear Flag
|
||||
* @arg USART_CLEAR_NEF: Noise detected Clear Flag
|
||||
* @arg USART_CLEAR_OREF: OverRun Error Clear Flag
|
||||
* @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
|
||||
* @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
|
||||
* @arg USART_CLEAR_EOBF: End Of Block Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
/** @brief Set a specific SMARTCARD request flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
|
||||
* @param __REQ__: specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
|
||||
* @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the
|
||||
* maximum clock on F3 (i.e. 72 MHz) divided by the oversampling used
|
||||
* on the SMARTCARD (i.e. 16)
|
||||
* @param __BAUDRATE__: Baud rate set by the configuration function.
|
||||
* @retval Test result (TRUE or FALSE)
|
||||
*/
|
||||
#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
|
||||
|
||||
/** @brief Check the block length range. The maximum SMARTCARD block length is 0xFF.
|
||||
* @param __LENGTH__: block length.
|
||||
* @retval Test result (TRUE or FALSE)
|
||||
*/
|
||||
#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
|
||||
|
||||
/** @brief Check the receiver timeout value. The maximum SMARTCARD receiver timeout
|
||||
* value is 0xFFFFFF.
|
||||
* @param __TIMEOUTVALUE__: receiver timeout value.
|
||||
* @retval Test result (TRUE or FALSE)
|
||||
*/
|
||||
#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
|
||||
|
||||
/** @brief Check the SMARTCARD autoretry counter value. The maximum number of
|
||||
* retransmissions is 0x7.
|
||||
* @param __COUNT__: number of retransmissions
|
||||
* @retval Test result (TRUE or FALSE)
|
||||
*/
|
||||
#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include SMARTCARD HAL Extension module */
|
||||
#include "stm32f3xx_hal_smartcard_ex.h"
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_SMARTCARD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief SMARTCARD HAL module driver.
|
||||
*
|
||||
* This file provides extended firmware functions to manage the following
|
||||
* functionalities of the SmartCard.
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
The Extended SMARTCARD HAL driver can be used as follows:
|
||||
|
||||
|
||||
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
|
||||
then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
|
||||
auto-retry counter,...) in the hsmartcard AdvancedInit structure.
|
||||
|
||||
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx
|
||||
* @brief SMARTCARD Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the SMARTCARD.
|
||||
(+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
|
||||
(+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
|
||||
(+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
|
||||
(+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update on the fly the SMARTCARD block length in RTOR register
|
||||
* @param hsmartcard: SMARTCARD handle
|
||||
* @param BlockLength: SMARTCARD block length (8-bit long at most)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
|
||||
{
|
||||
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update on the fly the receiver timeout value in RTOR register
|
||||
* @param hsmartcard: SMARTCARD handle
|
||||
* @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
|
||||
* value must be less or equal to 0x0FFFFFFFF.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
|
||||
{
|
||||
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
|
||||
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the SMARTCARD receiver timeout feature
|
||||
* @param hsmartcard: SMARTCARD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsmartcard);
|
||||
|
||||
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
|
||||
|
||||
/* Set the USART RTOEN bit */
|
||||
hsmartcard->Instance->CR2 |= USART_CR2_RTOEN;
|
||||
|
||||
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsmartcard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SMARTCARD receiver timeout feature
|
||||
* @param hsmartcard: SMARTCARD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsmartcard);
|
||||
|
||||
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
|
||||
|
||||
/* Clear the USART RTOEN bit */
|
||||
hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN);
|
||||
|
||||
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsmartcard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smartcard_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_SMARTCARD_EX_H
|
||||
#define __STM32F3xx_HAL_SMARTCARD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARDEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reports the SMARTCARD clock source.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle
|
||||
* @param __CLOCKSOURCE__ : output variable
|
||||
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32F334x8) || defined(STM32F303x8) || defined(STM32F328xx)
|
||||
#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
|
||||
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_SMARTCARD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,573 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_smbus.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of SMBUS HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_SMBUS_H
|
||||
#define __STM32F3xx_HAL_SMBUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SMBUS Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
||||
This parameter can be a a value of @ref SMBUS_Analog_Filter */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
||||
|
||||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
||||
|
||||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
||||
|
||||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
|
||||
(Enable bits and different timeout values)
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
} SMBUS_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */
|
||||
HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */
|
||||
HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */
|
||||
HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
|
||||
HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
|
||||
HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
|
||||
HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
|
||||
HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */
|
||||
HAL_SMBUS_STATE_SLAVE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */
|
||||
/* Aliases for inter STM32 series compatibility */
|
||||
HAL_SMBUS_STATE_LISTEN = HAL_SMBUS_STATE_SLAVE_LISTEN
|
||||
}HAL_SMBUS_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMBUS Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */
|
||||
HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */
|
||||
HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */
|
||||
HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */
|
||||
HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */
|
||||
HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */
|
||||
HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */
|
||||
HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */
|
||||
|
||||
}HAL_SMBUS_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMBUS handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
||||
|
||||
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SMBUS transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
|
||||
|
||||
__IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
|
||||
|
||||
__IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
|
||||
|
||||
__IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */
|
||||
|
||||
}SMBUS_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
|
||||
#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
|
||||
#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_dual_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
|
||||
#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
|
||||
|
||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_own_address2_masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_OA2_NOMASK ((uint8_t)0x00)
|
||||
#define SMBUS_OA2_MASK01 ((uint8_t)0x01)
|
||||
#define SMBUS_OA2_MASK02 ((uint8_t)0x02)
|
||||
#define SMBUS_OA2_MASK03 ((uint8_t)0x03)
|
||||
#define SMBUS_OA2_MASK04 ((uint8_t)0x04)
|
||||
#define SMBUS_OA2_MASK05 ((uint8_t)0x05)
|
||||
#define SMBUS_OA2_MASK06 ((uint8_t)0x06)
|
||||
#define SMBUS_OA2_MASK07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
||||
((MASK) == SMBUS_OA2_MASK01) || \
|
||||
((MASK) == SMBUS_OA2_MASK02) || \
|
||||
((MASK) == SMBUS_OA2_MASK03) || \
|
||||
((MASK) == SMBUS_OA2_MASK04) || \
|
||||
((MASK) == SMBUS_OA2_MASK05) || \
|
||||
((MASK) == SMBUS_OA2_MASK06) || \
|
||||
((MASK) == SMBUS_OA2_MASK07))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMBUS_general_call_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000)
|
||||
#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN
|
||||
|
||||
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
|
||||
((CALL) == SMBUS_GENERALCALL_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_nostretch_mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
|
||||
#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
|
||||
|
||||
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
|
||||
((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_packet_error_check_mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000)
|
||||
#define SMBUS_PEC_ENABLED I2C_CR1_PECEN
|
||||
|
||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \
|
||||
((PEC) == SMBUS_PEC_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_peripheral_mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
|
||||
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
|
||||
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
|
||||
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
|
||||
#define SMBUS_GENERATE_STOP I2C_CR2_STOP
|
||||
#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
|
||||
|
||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_XferOptions_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Interrupt_configuration_definition
|
||||
* @brief SMBUS Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
|
||||
#define SMBUS_IT_TCI I2C_CR1_TCIE
|
||||
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
|
||||
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
|
||||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Flag_definition
|
||||
* @brief Flag definition
|
||||
* Elements values convention: 0xXXXXYYYY
|
||||
* - XXXXXXXX : Flag mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_FLAG_TXE I2C_ISR_TXE
|
||||
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define SMBUS_FLAG_AF I2C_ISR_NACKF
|
||||
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define SMBUS_FLAG_TC I2C_ISR_TC
|
||||
#define SMBUS_FLAG_TCR I2C_ISR_TCR
|
||||
#define SMBUS_FLAG_BERR I2C_ISR_BERR
|
||||
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define SMBUS_FLAG_OVR I2C_ISR_OVR
|
||||
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define SMBUS_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMBUS handle state
|
||||
* @param __HANDLE__: SMBUS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__: specifies the SMBUS Handle.
|
||||
* This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMBUS_IT_ERRI: Errors interrupt enable
|
||||
* @arg SMBUS_IT_TCI: Transfer complete interrupt enable
|
||||
* @arg SMBUS_IT_STOPI: STOP detection interrupt enable
|
||||
* @arg SMBUS_IT_NACKI: NACK received interrupt enable
|
||||
* @arg SMBUS_IT_ADDRI: Address match interrupt enable
|
||||
* @arg SMBUS_IT_RXI: RX interrupt enable
|
||||
* @arg SMBUS_IT_TXI: TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the SMBUS Handle.
|
||||
* This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
|
||||
* @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMBUS_IT_ERRI: Errors interrupt enable
|
||||
* @arg SMBUS_IT_TCI: Transfer complete interrupt enable
|
||||
* @arg SMBUS_IT_STOPI: STOP detection interrupt enable
|
||||
* @arg SMBUS_IT_NACKI: NACK received interrupt enable
|
||||
* @arg SMBUS_IT_ADDRI: Address match interrupt enable
|
||||
* @arg SMBUS_IT_RXI: RX interrupt enable
|
||||
* @arg SMBUS_IT_TXI: TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified SMBUS flag is set or not.
|
||||
* @param __HANDLE__: specifies the SMBUS Handle.
|
||||
* This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMBUS_FLAG_TXE: Transmit data register empty
|
||||
* @arg SMBUS_FLAG_TXIS: Transmit interrupt status
|
||||
* @arg SMBUS_FLAG_RXNE: Receive data register not empty
|
||||
* @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
|
||||
* @arg SMBUS_FLAG_AF: NACK received flag
|
||||
* @arg SMBUS_FLAG_STOPF: STOP detection flag
|
||||
* @arg SMBUS_FLAG_TC: Transfer complete (master mode)
|
||||
* @arg SMBUS_FLAG_TCR: Transfer complete reload
|
||||
* @arg SMBUS_FLAG_BERR: Bus error
|
||||
* @arg SMBUS_FLAG_ARLO: Arbitration lost
|
||||
* @arg SMBUS_FLAG_OVR: Overrun/Underrun
|
||||
* @arg SMBUS_FLAG_PECERR: PEC error in reception
|
||||
* @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
|
||||
* @arg SMBUS_FLAG_ALERT: SMBus alert
|
||||
* @arg SMBUS_FLAG_BUSY: Bus busy
|
||||
* @arg SMBUS_FLAG_DIR: Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
|
||||
|
||||
/** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__: specifies the SMBUS Handle.
|
||||
* This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
|
||||
* @arg SMBUS_FLAG_AF: NACK received flag
|
||||
* @arg SMBUS_FLAG_STOPF: STOP detection flag
|
||||
* @arg SMBUS_FLAG_BERR: Bus error
|
||||
* @arg SMBUS_FLAG_ARLO: Arbitration lost
|
||||
* @arg SMBUS_FLAG_OVR: Overrun/Underrun
|
||||
* @arg SMBUS_FLAG_PECERR: PEC error in reception
|
||||
* @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
|
||||
* @arg SMBUS_FLAG_ALERT: SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
|
||||
#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
|
||||
#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
|
||||
|
||||
#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
|
||||
#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
|
||||
#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
|
||||
#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
||||
#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
||||
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
/* Aliases for new API and to insure inter STM32 series compatibility */
|
||||
#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT
|
||||
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
|
||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
/* Aliases for new API and to insure inter STM32 series compatibility */
|
||||
#define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback
|
||||
#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback
|
||||
|
||||
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_SMBUS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,639 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_SPI_H
|
||||
#define __STM32F3xx_HAL_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
|
||||
This parameter can be a value of @ref SPI_TI_mode */
|
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
|
||||
|
||||
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
|
||||
CRC Length is only used with Data8 and Data16, not other data size
|
||||
This parameter must 0 or 1 or 2*/
|
||||
|
||||
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
|
||||
This mode is activated by the NSSP bit in the SPIx_CR2 register and
|
||||
it takes effect only if the SPI interface is configured as Motorola SPI
|
||||
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
|
||||
CPOL setting is ignored).. */
|
||||
} SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
|
||||
HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_SPI_STATE_TIMEOUT = 0x06, /*!< Timeout state */
|
||||
HAL_SPI_STATE_ERROR = 0x07 /*!< Data Transmission and Reception process is ongoing */
|
||||
|
||||
}HAL_SPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
|
||||
HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
|
||||
HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
|
||||
HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
|
||||
HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
|
||||
HAL_SPI_ERROR_FLAG = 0x20, /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
|
||||
HAL_SPI_ERROR_UNKNOW = 0x40, /*!< Unknow Error error */
|
||||
}HAL_SPI_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /* SPI registers base address */
|
||||
|
||||
SPI_InitTypeDef Init; /* SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* SPI Tx Transfer size */
|
||||
|
||||
uint16_t TxXferCount; /* SPI Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* SPI Rx Transfer size */
|
||||
|
||||
uint16_t RxXferCount; /* SPI Rx Transfer Counter */
|
||||
|
||||
uint32_t CRCSize; /* SPI CRC size used for the transfer */
|
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
|
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
HAL_SPI_StateTypeDef State; /* SPI communication state */
|
||||
|
||||
HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
|
||||
|
||||
}SPI_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
|
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
|
||||
((MODE) == SPI_MODE_MASTER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
|
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
||||
|
||||
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||
((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
|
||||
((MODE) == SPI_DIRECTION_1LINE))
|
||||
|
||||
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
|
||||
|
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
|
||||
((MODE) == SPI_DIRECTION_1LINE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DATASIZE_4BIT ((uint16_t)0x0300)
|
||||
#define SPI_DATASIZE_5BIT ((uint16_t)0x0400)
|
||||
#define SPI_DATASIZE_6BIT ((uint16_t)0x0500)
|
||||
#define SPI_DATASIZE_7BIT ((uint16_t)0x0600)
|
||||
#define SPI_DATASIZE_8BIT ((uint16_t)0x0700)
|
||||
#define SPI_DATASIZE_9BIT ((uint16_t)0x0800)
|
||||
#define SPI_DATASIZE_10BIT ((uint16_t)0x0900)
|
||||
#define SPI_DATASIZE_11BIT ((uint16_t)0x0A00)
|
||||
#define SPI_DATASIZE_12BIT ((uint16_t)0x0B00)
|
||||
#define SPI_DATASIZE_13BIT ((uint16_t)0x0C00)
|
||||
#define SPI_DATASIZE_14BIT ((uint16_t)0x0D00)
|
||||
#define SPI_DATASIZE_15BIT ((uint16_t)0x0E00)
|
||||
#define SPI_DATASIZE_16BIT ((uint16_t)0x0F00)
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_15BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_14BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_13BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_12BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_11BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_10BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_9BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_8BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_7BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_6BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_5BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_4BIT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
|
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
|
||||
((CPOL) == SPI_POLARITY_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
|
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
|
||||
((CPHA) == SPI_PHASE_2EDGE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
||||
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
|
||||
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
|
||||
((NSS) == SPI_NSS_HARD_INPUT) || \
|
||||
((NSS) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_NSS pulse management
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
|
||||
#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \
|
||||
((NSSP) == SPI_NSS_PULSE_DISABLED))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
|
||||
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
|
||||
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
|
||||
#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
|
||||
#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
|
||||
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
|
||||
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
|
||||
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
|
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
|
||||
((BIT) == SPI_FIRSTBIT_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_TI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
|
||||
#define SPI_TIMODE_ENABLED SPI_CR2_FRF
|
||||
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
|
||||
((MODE) == SPI_TIMODE_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Calculation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
|
||||
#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
|
||||
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
|
||||
((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length
|
||||
* @{
|
||||
* This parameter can be one of the following values:
|
||||
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
|
||||
* SPI_CRC_LENGTH_8BIT : CRC 8bit
|
||||
* SPI_CRC_LENGTH_16BIT : CRC 16bit
|
||||
*/
|
||||
#define SPI_CRC_LENGTH_DATASIZE 0
|
||||
#define SPI_CRC_LENGTH_8BIT 1
|
||||
#define SPI_CRC_LENGTH_16BIT 2
|
||||
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
|
||||
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
|
||||
((LENGTH) == SPI_CRC_LENGTH_16BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold
|
||||
* @{
|
||||
* This parameter can be one of the following values:
|
||||
* SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
|
||||
* level is greater or equal to 1/2(16-bits).
|
||||
* SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
|
||||
* level is greater or equal to 1/4(8 bits).
|
||||
*/
|
||||
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
|
||||
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
|
||||
#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Interrupt_configuration_definition
|
||||
* @brief SPI Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
||||
#define IS_SPI_IT(IT) (((IT) == SPI_IT_TXE) || \
|
||||
((IT) == SPI_IT_RXNE) || \
|
||||
((IT) == SPI_IT_ERR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_Flag_definition
|
||||
* @brief Flag definition
|
||||
* Elements values convention: 0xXXXXYYYY
|
||||
* - XXXX : Flag register Index
|
||||
* - YYYY : Flag mask
|
||||
*/
|
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
||||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
||||
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
|
||||
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
|
||||
#define IS_SPI_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXNE) || \
|
||||
((FLAG) == SPI_FLAG_TXE) || \
|
||||
((FLAG) == SPI_FLAG_BSY) || \
|
||||
((FLAG) == SPI_FLAG_CRCERR)|| \
|
||||
((FLAG) == SPI_FLAG_MODF) || \
|
||||
((FLAG) == SPI_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_FTLVL) || \
|
||||
((FLAG) == SPI_FLAG_FRLVL) || \
|
||||
((FLAG) == SPI_IT_FRE))
|
||||
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FTLVL_EMPTY ((uint16_t)0x0000)
|
||||
#define SPI_FTLVL_QUARTER_FULL ((uint16_t)0x0800)
|
||||
#define SPI_FTLVL_HALF_FULL ((uint16_t)0x1000)
|
||||
#define SPI_FTLVL_FULL ((uint16_t)0x1800)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FRLVL_EMPTY ((uint16_t)0x0000)
|
||||
#define SPI_FRLVL_QUARTER_FULL ((uint16_t)0x0200)
|
||||
#define SPI_FRLVL_HALF_FULL ((uint16_t)0x0400)
|
||||
#define SPI_FRLVL_FULL ((uint16_t)0x0600)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset SPI handle state
|
||||
* @param __HANDLE__: SPI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
|
||||
/** @brief Enables or disables the specified SPI interrupts.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__: specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
|
||||
|
||||
/** @brief Clears the SPI MODF pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
|
||||
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
|
||||
|
||||
/** @brief Clears the SPI OVR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
|
||||
(__HANDLE__)->Instance->SR;}while(0)
|
||||
|
||||
/** @brief Clears the SPI FRE pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
|
||||
|
||||
/** @brief Enables the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
|
||||
|
||||
/** @brief Disables the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
|
||||
|
||||
/** @brief Sets the SPI transmit-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Sets the SPI receive-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Resets the CRC calculation of the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
|
||||
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
|
||||
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_SPI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,947 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of TIM HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_TIM_EX_H
|
||||
#define __STM32F3xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/**
|
||||
* @brief TIM Master configuration Structure definition
|
||||
* @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
|
||||
* output
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
|
||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */
|
||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
|
||||
This parameter can be a value of @ref TIM_Master_Slave_Mode */
|
||||
}TIM_MasterConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Break and Dead time configuration Structure definition
|
||||
* @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode
|
||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
|
||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
uint32_t LockLevel; /*!< TIM Lock level
|
||||
This parameter can be a value of @ref TIM_Lock_level */
|
||||
uint32_t DeadTime; /*!< TIM dead Time
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint32_t BreakState; /*!< TIM Break State
|
||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
uint32_t BreakPolarity; /*!< TIM Break input polarity
|
||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BreakDeadTimeConfigTypeDef;
|
||||
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
/**
|
||||
* @brief TIM Break input(s) and Dead time configuration Structure definition
|
||||
* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
|
||||
* filter and polarity.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode
|
||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
|
||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
uint32_t LockLevel; /*!< TIM Lock level
|
||||
This parameter can be a value of @ref TIM_Lock_level */
|
||||
uint32_t DeadTime; /*!< TIM dead Time
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint32_t BreakState; /*!< TIM Break State
|
||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
uint32_t BreakPolarity; /*!< TIM Break input polarity
|
||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
uint32_t BreakFilter; /*!< Specifies the brek input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t Break2State; /*!< TIM Break2 State
|
||||
This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
|
||||
uint32_t Break2Polarity; /*!< TIM Break2 input polarity
|
||||
This parameter can be a value of @ref TIMEx_Break2_Polarity */
|
||||
uint32_t Break2Filter; /*!< TIM break2 input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BreakDeadTimeConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Master configuration Structure definition
|
||||
* @note Advanced timers provide TRGO2 internal line which is redirected
|
||||
* to the ADC
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
|
||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */
|
||||
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
|
||||
This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
|
||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
|
||||
This parameter can be a value of @ref TIM_Master_Slave_Mode */
|
||||
}TIM_MasterConfigTypeDef;
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/** @defgroup TIMEx_Channel
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CHANNEL_1 ((uint32_t)0x0000)
|
||||
#define TIM_CHANNEL_2 ((uint32_t)0x0004)
|
||||
#define TIM_CHANNEL_3 ((uint32_t)0x0008)
|
||||
#define TIM_CHANNEL_4 ((uint32_t)0x000C)
|
||||
#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
|
||||
|
||||
#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4) || \
|
||||
((CHANNEL) == TIM_CHANNEL_ALL))
|
||||
|
||||
#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Output_Compare_and_PWM_modes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
|
||||
#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
|
||||
#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
|
||||
#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
|
||||
#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
|
||||
|
||||
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
|
||||
((MODE) == TIM_OCMODE_ACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_INACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_TOGGLE) || \
|
||||
((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_FORCED_INACTIVE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_ClearInput_Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
|
||||
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
|
||||
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
|
||||
((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
|
||||
#define TIM_SLAVEMODE_RESET ((uint16_t)0x0004)
|
||||
#define TIM_SLAVEMODE_GATED ((uint16_t)0x0005)
|
||||
#define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006)
|
||||
#define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007)
|
||||
|
||||
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
|
||||
((MODE) == TIM_SLAVEMODE_RESET) || \
|
||||
((MODE) == TIM_SLAVEMODE_GATED) || \
|
||||
((MODE) == TIM_SLAVEMODE_TRIGGER) || \
|
||||
((MODE) == TIM_SLAVEMODE_EXTERNAL1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Event_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
|
||||
#define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
|
||||
#define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
|
||||
#define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
|
||||
#define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
|
||||
#define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
|
||||
#define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
|
||||
#define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
|
||||
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_DMA_Base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_DMABase_CR1 (0x00000000)
|
||||
#define TIM_DMABase_CR2 (0x00000001)
|
||||
#define TIM_DMABase_SMCR (0x00000002)
|
||||
#define TIM_DMABase_DIER (0x00000003)
|
||||
#define TIM_DMABase_SR (0x00000004)
|
||||
#define TIM_DMABase_EGR (0x00000005)
|
||||
#define TIM_DMABase_CCMR1 (0x00000006)
|
||||
#define TIM_DMABase_CCMR2 (0x00000007)
|
||||
#define TIM_DMABase_CCER (0x00000008)
|
||||
#define TIM_DMABase_CNT (0x00000009)
|
||||
#define TIM_DMABase_PSC (0x0000000A)
|
||||
#define TIM_DMABase_ARR (0x0000000B)
|
||||
#define TIM_DMABase_RCR (0x0000000C)
|
||||
#define TIM_DMABase_CCR1 (0x0000000D)
|
||||
#define TIM_DMABase_CCR2 (0x0000000E)
|
||||
#define TIM_DMABase_CCR3 (0x0000000F)
|
||||
#define TIM_DMABase_CCR4 (0x00000010)
|
||||
#define TIM_DMABase_BDTR (0x00000011)
|
||||
#define TIM_DMABase_DCR (0x00000012)
|
||||
#define TIM_DMABase_OR (0x00000013)
|
||||
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
|
||||
((BASE) == TIM_DMABase_CR2) || \
|
||||
((BASE) == TIM_DMABase_SMCR) || \
|
||||
((BASE) == TIM_DMABase_DIER) || \
|
||||
((BASE) == TIM_DMABase_SR) || \
|
||||
((BASE) == TIM_DMABase_EGR) || \
|
||||
((BASE) == TIM_DMABase_CCMR1) || \
|
||||
((BASE) == TIM_DMABase_CCMR2) || \
|
||||
((BASE) == TIM_DMABase_CCER) || \
|
||||
((BASE) == TIM_DMABase_CNT) || \
|
||||
((BASE) == TIM_DMABase_PSC) || \
|
||||
((BASE) == TIM_DMABase_ARR) || \
|
||||
((BASE) == TIM_DMABase_RCR) || \
|
||||
((BASE) == TIM_DMABase_CCR1) || \
|
||||
((BASE) == TIM_DMABase_CCR2) || \
|
||||
((BASE) == TIM_DMABase_CCR3) || \
|
||||
((BASE) == TIM_DMABase_CCR4) || \
|
||||
((BASE) == TIM_DMABase_BDTR) || \
|
||||
((BASE) == TIM_DMABase_DCR) || \
|
||||
((BASE) == TIM_DMABase_OR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
/** @defgroup TIMEx_Channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CHANNEL_1 ((uint32_t)0x0000)
|
||||
#define TIM_CHANNEL_2 ((uint32_t)0x0004)
|
||||
#define TIM_CHANNEL_3 ((uint32_t)0x0008)
|
||||
#define TIM_CHANNEL_4 ((uint32_t)0x000C)
|
||||
#define TIM_CHANNEL_5 ((uint32_t)0x0010)
|
||||
#define TIM_CHANNEL_6 ((uint32_t)0x0014)
|
||||
#define TIM_CHANNEL_ALL ((uint32_t)0x003C)
|
||||
|
||||
#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4) || \
|
||||
((CHANNEL) == TIM_CHANNEL_5) || \
|
||||
((CHANNEL) == TIM_CHANNEL_6) || \
|
||||
((CHANNEL) == TIM_CHANNEL_ALL))
|
||||
|
||||
#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Output_Compare_and_PWM_modes
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
|
||||
#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
|
||||
#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
|
||||
#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
|
||||
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
|
||||
|
||||
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_PWM2) || \
|
||||
((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
|
||||
((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
|
||||
((MODE) == TIM_OCMODE_ACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_INACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_TOGGLE) || \
|
||||
((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
|
||||
((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_ClearInput_Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
|
||||
#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
|
||||
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
|
||||
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
|
||||
((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
|
||||
((MODE) == TIM_CLEARINPUTSOURCE_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_BreakInput_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break2_Input_enable_disable
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
|
||||
#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
|
||||
|
||||
#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
|
||||
((STATE) == TIM_BREAK2_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup TIMEx_Break2_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
|
||||
#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
|
||||
|
||||
#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
|
||||
((POLARITY) == TIM_BREAK2POLARITY_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Master_Mode_Selection_2
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TRGO2_RESET ((uint32_t)0x00000000)
|
||||
#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
|
||||
#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
|
||||
#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
|
||||
#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
|
||||
#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
|
||||
((SOURCE) == TIM_TRGO2_ENABLE) || \
|
||||
((SOURCE) == TIM_TRGO2_UPDATE) || \
|
||||
((SOURCE) == TIM_TRGO2_OC1) || \
|
||||
((SOURCE) == TIM_TRGO2_OC1REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC2REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC3REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC3REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC5REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC6REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
|
||||
#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
|
||||
#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
|
||||
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
|
||||
#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
|
||||
#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
|
||||
|
||||
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
|
||||
((MODE) == TIM_SLAVEMODE_RESET) || \
|
||||
((MODE) == TIM_SLAVEMODE_GATED) || \
|
||||
((MODE) == TIM_SLAVEMODE_TRIGGER) || \
|
||||
((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
|
||||
((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Event_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
|
||||
#define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
|
||||
#define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
|
||||
#define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
|
||||
#define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
|
||||
#define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
|
||||
#define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
|
||||
#define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
|
||||
#define TIM_EventSource_Break2 TIM_EGR_B2G /*!< A break 2 event is generated */
|
||||
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_Base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_DMABase_CR1 (0x00000000)
|
||||
#define TIM_DMABase_CR2 (0x00000001)
|
||||
#define TIM_DMABase_SMCR (0x00000002)
|
||||
#define TIM_DMABase_DIER (0x00000003)
|
||||
#define TIM_DMABase_SR (0x00000004)
|
||||
#define TIM_DMABase_EGR (0x00000005)
|
||||
#define TIM_DMABase_CCMR1 (0x00000006)
|
||||
#define TIM_DMABase_CCMR2 (0x00000007)
|
||||
#define TIM_DMABase_CCER (0x00000008)
|
||||
#define TIM_DMABase_CNT (0x00000009)
|
||||
#define TIM_DMABase_PSC (0x0000000A)
|
||||
#define TIM_DMABase_ARR (0x0000000B)
|
||||
#define TIM_DMABase_RCR (0x0000000C)
|
||||
#define TIM_DMABase_CCR1 (0x0000000D)
|
||||
#define TIM_DMABase_CCR2 (0x0000000E)
|
||||
#define TIM_DMABase_CCR3 (0x0000000F)
|
||||
#define TIM_DMABase_CCR4 (0x00000010)
|
||||
#define TIM_DMABase_BDTR (0x00000011)
|
||||
#define TIM_DMABase_DCR (0x00000012)
|
||||
#define TIM_DMABase_CCMR3 (0x00000015)
|
||||
#define TIM_DMABase_CCR5 (0x00000016)
|
||||
#define TIM_DMABase_CCR6 (0x00000017)
|
||||
#define TIM_DMABase_OR (0x00000018)
|
||||
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
|
||||
((BASE) == TIM_DMABase_CR2) || \
|
||||
((BASE) == TIM_DMABase_SMCR) || \
|
||||
((BASE) == TIM_DMABase_DIER) || \
|
||||
((BASE) == TIM_DMABase_SR) || \
|
||||
((BASE) == TIM_DMABase_EGR) || \
|
||||
((BASE) == TIM_DMABase_CCMR1) || \
|
||||
((BASE) == TIM_DMABase_CCMR2) || \
|
||||
((BASE) == TIM_DMABase_CCER) || \
|
||||
((BASE) == TIM_DMABase_CNT) || \
|
||||
((BASE) == TIM_DMABase_PSC) || \
|
||||
((BASE) == TIM_DMABase_ARR) || \
|
||||
((BASE) == TIM_DMABase_RCR) || \
|
||||
((BASE) == TIM_DMABase_CCR1) || \
|
||||
((BASE) == TIM_DMABase_CCR2) || \
|
||||
((BASE) == TIM_DMABase_CCR3) || \
|
||||
((BASE) == TIM_DMABase_CCR4) || \
|
||||
((BASE) == TIM_DMABase_BDTR) || \
|
||||
((BASE) == TIM_DMABase_CCMR3) || \
|
||||
((BASE) == TIM_DMABase_CCR5) || \
|
||||
((BASE) == TIM_DMABase_CCR6) || \
|
||||
((BASE) == TIM_DMABase_OR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined(STM32F302xC)
|
||||
/** @defgroup TIMEx_Remap
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
|
||||
#define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
|
||||
#define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
|
||||
#define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
|
||||
|
||||
#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
|
||||
((REMAP) == TIM_TIM16_GPIO) ||\
|
||||
((REMAP) == TIM_TIM16_RTC) ||\
|
||||
((REMAP) == TIM_TIM16_HSE) ||\
|
||||
((REMAP) == TIM_TIM16_MCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F302xC */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/** @defgroup TIMEx_Remap
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
|
||||
#define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
|
||||
#define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
|
||||
#define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
|
||||
#define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
|
||||
#define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
|
||||
#define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
|
||||
#define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
|
||||
|
||||
#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
|
||||
((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
|
||||
((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
|
||||
((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
|
||||
((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
|
||||
((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
|
||||
((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
|
||||
((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
|
||||
((REMAP1) == TIM_TIM16_GPIO) ||\
|
||||
((REMAP1) == TIM_TIM16_RTC) ||\
|
||||
((REMAP1) == TIM_TIM16_HSE) ||\
|
||||
((REMAP1) == TIM_TIM16_MCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap2
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
|
||||
#define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
|
||||
#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
|
||||
#define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
|
||||
#define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
|
||||
#define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
|
||||
#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
|
||||
#define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
|
||||
|
||||
#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
|
||||
((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
|
||||
((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
|
||||
((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
|
||||
((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
|
||||
((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
|
||||
((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
|
||||
((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
|
||||
((REMAP2) == TIM_TIM16_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/** @defgroup TIMEx_Remap
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
|
||||
#define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
|
||||
#define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
|
||||
#define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
|
||||
#define TIM_TIM14_GPIO (0x00000000) /* !< TIM14 TI1 is connected to GPIO */
|
||||
#define TIM_TIM14_RTC (0x00000001) /* !< TIM14 TI1 is connected to RTC_clock */
|
||||
#define TIM_TIM14_HSE (0x00000002) /* !< TIM14 TI1 is connected to HSE/32 */
|
||||
#define TIM_TIM14_MCO (0x00000003) /* !< TIM14 TI1 is connected to MCO */
|
||||
|
||||
#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
|
||||
((REMAP) == TIM_TIM2_ETH_PTP) ||\
|
||||
((REMAP) == TIM_TIM2_USBFS_SOF) ||\
|
||||
((REMAP) == TIM_TIM2_USBHS_SOF) ||\
|
||||
((REMAP) == TIM_TIM14_GPIO) ||\
|
||||
((REMAP) == TIM_TIM14_RTC) ||\
|
||||
((REMAP) == TIM_TIM14_HSE) ||\
|
||||
((REMAP) == TIM_TIM14_MCO))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
/** @defgroup TIMEx_Remap
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
|
||||
#define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
|
||||
#define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
|
||||
#define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
|
||||
|
||||
#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
|
||||
((REMAP) == TIM_TIM16_GPIO) ||\
|
||||
((REMAP) == TIM_TIM16_RTC) ||\
|
||||
((REMAP) == TIM_TIM16_HSE) ||\
|
||||
((REMAP) == TIM_TIM16_MCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
/** @defgroup TIMEx_Remap
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
|
||||
#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
|
||||
#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
|
||||
((REMAP) == TIM_TIM1_ADC1_AWD3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
/** @defgroup TIMEx_Group_Channel5
|
||||
* @{
|
||||
*/
|
||||
#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
|
||||
#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
|
||||
|
||||
#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/**
|
||||
* @brief Sets the TIM Capture Compare Register value on runtime without
|
||||
* calling another time ConfigChannel function.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__ : TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @param __COMPARE__: specifies the Capture Compare register new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
|
||||
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
|
||||
|
||||
/**
|
||||
* @brief Gets the TIM Capture Compare Register value on runtime
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__ : TIM Channel associated with the capture compare register
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
|
||||
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
|
||||
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
|
||||
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
|
||||
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
/**
|
||||
* @brief Sets the TIM Capture Compare Register value on runtime without
|
||||
* calling another time ConfigChannel function.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__ : TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
||||
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
||||
* @param __COMPARE__: specifies the Capture Compare register new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
|
||||
((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))
|
||||
|
||||
/**
|
||||
* @brief Gets the TIM Capture Compare Register value on runtime
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__ : TIM Channel associated with the capture compare register
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
|
||||
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
|
||||
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
|
||||
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
|
||||
* @arg TIM_CHANNEL_5: get capture/compare 5 register value
|
||||
* @arg TIM_CHANNEL_6: get capture/compare 6 register value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
|
||||
((__HANDLE__)->Instance->CCR6))
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Extnsion Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx)
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
||||
/* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
|
||||
/* Extension Callback *********************************************************/
|
||||
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Extension Peripheral State functions **************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_TIM_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,766 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_tsc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Touch Sensing Controller (TSC) peripheral:
|
||||
* + Initialization and DeInitialization
|
||||
* + Channel IOs, Shield IOs and Sampling IOs configuration
|
||||
* + Start and Stop an acquisition
|
||||
* + Read acquisition result
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### TSC specific features #####
|
||||
================================================================================
|
||||
[..]
|
||||
(#) Proven and robust surface charge transfer acquisition principle
|
||||
|
||||
(#) Supports up to 3 capacitive sensing channels per group
|
||||
|
||||
(#) Capacitive sensing channels can be acquired in parallel offering a very good
|
||||
response time
|
||||
|
||||
(#) Spread spectrum feature to improve system robustness in noisy environments
|
||||
|
||||
(#) Full hardware management of the charge transfer acquisition sequence
|
||||
|
||||
(#) Programmable charge transfer frequency
|
||||
|
||||
(#) Programmable sampling capacitor I/O pin
|
||||
|
||||
(#) Programmable channel I/O pin
|
||||
|
||||
(#) Programmable max count value to avoid long acquisition when a channel is faulty
|
||||
|
||||
(#) Dedicated end of acquisition and max count error flags with interrupt capability
|
||||
|
||||
(#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
|
||||
components
|
||||
|
||||
(#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(#) Enable the TSC interface clock using __TSC_CLK_ENABLE() macro.
|
||||
|
||||
(#) GPIO pins configuration
|
||||
(++) Enable the clock for the TSC GPIOs using __GPIOx_CLK_ENABLE() macro.
|
||||
(++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
|
||||
and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
|
||||
using HAL_GPIO_Init() function.
|
||||
(++) Configure the alternate function on all the TSC pins using HAL_xxxx() function.
|
||||
|
||||
(#) Interrupts configuration
|
||||
(++) Configure the NVIC (if the interrupt model is used) using HAL_xxx() function.
|
||||
|
||||
(#) TSC configuration
|
||||
(++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
|
||||
|
||||
*** Acquisition sequence ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Discharge all IOs using HAL_TSC_IODischarge() function.
|
||||
(+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
|
||||
of the sampling capacitor and electrodes design.
|
||||
(+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
|
||||
(+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
|
||||
If the synchronized mode is selected, the acquisition will start as soon as the signal
|
||||
is received on the synchro pin.
|
||||
(+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
|
||||
HAL_TSC_GetState() function or using WFI instruction for example.
|
||||
(+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
|
||||
(+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TSC
|
||||
* @brief HAL TSC module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static uint32_t TSC_extract_groups(uint32_t iomask);
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TSC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the TSC.
|
||||
(+) De-initialize the TSC.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the TSC peripheral according to the specified parameters
|
||||
* in the TSC_InitTypeDef structure.
|
||||
* @param htsc: TSC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check TSC handle allocation */
|
||||
if (htsc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
|
||||
assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
|
||||
assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
|
||||
assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
|
||||
assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
|
||||
assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
|
||||
assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
|
||||
assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
|
||||
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
|
||||
assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
|
||||
assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
|
||||
|
||||
/* Initialize the TSC state */
|
||||
htsc->State = HAL_TSC_STATE_BUSY;
|
||||
|
||||
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
|
||||
HAL_TSC_MspInit(htsc);
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Set TSC parameters */
|
||||
|
||||
/* Enable TSC */
|
||||
htsc->Instance->CR = TSC_CR_TSCE;
|
||||
|
||||
/* Set all functions */
|
||||
htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
|
||||
htsc->Init.CTPulseLowLength |
|
||||
(uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) |
|
||||
htsc->Init.SpreadSpectrumPrescaler |
|
||||
htsc->Init.PulseGeneratorPrescaler |
|
||||
htsc->Init.MaxCountValue |
|
||||
htsc->Init.IODefaultMode |
|
||||
htsc->Init.SynchroPinPolarity |
|
||||
htsc->Init.AcquisitionMode);
|
||||
|
||||
/* Spread spectrum */
|
||||
if (htsc->Init.SpreadSpectrum == ENABLE)
|
||||
{
|
||||
htsc->Instance->CR |= TSC_CR_SSE;
|
||||
}
|
||||
|
||||
/* Disable Schmitt trigger hysteresis on all used TSC IOs */
|
||||
htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
|
||||
|
||||
/* Set channel and shield IOs */
|
||||
htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
|
||||
|
||||
/* Set sampling IOs */
|
||||
htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
|
||||
|
||||
/* Set the groups to be acquired */
|
||||
htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
|
||||
|
||||
/* Disable interrupts */
|
||||
htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
|
||||
|
||||
/* Clear flags */
|
||||
htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
/* Initialize the TSC state */
|
||||
htsc->State = HAL_TSC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the TSC peripheral registers to their default reset values.
|
||||
* @param htsc: TSC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check TSC handle allocation */
|
||||
if (htsc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_TSC_MspDeInit(htsc);
|
||||
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the TSC MSP.
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_TSC_MspInit could be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the TSC MSP.
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_TSC_MspDeInit could be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TSC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### I/O Operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start acquisition in polling mode.
|
||||
(+) Start acquisition in interrupt mode.
|
||||
(+) Stop conversion in polling mode.
|
||||
(+) Stop conversion in interrupt mode.
|
||||
(+) Get group acquisition status.
|
||||
(+) Get group acquisition value.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the acquisition.
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_BUSY;
|
||||
|
||||
/* Clear interrupts */
|
||||
__HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
|
||||
|
||||
/* Clear flags */
|
||||
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
|
||||
|
||||
/* Stop discharging the IOs */
|
||||
__HAL_TSC_SET_IODEF_INFLOAT(htsc);
|
||||
|
||||
/* Launch the acquisition */
|
||||
__HAL_TSC_START_ACQ(htsc);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the interrupt and starts the acquisition
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_BUSY;
|
||||
|
||||
/* Enable end of acquisition interrupt */
|
||||
__HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
|
||||
|
||||
/* Enable max count error interrupt (optional) */
|
||||
if (htsc->Init.MaxCountInterrupt == ENABLE)
|
||||
{
|
||||
__HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
|
||||
}
|
||||
|
||||
/* Clear flags */
|
||||
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
|
||||
|
||||
/* Stop discharging the IOs */
|
||||
__HAL_TSC_SET_IODEF_INFLOAT(htsc);
|
||||
|
||||
/* Launch the acquisition */
|
||||
__HAL_TSC_START_ACQ(htsc);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the acquisition previously launched in polling mode
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
/* Stop the acquisition */
|
||||
__HAL_TSC_STOP_ACQ(htsc);
|
||||
|
||||
/* Clear flags */
|
||||
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
|
||||
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the acquisition previously launched in interrupt mode
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
/* Stop the acquisition */
|
||||
__HAL_TSC_STOP_ACQ(htsc);
|
||||
|
||||
/* Disable interrupts */
|
||||
__HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
|
||||
|
||||
/* Clear flags */
|
||||
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
|
||||
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the acquisition status for a group
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @param gx_index: Index of the group
|
||||
* @retval Group status
|
||||
*/
|
||||
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
assert_param(IS_GROUP_INDEX(gx_index));
|
||||
|
||||
/* Return the group status */
|
||||
return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the acquisition measure for a group
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @param gx_index: Index of the group
|
||||
* @retval Acquisition measure
|
||||
*/
|
||||
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
assert_param(IS_GROUP_INDEX(gx_index));
|
||||
|
||||
/* Return the group acquisition counter */
|
||||
return htsc->Instance->IOGXCR[gx_index];
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TSC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure TSC IOs
|
||||
(+) Discharge TSC IOs
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures TSC IOs
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @param config: pointer to the configuration structure.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
/* Stop acquisition */
|
||||
__HAL_TSC_STOP_ACQ(htsc);
|
||||
|
||||
/* Disable Schmitt trigger hysteresis on all used TSC IOs */
|
||||
htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
|
||||
|
||||
/* Set channel and shield IOs */
|
||||
htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
|
||||
|
||||
/* Set sampling IOs */
|
||||
htsc->Instance->IOSCR = config->SamplingIOs;
|
||||
|
||||
/* Set groups to be acquired */
|
||||
htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Discharge TSC IOs
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @param choice: enable or disable
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
if (choice == ENABLE)
|
||||
{
|
||||
__HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TSC_SET_IODEF_INFLOAT(htsc);
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
/* Return the group acquisition counter */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TSC_Group4 State functions
|
||||
* @brief State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Get TSC state.
|
||||
(+) Poll for acquisition completed.
|
||||
(+) Handles TSC interrupt request.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the TSC state
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
if (htsc->State == HAL_TSC_STATE_BUSY)
|
||||
{
|
||||
/* Check end of acquisition flag */
|
||||
if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
|
||||
{
|
||||
/* Check max count error flag */
|
||||
if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
|
||||
{
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_READY;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Return TSC state */
|
||||
return htsc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start acquisition and wait until completion
|
||||
* @note There is no need of a timeout parameter as the max count error is already
|
||||
* managed by the TSC peripheral.
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(htsc);
|
||||
|
||||
/* Check end of acquisition */
|
||||
while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
|
||||
{
|
||||
/* The timeout (max count error) is managed by the TSC peripheral itself. */
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(htsc);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles TSC interrupt request
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
|
||||
|
||||
/* Check if the end of acquisition occured */
|
||||
if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
|
||||
{
|
||||
/* Clear EOA flag */
|
||||
__HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
|
||||
}
|
||||
|
||||
/* Check if max count error occured */
|
||||
if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
|
||||
{
|
||||
/* Clear MCE flag */
|
||||
__HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_ERROR;
|
||||
/* Conversion completed callback */
|
||||
HAL_TSC_ErrorCallback(htsc);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change TSC state */
|
||||
htsc->State = HAL_TSC_STATE_READY;
|
||||
/* Conversion completed callback */
|
||||
HAL_TSC_ConvCpltCallback(htsc);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Acquisition completed callback in non blocking mode
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_TSC_ConvCpltCallback could be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error callback in non blocking mode
|
||||
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified TSC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_TSC_ErrorCallback could be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Utility function used to set the acquired groups mask
|
||||
* @param iomask: Channels IOs mask
|
||||
* @retval Acquired groups mask
|
||||
*/
|
||||
static uint32_t TSC_extract_groups(uint32_t iomask)
|
||||
{
|
||||
uint32_t groups = 0;
|
||||
uint32_t idx;
|
||||
|
||||
for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++)
|
||||
{
|
||||
if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET)
|
||||
{
|
||||
groups |= ((uint32_t)1 << idx);
|
||||
}
|
||||
}
|
||||
|
||||
return groups;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_TSC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,584 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_tsc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file contains all the functions prototypes for the TSC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_TSC_H
|
||||
#define __STM32F3xx_TSC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief TSC state structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */
|
||||
HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
|
||||
HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */
|
||||
HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */
|
||||
} HAL_TSC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC group status structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */
|
||||
TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */
|
||||
} TSC_GroupStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
|
||||
uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
|
||||
uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
|
||||
uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
|
||||
uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
|
||||
uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
|
||||
uint32_t MaxCountValue; /*!< Max count value */
|
||||
uint32_t IODefaultMode; /*!< IO default mode */
|
||||
uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
|
||||
uint32_t AcquisitionMode; /*!< Acquisition mode */
|
||||
uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */
|
||||
uint32_t ChannelIOs; /*!< Channel IOs mask */
|
||||
uint32_t ShieldIOs; /*!< Shield IOs mask */
|
||||
uint32_t SamplingIOs; /*!< Sampling IOs mask */
|
||||
} TSC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC IOs configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ChannelIOs; /*!< Channel IOs mask */
|
||||
uint32_t ShieldIOs; /*!< Shield IOs mask */
|
||||
uint32_t SamplingIOs; /*!< Sampling IOs mask */
|
||||
} TSC_IOConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSC_TypeDef *Instance; /*!< Register base address */
|
||||
TSC_InitTypeDef Init; /*!< Initialization parameters */
|
||||
__IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
|
||||
HAL_LockTypeDef Lock; /*!< Lock feature */
|
||||
} TSC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TSC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
|
||||
#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
|
||||
#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
|
||||
#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
|
||||
#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
|
||||
#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
|
||||
#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
|
||||
#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
|
||||
#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
|
||||
#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
|
||||
#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
|
||||
#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
|
||||
#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
|
||||
#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
|
||||
#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
|
||||
#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
|
||||
#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
|
||||
((VAL) == TSC_CTPH_2CYCLES) || \
|
||||
((VAL) == TSC_CTPH_3CYCLES) || \
|
||||
((VAL) == TSC_CTPH_4CYCLES) || \
|
||||
((VAL) == TSC_CTPH_5CYCLES) || \
|
||||
((VAL) == TSC_CTPH_6CYCLES) || \
|
||||
((VAL) == TSC_CTPH_7CYCLES) || \
|
||||
((VAL) == TSC_CTPH_8CYCLES) || \
|
||||
((VAL) == TSC_CTPH_9CYCLES) || \
|
||||
((VAL) == TSC_CTPH_10CYCLES) || \
|
||||
((VAL) == TSC_CTPH_11CYCLES) || \
|
||||
((VAL) == TSC_CTPH_12CYCLES) || \
|
||||
((VAL) == TSC_CTPH_13CYCLES) || \
|
||||
((VAL) == TSC_CTPH_14CYCLES) || \
|
||||
((VAL) == TSC_CTPH_15CYCLES) || \
|
||||
((VAL) == TSC_CTPH_16CYCLES))
|
||||
|
||||
#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
|
||||
#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
|
||||
#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
|
||||
#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
|
||||
#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
|
||||
#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
|
||||
#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
|
||||
#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
|
||||
#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
|
||||
#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
|
||||
#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
|
||||
#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
|
||||
#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
|
||||
#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
|
||||
#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
|
||||
#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
|
||||
#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
|
||||
((VAL) == TSC_CTPL_2CYCLES) || \
|
||||
((VAL) == TSC_CTPL_3CYCLES) || \
|
||||
((VAL) == TSC_CTPL_4CYCLES) || \
|
||||
((VAL) == TSC_CTPL_5CYCLES) || \
|
||||
((VAL) == TSC_CTPL_6CYCLES) || \
|
||||
((VAL) == TSC_CTPL_7CYCLES) || \
|
||||
((VAL) == TSC_CTPL_8CYCLES) || \
|
||||
((VAL) == TSC_CTPL_9CYCLES) || \
|
||||
((VAL) == TSC_CTPL_10CYCLES) || \
|
||||
((VAL) == TSC_CTPL_11CYCLES) || \
|
||||
((VAL) == TSC_CTPL_12CYCLES) || \
|
||||
((VAL) == TSC_CTPL_13CYCLES) || \
|
||||
((VAL) == TSC_CTPL_14CYCLES) || \
|
||||
((VAL) == TSC_CTPL_15CYCLES) || \
|
||||
((VAL) == TSC_CTPL_16CYCLES))
|
||||
|
||||
#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
|
||||
|
||||
#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
|
||||
|
||||
#define TSC_SS_PRESC_DIV1 ((uint32_t)0)
|
||||
#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
|
||||
#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
|
||||
|
||||
#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
|
||||
#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
|
||||
#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
|
||||
#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
|
||||
#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
|
||||
#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
|
||||
#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
|
||||
#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
|
||||
#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV2) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV4) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV8) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV16) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV32) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV64) || \
|
||||
((VAL) == TSC_PG_PRESC_DIV128))
|
||||
|
||||
#define TSC_MCV_255 ((uint32_t)(0 << 5))
|
||||
#define TSC_MCV_511 ((uint32_t)(1 << 5))
|
||||
#define TSC_MCV_1023 ((uint32_t)(2 << 5))
|
||||
#define TSC_MCV_2047 ((uint32_t)(3 << 5))
|
||||
#define TSC_MCV_4095 ((uint32_t)(4 << 5))
|
||||
#define TSC_MCV_8191 ((uint32_t)(5 << 5))
|
||||
#define TSC_MCV_16383 ((uint32_t)(6 << 5))
|
||||
#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
|
||||
((VAL) == TSC_MCV_511) || \
|
||||
((VAL) == TSC_MCV_1023) || \
|
||||
((VAL) == TSC_MCV_2047) || \
|
||||
((VAL) == TSC_MCV_4095) || \
|
||||
((VAL) == TSC_MCV_8191) || \
|
||||
((VAL) == TSC_MCV_16383))
|
||||
|
||||
#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
|
||||
#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
|
||||
#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
|
||||
|
||||
#define TSC_SYNC_POL_FALL ((uint32_t)0)
|
||||
#define TSC_SYNC_POL_RISE_HIGH (TSC_CR_SYNCPOL)
|
||||
#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH))
|
||||
|
||||
#define TSC_ACQ_MODE_NORMAL ((uint32_t)0)
|
||||
#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
|
||||
#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
|
||||
|
||||
#define TSC_IOMODE_UNUSED ((uint32_t)0)
|
||||
#define TSC_IOMODE_CHANNEL ((uint32_t)1)
|
||||
#define TSC_IOMODE_SHIELD ((uint32_t)2)
|
||||
#define TSC_IOMODE_SAMPLING ((uint32_t)3)
|
||||
#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
|
||||
((VAL) == TSC_IOMODE_CHANNEL) || \
|
||||
((VAL) == TSC_IOMODE_SHIELD) || \
|
||||
((VAL) == TSC_IOMODE_SAMPLING))
|
||||
|
||||
/** @defgroup TSC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
|
||||
#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
|
||||
#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
|
||||
#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define TSC_NB_OF_GROUPS (8)
|
||||
|
||||
#define TSC_GROUP1 ((uint32_t)0x00000001)
|
||||
#define TSC_GROUP2 ((uint32_t)0x00000002)
|
||||
#define TSC_GROUP3 ((uint32_t)0x00000004)
|
||||
#define TSC_GROUP4 ((uint32_t)0x00000008)
|
||||
#define TSC_GROUP5 ((uint32_t)0x00000010)
|
||||
#define TSC_GROUP6 ((uint32_t)0x00000020)
|
||||
#define TSC_GROUP7 ((uint32_t)0x00000040)
|
||||
#define TSC_GROUP8 ((uint32_t)0x00000080)
|
||||
#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
|
||||
|
||||
#define TSC_GROUP1_IDX ((uint32_t)0)
|
||||
#define TSC_GROUP2_IDX ((uint32_t)1)
|
||||
#define TSC_GROUP3_IDX ((uint32_t)2)
|
||||
#define TSC_GROUP4_IDX ((uint32_t)3)
|
||||
#define TSC_GROUP5_IDX ((uint32_t)4)
|
||||
#define TSC_GROUP6_IDX ((uint32_t)5)
|
||||
#define TSC_GROUP7_IDX ((uint32_t)6)
|
||||
#define TSC_GROUP8_IDX ((uint32_t)7)
|
||||
#define IS_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
|
||||
|
||||
#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
|
||||
#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
|
||||
#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
|
||||
#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
|
||||
#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
|
||||
|
||||
#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
|
||||
#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
|
||||
#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
|
||||
#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
|
||||
#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
|
||||
|
||||
#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
|
||||
#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
|
||||
#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
|
||||
#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
|
||||
#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
|
||||
|
||||
#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
|
||||
#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
|
||||
#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
|
||||
#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
|
||||
#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
|
||||
|
||||
#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
|
||||
#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
|
||||
#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
|
||||
#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
|
||||
#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
|
||||
|
||||
#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
|
||||
#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
|
||||
#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
|
||||
#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
|
||||
#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
|
||||
|
||||
#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
|
||||
#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
|
||||
#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
|
||||
#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
|
||||
#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
|
||||
|
||||
#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
|
||||
#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
|
||||
#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
|
||||
#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
|
||||
#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
|
||||
|
||||
#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset TSC handle state
|
||||
* @param __HANDLE__: TSC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the TSC peripheral.
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
|
||||
|
||||
/**
|
||||
* @brief Disable the TSC peripheral.
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
|
||||
|
||||
/**
|
||||
* @brief Start acquisition
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
|
||||
|
||||
/**
|
||||
* @brief Stop acquisition
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
|
||||
|
||||
/**
|
||||
* @brief Set IO default mode to output push-pull low
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
|
||||
|
||||
/**
|
||||
* @brief Set IO default mode to input floating
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
|
||||
|
||||
/**
|
||||
* @brief Set synchronization polarity to falling edge
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
|
||||
|
||||
/**
|
||||
* @brief Set synchronization polarity to rising edge and high level
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
|
||||
|
||||
/**
|
||||
* @brief Enable TSC interrupt.
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __INTERRUPT__: TSC interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable TSC interrupt.
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __INTERRUPT__: TSC interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check if the specified TSC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: TSC Handle
|
||||
* @param __INTERRUPT__: TSC interrupt
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected TSC's flag status.
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __FLAG__: TSC flag
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the TSC's pending flag.
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __FLAG__: TSC flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable schmitt trigger hysteresis on a group of IOs
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable schmitt trigger hysteresis on a group of IOs
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Open analog switch on a group of IOs
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Close analog switch on a group of IOs
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Enable a group of IOs in channel mode
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable a group of channel IOs
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Enable a group of IOs in sampling mode
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable a group of sampling IOs
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_IOY_MASK__: IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Enable acquisition groups
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_MASK__: Groups mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable acquisition groups
|
||||
* @param __HANDLE__: TSC handle
|
||||
* @param __GX_MASK__: Groups mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
|
||||
|
||||
/** @brief Gets acquisition group status
|
||||
* @param __HANDLE__: TSC Handle
|
||||
* @param __GX_INDEX__: Group index
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
|
||||
((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
|
||||
void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
|
||||
void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
|
||||
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
|
||||
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
|
||||
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
|
||||
void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
|
||||
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
|
||||
void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F3xx_TSC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,405 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_uart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended UART HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
The UART HAL driver can be used as follows:
|
||||
|
||||
(#) Declare a UART_HandleTypeDef handle structure.
|
||||
|
||||
(#) For the UART RS485 Driver Enabled mode, initialize the UART registers
|
||||
by calling the HAL_RS485Ex_Init() API.
|
||||
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx
|
||||
* @brief UART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
|
||||
in asynchronous mode.
|
||||
(+) For the asynchronous mode only these parameters can be configured:
|
||||
(++) Baud Rate
|
||||
(++) Word Length
|
||||
(++) Stop Bit
|
||||
(++) Parity: If the parity is enabled, then the MSB bit of the data written
|
||||
in the data register is transmitted but is changed by the parity bit.
|
||||
Depending on the frame length defined by the M bit (8-bits or 9-bits)
|
||||
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
|
||||
the possible UART frame formats are as listed in the following table:
|
||||
+---------------------------------------------------------------+
|
||||
| M bit | PCE bit | UART frame |
|
||||
|-----------|-----------|---------------------------------------|
|
||||
| 0 | 0 | | SB | 8-bit data | STB | |
|
||||
|-----------|-----------|---------------------------------------|
|
||||
| 0 | 1 | | SB | 7-bit data | PB | STB | |
|
||||
|-----------|-----------|---------------------------------------|
|
||||
| 1 | 0 | | SB | 9-bit data | STB | |
|
||||
|-----------|-----------|---------------------------------------|
|
||||
| 1 | 1 | | SB | 8-bit data | PB | STB | |
|
||||
+---------------------------------------------------------------+
|
||||
| M1M0 bits | PCE bit | UART frame |
|
||||
|-----------------------|---------------------------------------|
|
||||
| 10 | 0 | | SB | 7-bit data | STB | |
|
||||
|-----------|-----------|---------------------------------------|
|
||||
| 10 | 1 | | SB | 6-bit data | PB | STB | |
|
||||
+---------------------------------------------------------------+
|
||||
(++) Hardware flow control
|
||||
(++) Receiver/transmitter modes
|
||||
(++) Over Sampling Method
|
||||
(++) One-Bit Sampling Method
|
||||
(+) For the asynchronous mode, the following advanced features can be configured as well:
|
||||
(++) TX and/or RX pin level inversion
|
||||
(++) data logical level inversion
|
||||
(++) RX and TX pins swap
|
||||
(++) RX overrun detection disabling
|
||||
(++) DMA disabling on RX error
|
||||
(++) MSB first on communication line
|
||||
(++) auto Baud rate detection
|
||||
[..]
|
||||
The HAL_RS485Ex_Init() API follows respectively the UART RS485 mode
|
||||
configuration procedures (details for the procedures are available in reference manual).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the RS485 Driver enable feature according to the specified
|
||||
* parameters in the UART_InitTypeDef and creates the associated handle .
|
||||
* @param huart: uart handle
|
||||
* @param UART_DEPolarity: select the driver enable polarity
|
||||
* This parameter can be one of the following values:
|
||||
* @arg UART_DE_POLARITY_HIGH: DE signal is active high
|
||||
* @arg UART_DE_POLARITY_LOW: DE signal is active low
|
||||
* @param UART_DEAssertionTime: Driver Enable assertion time
|
||||
* 5-bit value defining the time between the activation of the DE (Driver Enable)
|
||||
* signal and the beginning of the start bit. It is expressed in sample time
|
||||
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
|
||||
* @param UART_DEDeassertionTime: Driver Enable deassertion time
|
||||
* 5-bit value defining the time between the end of the last stop bit, in a
|
||||
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
|
||||
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
|
||||
* oversampling rate).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime)
|
||||
{
|
||||
uint32_t temp = 0x0;
|
||||
|
||||
/* Check the UART handle allocation */
|
||||
if(huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the Driver Enable UART instance */
|
||||
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
|
||||
|
||||
/* Check the Driver Enable polarity */
|
||||
assert_param(IS_UART_DE_POLARITY(UART_DEPolarity));
|
||||
|
||||
/* Check the Driver Enable assertion time */
|
||||
assert_param(IS_UART_ASSERTIONTIME(UART_DEAssertionTime));
|
||||
|
||||
/* Check the Driver Enable deassertion time */
|
||||
assert_param(IS_UART_DEASSERTIONTIME(UART_DEDeassertionTime));
|
||||
|
||||
if(huart->State == HAL_UART_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware : GPIO, CLOCK */
|
||||
HAL_UART_MspInit(huart);
|
||||
}
|
||||
|
||||
huart->State = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
huart->Instance->CR3 |= USART_CR3_DEM;
|
||||
|
||||
/* Set the Driver Enable polarity */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, UART_DEPolarity);
|
||||
|
||||
/* Set the Driver Enable assertion and deassertion times */
|
||||
temp = (UART_DEAssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
|
||||
temp |= (UART_DEDeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
||||
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->State to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Group2 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides an extended function allowing to control the UART.
|
||||
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
|
||||
detection length to more than 4 bits for multiprocessor address mark wake up.
|
||||
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() configures the address for wake-up from
|
||||
Stop mode based on address match
|
||||
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
|
||||
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief By default in multiprocessor mode, when the wake up method is set
|
||||
* to address mark, the UART handles only 4-bit long addresses detection.
|
||||
* This API allows to enable longer addresses detection (6-, 7- or 8-bit
|
||||
* long):
|
||||
* - 6-bit address detection in 7-bit data mode
|
||||
* - 7-bit address detection in 8-bit data mode
|
||||
* - 8-bit address detection in 9-bit data mode
|
||||
* @param huart: UART handle
|
||||
* @param AddressLength: this parameter can be one of the following values:
|
||||
* @arg UART_ADDRESS_DETECT_4B: 4-bit long address
|
||||
* @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
|
||||
{
|
||||
/* Check the UART handle allocation */
|
||||
if(huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the address length parameter */
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
|
||||
|
||||
huart->State = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->State to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set Wakeup from Stop mode interrupt flag selection
|
||||
* @param huart: uart handle,
|
||||
* @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg UART_WAKEUP_ON_ADDRESS
|
||||
* @arg UART_WAKEUP_ON_STARTBIT
|
||||
* @arg UART_WAKEUP_ON_READDATA_NONEMPTY
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
|
||||
/* check the wake-up from stop mode UART instance */
|
||||
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
|
||||
/* check the wake-up selection parameter */
|
||||
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->State = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the wake-up selection scheme */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
|
||||
|
||||
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
|
||||
{
|
||||
UART_Wakeup_AddressConfig(huart, WakeUpSelection);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* Wait until REACK flag is set */
|
||||
if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the UART State */
|
||||
huart->State= HAL_UART_STATE_READY;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable UART Stop Mode
|
||||
* The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE
|
||||
* @param huart: uart handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->State = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Set the USART UESM bit */
|
||||
huart->Instance->CR1 |= USART_CR1_UESM;
|
||||
|
||||
huart->State = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable UART Stop Mode
|
||||
* @param huart: uart handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->State = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Clear USART UESM bit */
|
||||
huart->Instance->CR1 &= ~(USART_CR1_UESM);
|
||||
|
||||
huart->State = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
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Reference in New Issue