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Merge pull request #5698 from jeromecoutant/PR_ST_ASSERT 

STM32 : correct compilation issue with USE_FULL_ASSERT macro
pull/5723/head
Martin Kojtal 2017-12-20 14:41:25 +00:00 committed by GitHub
parent 2e6f24518b 8bc92bdd22
commit 897324e8a3
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 15 additions and 16 deletions
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13
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h
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@ -442,16 +442,6 @@
* @{ * @{
*/ */
#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ #define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
is connected to the non inverting input of comparator X-1U */
/**
* @}
*/
#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
* @{
*/
#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) #define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
is connected to the non inverting input of comparator X-1U */ is connected to the non inverting input of comparator X-1U */
/** /**
@ -2395,8 +2385,7 @@
|| \ || \
(((INPUT) == COMP_NONINVERTINGINPUT_IO1))) (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ #define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */ #define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c
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@ -176,11 +176,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
} }
/* Select PLLSAI output as USB clock source */ /* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
@ -241,11 +243,13 @@ uint8_t SetSysClock_PLL_HSI(void)
} }
/* Select PLLSAI output as USB clock source */ /* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c
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@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
} }
/* Select PLLSAI output as USB clock source */ /* Select PLLSAI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
@ -242,11 +244,13 @@ uint8_t SetSysClock_PLL_HSI(void)
} }
/* Select PLLI2S output as USB clock source */ /* Select PLLI2S output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

2
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h
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@ -611,6 +611,8 @@ typedef struct __SPI_HandleTypeDef
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
/** /**
* @} * @}