From 75db24ff155f1a80e539083bbdb4aa93988e126a Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 12 Dec 2017 10:59:34 +0100 Subject: [PATCH 1/3] STM32F3 : compilation issue Issue comes only when ST HAL macro USE_FULL_ASSERT is enabled --- .../TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h index 2a8d5d3509..855b76fc0c 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h @@ -442,16 +442,6 @@ * @{ */ #define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ -#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) - is connected to the non inverting input of comparator X-1U */ -/** - * @} - */ -#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) -/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices) - * @{ - */ -#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ #define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) is connected to the non inverting input of comparator X-1U */ /** @@ -2395,8 +2385,7 @@ || \ (((INPUT) == COMP_NONINVERTINGINPUT_IO1))) -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE)) +#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */ #define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */ From 4637279f51e086e58b754f089a4c7c6442cbb4ca Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 12 Dec 2017 11:00:56 +0100 Subject: [PATCH 2/3] STM32L4 : compilation issue Issue comes only when ST HAL macro USE_FULL_ASSERT is enabled --- targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h index 2e51ffb989..0be73f9243 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h @@ -611,6 +611,8 @@ typedef struct __SPI_HandleTypeDef #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) +#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) + /** * @} From 8bc92bdd22e79b474ed87e5bac1d52d217ca110c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 13 Dec 2017 10:32:58 +0100 Subject: [PATCH 3/3] STM32F4 : compilation issue Issue comes only when ST HAL macro USE_FULL_ASSERT is enabled --- .../TARGET_NUCLEO_F412ZG/system_clock.c | 8 ++++++-- .../TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c index 2ffdfc51c0..191ecaf3ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c @@ -176,11 +176,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -241,11 +243,13 @@ uint8_t SetSysClock_PLL_HSI(void) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c index 34aa173313..66575fd3f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c @@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -242,11 +244,13 @@ uint8_t SetSysClock_PLL_HSI(void) } /* Select PLLI2S output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);