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Merge pull request #1130 from stevew817/master 

Silicon Labs - Cosmetic: apply mbed coding style to HAL
pull/1132/head
Martin Kojtal 2015-05-22 10:18:28 +01:00
parent 61deb3e97c 2c55311cfb
commit 88d158e43b
31 changed files with 1455 additions and 1423 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c
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@ -42,7 +42,8 @@ void analogout_preinit(dac_t *obj, PinName pin)
MBED_ASSERT((int) obj->channel != NC); MBED_ASSERT((int) obj->channel != NC);
} }
void analogout_init(dac_t *obj, PinName pin) { void analogout_init(dac_t *obj, PinName pin)
{
static uint8_t dac_initialized = 0; static uint8_t dac_initialized = 0;
/* init in-memory structure */ /* init in-memory structure */
@ -83,7 +84,8 @@ void analogout_pins_enable(dac_t *obj, uint8_t enable)
//not avail for EFM32 //not avail for EFM32
} }
static inline void dac_write(dac_t *obj, int value) { static inline void dac_write(dac_t *obj, int value)
{
switch (obj->channel) { switch (obj->channel) {
case 0: case 0:
obj->dac->CH0DATA = value; obj->dac->CH0DATA = value;
@ -94,7 +96,8 @@ static inline void dac_write(dac_t *obj, int value) {
} }
} }
static inline int dac_read(dac_t *obj) { static inline int dac_read(dac_t *obj)
{
switch (obj->channel) { switch (obj->channel) {
case 0: case 0:
return obj->dac->CH0DATA; return obj->dac->CH0DATA;
@ -109,23 +112,27 @@ static inline int dac_read(dac_t *obj) {
} }
} }
void analogout_write(dac_t *obj, float value) { void analogout_write(dac_t *obj, float value)
{
/* We multiply the float value with 0xFFF because the DAC has 12-bit resolution. /* We multiply the float value with 0xFFF because the DAC has 12-bit resolution.
* Ie. accepts values between 0 and 0xFFF (4096). */ * Ie. accepts values between 0 and 0xFFF (4096). */
dac_write(obj, value*0xFFF); dac_write(obj, value*0xFFF);
} }
void analogout_write_u16(dac_t *obj, uint16_t value) { void analogout_write_u16(dac_t *obj, uint16_t value)
{
/* The DAC has 12 bit resolution, so we remove the 4 least significant bits */ /* The DAC has 12 bit resolution, so we remove the 4 least significant bits */
dac_write(obj, value >> 4); dac_write(obj, value >> 4);
} }
float analogout_read(dac_t *obj) { float analogout_read(dac_t *obj)
{
/* dac_read returns a number between 0 and 0xFFF. Division gives us a float between 0 and 1 */ /* dac_read returns a number between 0 and 0xFFF. Division gives us a float between 0 and 1 */
return dac_read(obj)/(float)0xFFF; return dac_read(obj)/(float)0xFFF;
} }
uint16_t analogout_read_u16(dac_t *obj) { uint16_t analogout_read_u16(dac_t *obj)
{
/* dac_read returns a number with 12 significant digits, /* dac_read returns a number with 12 significant digits,
* so we shift in 0s from right to make it a 16 bit number */ * so we shift in 0s from right to make it a 16 bit number */
return dac_read(obj) << 4; return dac_read(obj) << 4;

12
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c
View File

@ -56,10 +56,8 @@ int dma_channel_allocate(uint32_t capabilities)
{ {
int i; int i;
// Check if 2d copy is required // Check if 2d copy is required
if (DMA_CAP_2DCOPY & capabilities) if (DMA_CAP_2DCOPY & capabilities) {
{ if (channels & 1) {
if (channels & 1)
{
// Channel already in use // Channel already in use
return DMA_ERROR_OUT_OF_CHANNELS; return DMA_ERROR_OUT_OF_CHANNELS;
} else { } else {
@ -67,10 +65,8 @@ int dma_channel_allocate(uint32_t capabilities)
return 0; return 0;
} }
} }
for (i = 1; i < DMA_CHAN_COUNT; i++) for (i = 1; i < DMA_CHAN_COUNT; i++) {
{ if ((channels & (1 << i)) == 0) {
if ((channels & (1 << i)) == 0)
{
// Channel available // Channel available
channels |= 1 << i; channels |= 1 << i;
return i; return i;

3
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c
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@ -168,8 +168,7 @@ static void GPIOINT_IRQDispatcher(uint32_t iflags)
uint32_t irqIdx; uint32_t irqIdx;
/* check for all flags set in IF register */ /* check for all flags set in IF register */
while(iflags) while(iflags) {
{
irqIdx = GPIOINT_MASK2IDX(iflags); irqIdx = GPIOINT_MASK2IDX(iflags);
/* clear flag*/ /* clear flag*/

3
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h
View File

@ -49,7 +49,8 @@ static inline int gpio_read(gpio_t *obj)
} }
} }
static inline int gpio_is_connected(const gpio_t *obj) { static inline int gpio_is_connected(const gpio_t *obj)
{
return obj->pin != (PinName)NC; return obj->pin != (PinName)NC;
} }

27
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c
View File

@ -344,10 +344,10 @@ int block_and_wait_for_ack(I2C_TypeDef *i2c)
void i2c_slave_mode(i2c_t *obj, int enable_slave) void i2c_slave_mode(i2c_t *obj, int enable_slave)
{ {
if(enable_slave){ if(enable_slave) {
obj->i2c.i2c->CTRL |= _I2C_CTRL_SLAVE_MASK; obj->i2c.i2c->CTRL |= _I2C_CTRL_SLAVE_MASK;
obj->i2c.i2c->CTRL |= _I2C_CTRL_AUTOACK_MASK; //Slave implementation assumes auto acking obj->i2c.i2c->CTRL |= _I2C_CTRL_AUTOACK_MASK; //Slave implementation assumes auto acking
}else{ } else {
obj->i2c.i2c->CTRL &= ~_I2C_CTRL_SLAVE_MASK; obj->i2c.i2c->CTRL &= ~_I2C_CTRL_SLAVE_MASK;
obj->i2c.i2c->CTRL &= ~_I2C_CTRL_AUTOACK_MASK; //Master implementation ACKs manually obj->i2c.i2c->CTRL &= ~_I2C_CTRL_AUTOACK_MASK; //Master implementation ACKs manually
} }
@ -356,19 +356,19 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave)
int i2c_slave_receive(i2c_t *obj) int i2c_slave_receive(i2c_t *obj)
{ {
if(obj->i2c.i2c->IF & I2C_IF_ADDR){ if(obj->i2c.i2c->IF & I2C_IF_ADDR) {
obj->i2c.i2c->IFC = I2C_IF_ADDR; //Clear interrupt obj->i2c.i2c->IFC = I2C_IF_ADDR; //Clear interrupt
/*0x00 is the address for general write. /*0x00 is the address for general write.
The address the master wrote is in RXDATA now The address the master wrote is in RXDATA now
and reading it also frees the buffer for the next and reading it also frees the buffer for the next
write which can then be acked. */ write which can then be acked. */
if(obj->i2c.i2c->RXDATA == 0x00){ if(obj->i2c.i2c->RXDATA == 0x00) {
return WriteGeneral; //Read the address; return WriteGeneral; //Read the address;
} }
if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER){ if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER) {
return ReadAddressed; return ReadAddressed;
}else{ } else {
return WriteAddressed; return WriteAddressed;
} }
} }
@ -426,7 +426,8 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
* @param handler The I2C IRQ handler to be set * @param handler The I2C IRQ handler to be set
* @param hint DMA hint usage * @param hint DMA hint usage
*/ */
void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) { void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
{
I2C_TransferReturn_TypeDef retval; I2C_TransferReturn_TypeDef retval;
if(i2c_active(obj)) return; if(i2c_active(obj)) return;
if((tx_length == 0) && (rx_length == 0)) return; if((tx_length == 0) && (rx_length == 0)) return;
@ -468,8 +469,7 @@ void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_
if(retval == i2cTransferInProgress) { if(retval == i2cTransferInProgress) {
blockSleepMode(EM1); blockSleepMode(EM1);
} } else {
else {
// something happened, and the transfer did not go through // something happened, and the transfer did not go through
// So, we need to clean up // So, we need to clean up
@ -485,7 +485,8 @@ void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_
* @param obj The I2C object which holds the transfer information * @param obj The I2C object which holds the transfer information
* @return Returns event flags if a transfer termination condition was met or 0 otherwise. * @return Returns event flags if a transfer termination condition was met or 0 otherwise.
*/ */
uint32_t i2c_irq_handler_asynch(i2c_t *obj) { uint32_t i2c_irq_handler_asynch(i2c_t *obj)
{
// For now, we are assuming a solely interrupt-driven implementation. // For now, we are assuming a solely interrupt-driven implementation.
@ -527,14 +528,16 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
* @param obj The I2C object * @param obj The I2C object
* @return non-zero if the I2C module is active or zero if it is not * @return non-zero if the I2C module is active or zero if it is not
*/ */
uint8_t i2c_active(i2c_t *obj) { uint8_t i2c_active(i2c_t *obj)
{
return (obj->i2c.i2c->STATE & I2C_STATE_BUSY); return (obj->i2c.i2c->STATE & I2C_STATE_BUSY);
} }
/** Abort ongoing asynchronous transaction. /** Abort ongoing asynchronous transaction.
* @param obj The I2C object * @param obj The I2C object
*/ */
void i2c_abort_asynch(i2c_t *obj) { void i2c_abort_asynch(i2c_t *obj)
{
// Do not deactivate I2C twice // Do not deactivate I2C twice
if (!i2c_active(obj)) return; if (!i2c_active(obj)) return;

12
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c
View File

@ -27,7 +27,8 @@ void lp_ticker_init()
rtc_set_comp0_handler((uint32_t)lp_ticker_irq_handler); rtc_set_comp0_handler((uint32_t)lp_ticker_irq_handler);
} }
void lp_ticker_set_interrupt(timestamp_t timestamp) { void lp_ticker_set_interrupt(timestamp_t timestamp)
{
uint64_t timestamp_ticks; uint64_t timestamp_ticks;
uint64_t current_ticks = RTC_CounterGet(); uint64_t current_ticks = RTC_CounterGet();
timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)); timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT));
@ -55,15 +56,18 @@ void lp_ticker_set_interrupt(timestamp_t timestamp) {
RTC_FreezeEnable(false); RTC_FreezeEnable(false);
} }
inline void lp_ticker_disable_interrupt() { inline void lp_ticker_disable_interrupt()
{
RTC_IntDisable(RTC_IF_COMP0); RTC_IntDisable(RTC_IF_COMP0);
} }
inline void lp_ticker_clear_interrupt() { inline void lp_ticker_clear_interrupt()
{
RTC_IntClear(RTC_IF_COMP0); RTC_IntClear(RTC_IF_COMP0);
} }
timestamp_t lp_ticker_read() { timestamp_t lp_ticker_read()
{
uint64_t ticks_temp; uint64_t ticks_temp;
uint64_t ticks = RTC_CounterGet(); uint64_t ticks = RTC_CounterGet();

3
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c
View File

@ -92,7 +92,8 @@ void mbed_sdk_init()
gpio_init_out_ex(&bc_enable, EFM_BC_EN, 1); gpio_init_out_ex(&bc_enable, EFM_BC_EN, 1);
} }
void check_usart_clock(USART_TypeDef* usart, uint32_t clockmask) { void check_usart_clock(USART_TypeDef* usart, uint32_t clockmask)
{
uint32_t freq = 14000000, baudrate; uint32_t freq = 14000000, baudrate;
USART_OVS_TypeDef ovs; USART_OVS_TypeDef ovs;

6
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c
View File

@ -33,7 +33,8 @@
static int pwm_clockfreq; static int pwm_clockfreq;
static int pwm_prescaler_div; static int pwm_prescaler_div;
uint32_t pwmout_get_channel_route(pwmout_t *obj) { uint32_t pwmout_get_channel_route(pwmout_t *obj)
{
MBED_ASSERT(obj->channel != (PWMName) NC); MBED_ASSERT(obj->channel != (PWMName) NC);
switch (obj->channel) { switch (obj->channel) {
@ -115,7 +116,8 @@ void pwmout_init(pwmout_t *obj, PinName pin)
pwmout_period(obj, 0.02); pwmout_period(obj, 0.02);
} }
void pwmout_free(pwmout_t *obj) { void pwmout_free(pwmout_t *obj)
{
uint32_t routeloc = pwmout_get_channel_route(obj); uint32_t routeloc = pwmout_get_channel_route(obj);
if(PWM_TIMER->ROUTE & routeloc) { if(PWM_TIMER->ROUTE & routeloc) {
//This channel was in use, so disable //This channel was in use, so disable

15
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c
View File

@ -37,17 +37,14 @@ void RTC_IRQHandler(void)
{ {
uint32_t flags; uint32_t flags;
flags = RTC_IntGet(); flags = RTC_IntGet();
if (flags & RTC_IF_OF) if (flags & RTC_IF_OF) {
{
RTC_IntClear(RTC_IF_OF); RTC_IntClear(RTC_IF_OF);
/* RTC has overflowed (24 bits). Use time_base as software counter for upper 8 bits. */ /* RTC has overflowed (24 bits). Use time_base as software counter for upper 8 bits. */
time_base += 1 << 24; time_base += 1 << 24;
} }
if (flags & RTC_IF_COMP0) if (flags & RTC_IF_COMP0) {
{
RTC_IntClear(RTC_IF_COMP0); RTC_IntClear(RTC_IF_COMP0);
if (comp0_handler != NULL) if (comp0_handler != NULL) {
{
comp0_handler(); comp0_handler();
} }
} }
@ -69,8 +66,7 @@ void rtc_init_real(uint32_t flags)
{ {
useflags |= flags; useflags |= flags;
if (!rtc_inited) if (!rtc_inited) {
{
/* Start LFXO and wait until it is stable */ /* Start LFXO and wait until it is stable */
CMU_OscillatorEnable(cmuOsc_LFXO, true, true); CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
@ -114,8 +110,7 @@ void rtc_free_real(uint32_t flags)
flags &= ~flags; flags &= ~flags;
/* Disable the RTC if it was inited and is no longer in use by anyone. */ /* Disable the RTC if it was inited and is no longer in use by anyone. */
if (rtc_inited && (flags == 0)) if (rtc_inited && (flags == 0)) {
{
NVIC_DisableIRQ(RTC_IRQn); NVIC_DisableIRQ(RTC_IRQn);
RTC_Reset(); RTC_Reset();
CMU_ClockEnable(cmuClock_RTC, false); CMU_ClockEnable(cmuClock_RTC, false);

57
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c
View File

@ -94,7 +94,8 @@ static void usart2_rx_irq() { uart_irq(USART_2, 4, RxIrq); }
static void usart2_tx_irq() { uart_irq(USART_2, 4, TxIrq); USART_IntClear((USART_TypeDef*)USART_2, USART_IFC_TXC);} static void usart2_tx_irq() { uart_irq(USART_2, 4, TxIrq); USART_IntClear((USART_TypeDef*)USART_2, USART_IFC_TXC);}
#endif #endif
#ifdef LEUART0 #ifdef LEUART0
static void leuart0_irq() { static void leuart0_irq()
{
if(LEUART_IntGetEnabled(LEUART0) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) { if(LEUART_IntGetEnabled(LEUART0) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) {
uart_irq(LEUART_0, 5, RxIrq); uart_irq(LEUART_0, 5, RxIrq);
} else { } else {
@ -103,7 +104,8 @@ static void leuart0_irq() {
} }
#endif #endif
#ifdef LEUART1 #ifdef LEUART1
static void leuart1_irq() { static void leuart1_irq()
{
if(LEUART_IntGetEnabled(LEUART1) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) { if(LEUART_IntGetEnabled(LEUART1) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) {
uart_irq(LEUART_1, 6, RxIrq); uart_irq(LEUART_1, 6, RxIrq);
} else { } else {
@ -880,7 +882,8 @@ static void serial_dmaTransferComplete(unsigned int channel, bool primary, void
* Sets up the DMA configuration block for the assigned channel * Sets up the DMA configuration block for the assigned channel
* tx_nrx: true if configuring TX, false if configuring RX. * tx_nrx: true if configuring TX, false if configuring RX.
******************************************/ ******************************************/
static void serial_dmaSetupChannel(serial_t *obj, bool tx_nrx) { static void serial_dmaSetupChannel(serial_t *obj, bool tx_nrx)
{
DMA_CfgChannel_TypeDef channelConfig; DMA_CfgChannel_TypeDef channelConfig;
if(tx_nrx) { if(tx_nrx) {
@ -994,7 +997,8 @@ static void serial_dmaSetupChannel(serial_t *obj, bool tx_nrx) {
* Will try to allocate a channel and keep it. * Will try to allocate a channel and keep it.
* If succesfully allocated, state changes to DMA_USAGE_ALLOCATED. * If succesfully allocated, state changes to DMA_USAGE_ALLOCATED.
******************************************/ ******************************************/
static void serial_dmaTrySetState(DMA_OPTIONS_t *obj, DMAUsage requestedState, serial_t *serialPtr, bool tx_nrx) { static void serial_dmaTrySetState(DMA_OPTIONS_t *obj, DMAUsage requestedState, serial_t *serialPtr, bool tx_nrx)
{
DMAUsage currentState = obj->dmaUsageState; DMAUsage currentState = obj->dmaUsageState;
int tempDMAChannel = -1; int tempDMAChannel = -1;
@ -1029,7 +1033,8 @@ static void serial_dmaTrySetState(DMA_OPTIONS_t *obj, DMAUsage requestedState, s
} }
} }
static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length, bool tx_nrx) { static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length, bool tx_nrx)
{
DMA_CfgDescr_TypeDef channelConfig; DMA_CfgDescr_TypeDef channelConfig;
if(tx_nrx) { if(tx_nrx) {
@ -1117,7 +1122,8 @@ static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length
* @param event The logical OR of the TX events to configure * @param event The logical OR of the TX events to configure
* @param enable Set to non-zero to enable events, or zero to disable them * @param enable Set to non-zero to enable events, or zero to disable them
*/ */
void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) { void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
{
// Shouldn't have to enable TX interrupt here, just need to keep track of the requested events. // Shouldn't have to enable TX interrupt here, just need to keep track of the requested events.
if(enable) obj->serial.events |= event; if(enable) obj->serial.events |= event;
else obj->serial.events &= ~event; else obj->serial.events &= ~event;
@ -1128,7 +1134,8 @@ void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) {
* @param event The logical OR of the RX events to configure * @param event The logical OR of the RX events to configure
* @param enable Set to non-zero to enable events, or zero to disable them * @param enable Set to non-zero to enable events, or zero to disable them
*/ */
void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) { void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
{
if(enable) { if(enable) {
obj->serial.events |= event; obj->serial.events |= event;
} else { } else {
@ -1187,7 +1194,8 @@ void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) {
* @param tx The buffer for sending. * @param tx The buffer for sending.
* @param tx_length The number of words to transmit. * @param tx_length The number of words to transmit.
*/ */
void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) { void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
{
// We only support byte buffers for now // We only support byte buffers for now
MBED_ASSERT(width == 8); MBED_ASSERT(width == 8);
@ -1206,7 +1214,8 @@ void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
* @param rx The buffer for receiving. * @param rx The buffer for receiving.
* @param rx_length The number of words to read. * @param rx_length The number of words to read.
*/ */
void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) { void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
{
// We only support byte buffers for now // We only support byte buffers for now
MBED_ASSERT(width == 8); MBED_ASSERT(width == 8);
@ -1226,7 +1235,8 @@ void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
* @param obj The serial object * @param obj The serial object
* @param char_match A character in range 0-254 * @param char_match A character in range 0-254
*/ */
void serial_set_char_match(serial_t *obj, uint8_t char_match) { void serial_set_char_match(serial_t *obj, uint8_t char_match)
{
// We only have hardware support for this in LEUART. // We only have hardware support for this in LEUART.
// When in USART/UART, we can set up a check in the receiving ISR, but not when using DMA. // When in USART/UART, we can set up a check in the receiving ISR, but not when using DMA.
if (char_match != SERIAL_RESERVED_CHAR_MATCH) { if (char_match != SERIAL_RESERVED_CHAR_MATCH) {
@ -1252,7 +1262,8 @@ void serial_set_char_match(serial_t *obj, uint8_t char_match) {
* @param hint A suggestion for how to use DMA with this transfer * @param hint A suggestion for how to use DMA with this transfer
* @return Returns number of data transfered, or 0 otherwise * @return Returns number of data transfered, or 0 otherwise
*/ */
int serial_tx_asynch(serial_t *obj, void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) { int serial_tx_asynch(serial_t *obj, void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
// Check that a buffer has indeed been set up // Check that a buffer has indeed been set up
MBED_ASSERT(tx != (void*)0); MBED_ASSERT(tx != (void*)0);
if(tx_length == 0) return 0; if(tx_length == 0) return 0;
@ -1314,7 +1325,8 @@ int serial_tx_asynch(serial_t *obj, void *tx, size_t tx_length, uint8_t tx_width
* @param cb The function to call when an event occurs * @param cb The function to call when an event occurs
* @param hint A suggestion for how to use DMA with this transfer * @param hint A suggestion for how to use DMA with this transfer
*/ */
void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) { void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
{
// Check that a buffer has indeed been set up // Check that a buffer has indeed been set up
MBED_ASSERT(rx != (void*)0); MBED_ASSERT(rx != (void*)0);
if(rx_length == 0) return; if(rx_length == 0) return;
@ -1379,7 +1391,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
* @param obj The serial object * @param obj The serial object
* @return Non-zero if the TX transaction is ongoing, 0 otherwise * @return Non-zero if the TX transaction is ongoing, 0 otherwise
*/ */
uint8_t serial_tx_active(serial_t *obj) { uint8_t serial_tx_active(serial_t *obj)
{
switch(obj->serial.dmaOptionsTX.dmaUsageState) { switch(obj->serial.dmaOptionsTX.dmaUsageState) {
case DMA_USAGE_TEMPORARY_ALLOCATED: case DMA_USAGE_TEMPORARY_ALLOCATED:
/* Temporary allocation always means its active, as this state gets cleared afterwards */ /* Temporary allocation always means its active, as this state gets cleared afterwards */
@ -1402,7 +1415,8 @@ uint8_t serial_tx_active(serial_t *obj) {
* @param obj The serial object * @param obj The serial object
* @return Non-zero if the RX transaction is ongoing, 0 otherwise * @return Non-zero if the RX transaction is ongoing, 0 otherwise
*/ */
uint8_t serial_rx_active(serial_t *obj) { uint8_t serial_rx_active(serial_t *obj)
{
switch(obj->serial.dmaOptionsRX.dmaUsageState) { switch(obj->serial.dmaOptionsRX.dmaUsageState) {
case DMA_USAGE_TEMPORARY_ALLOCATED: case DMA_USAGE_TEMPORARY_ALLOCATED:
/* Temporary allocation always means its active, as this state gets cleared afterwards */ /* Temporary allocation always means its active, as this state gets cleared afterwards */
@ -1426,7 +1440,8 @@ uint8_t serial_rx_active(serial_t *obj) {
* @param obj The serial object * @param obj The serial object
* @return Returns event flags if a TX transfer termination condition was met or 0 otherwise * @return Returns event flags if a TX transfer termination condition was met or 0 otherwise
*/ */
int serial_tx_irq_handler_asynch(serial_t *obj) { int serial_tx_irq_handler_asynch(serial_t *obj)
{
/* This interrupt handler is called from USART irq */ /* This interrupt handler is called from USART irq */
uint8_t *buf = obj->tx_buff.buffer; uint8_t *buf = obj->tx_buff.buffer;
@ -1458,7 +1473,8 @@ int serial_tx_irq_handler_asynch(serial_t *obj) {
* @param obj The serial object * @param obj The serial object
* @return Returns event flags if a RX transfer termination condition was met or 0 otherwise * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise
*/ */
int serial_rx_irq_handler_asynch(serial_t *obj) { int serial_rx_irq_handler_asynch(serial_t *obj)
{
int event = 0; int event = 0;
/* This interrupt handler is called from USART irq */ /* This interrupt handler is called from USART irq */
@ -1599,7 +1615,8 @@ int serial_rx_irq_handler_asynch(serial_t *obj) {
* *
* WARNING: this code should be stateless, as re-entrancy is very possible in interrupt-based mode. * WARNING: this code should be stateless, as re-entrancy is very possible in interrupt-based mode.
*/ */
int serial_irq_handler_asynch(serial_t *obj) { int serial_irq_handler_asynch(serial_t *obj)
{
/* First, check if we're running in DMA mode */ /* First, check if we're running in DMA mode */
if(serial_dma_irq_fired[obj->serial.dmaOptionsRX.dmaChannel]) { if(serial_dma_irq_fired[obj->serial.dmaOptionsRX.dmaChannel]) {
/* Clean up */ /* Clean up */
@ -1643,7 +1660,8 @@ int serial_irq_handler_asynch(serial_t *obj) {
* *
* @param obj The serial object * @param obj The serial object
*/ */
void serial_tx_abort_asynch(serial_t *obj) { void serial_tx_abort_asynch(serial_t *obj)
{
/* Stop transmitter */ /* Stop transmitter */
//obj->serial.periph.uart->CMD |= USART_CMD_TXDIS; //obj->serial.periph.uart->CMD |= USART_CMD_TXDIS;
@ -1679,7 +1697,8 @@ void serial_tx_abort_asynch(serial_t *obj) {
* *
* @param obj The serial object * @param obj The serial object
*/ */
void serial_rx_abort_asynch(serial_t *obj) { void serial_rx_abort_asynch(serial_t *obj)
{
/* Stop receiver */ /* Stop receiver */
obj->serial.periph.uart->CMD |= USART_CMD_RXDIS; obj->serial.periph.uart->CMD |= USART_CMD_RXDIS;

3
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c
View File

@ -91,8 +91,7 @@ void blockSleepMode(sleepstate_enum minimumMode)
void unblockSleepMode(sleepstate_enum minimumMode) void unblockSleepMode(sleepstate_enum minimumMode)
{ {
INT_Disable(); INT_Disable();
if(sleep_block_counter[minimumMode] > 0) if(sleep_block_counter[minimumMode] > 0) {
{
sleep_block_counter[minimumMode]--; sleep_block_counter[minimumMode]--;
} }
INT_Enable(); INT_Enable();

30
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c
View File

@ -35,7 +35,8 @@
static uint16_t fill_word = SPI_FILL_WORD; static uint16_t fill_word = SPI_FILL_WORD;
#define SPI_LEAST_ACTIVE_SLEEPMODE EM1 #define SPI_LEAST_ACTIVE_SLEEPMODE EM1
inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj) { inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj)
{
switch ((int)obj->spi.spi) { switch ((int)obj->spi.spi) {
#ifdef USART0 #ifdef USART0
case SPI_0: case SPI_0:
@ -81,7 +82,8 @@ inline uint8_t spi_get_index(spi_t *obj)
return index; return index;
} }
uint8_t spi_get_module(spi_t *obj) { uint8_t spi_get_module(spi_t *obj)
{
return spi_get_index(obj); return spi_get_index(obj);
} }
@ -254,8 +256,7 @@ void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
NVIC_SetVector(IRQvector, handler); NVIC_SetVector(IRQvector, handler);
USART_IntEnable(obj->spi.spi, USART_IEN_RXDATAV); USART_IntEnable(obj->spi.spi, USART_IEN_RXDATAV);
NVIC_EnableIRQ(IRQvector); NVIC_EnableIRQ(IRQvector);
} } else {
else {
NVIC_SetVector(IRQvector, handler); NVIC_SetVector(IRQvector, handler);
USART_IntDisable(obj->spi.spi, USART_IEN_RXDATAV); USART_IntDisable(obj->spi.spi, USART_IEN_RXDATAV);
NVIC_DisableIRQ(IRQvector); NVIC_DisableIRQ(IRQvector);
@ -633,7 +634,8 @@ void transferComplete(unsigned int channel, bool primary, void *user)
* *
* return value: whether the channels were acquired successfully (true) or not. * return value: whether the channels were acquired successfully (true) or not.
******************************************/ ******************************************/
bool spi_allocate_dma(spi_t *obj) { bool spi_allocate_dma(spi_t *obj)
{
int dmaChannelIn, dmaChannelOut; int dmaChannelIn, dmaChannelOut;
dmaChannelIn = dma_channel_allocate(DMA_CAP_NONE); dmaChannelIn = dma_channel_allocate(DMA_CAP_NONE);
if (dmaChannelIn == DMA_ERROR_OUT_OF_CHANNELS) { if (dmaChannelIn == DMA_ERROR_OUT_OF_CHANNELS) {
@ -759,7 +761,8 @@ static void spi_master_dma_channel_setup(spi_t *obj, void* callback)
* * tx_length: how many bytes will get sent. * * tx_length: how many bytes will get sent.
* * rx_length: how many bytes will get received. If > tx_length, TX will get padded with n lower bits of SPI_FILL_WORD. * * rx_length: how many bytes will get received. If > tx_length, TX will get padded with n lower bits of SPI_FILL_WORD.
******************************************/ ******************************************/
static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_length, int rx_length) { static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_length, int rx_length)
{
/* DMA descriptors */ /* DMA descriptors */
DMA_CfgDescr_TypeDef rxDescrCfg; DMA_CfgDescr_TypeDef rxDescrCfg;
DMA_CfgDescr_TypeDef txDescrCfg; DMA_CfgDescr_TypeDef txDescrCfg;
@ -863,7 +866,8 @@ static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_leng
* If the previous transfer has kept the channel, that channel will continue to get used. * If the previous transfer has kept the channel, that channel will continue to get used.
* *
********************************************************************/ ********************************************************************/
void spi_master_transfer_dma(spi_t *obj, void *txdata, void *rxdata, int tx_length, int rx_length, void* cb, DMAUsage hint) { void spi_master_transfer_dma(spi_t *obj, void *txdata, void *rxdata, int tx_length, int rx_length, void* cb, DMAUsage hint)
{
/* Init DMA here to include it in the power figure */ /* Init DMA here to include it in the power figure */
dma_init(); dma_init();
/* If the DMA channels are already allocated, we can assume they have been setup already */ /* If the DMA channels are already allocated, we can assume they have been setup already */
@ -910,7 +914,8 @@ void spi_master_transfer_dma(spi_t *obj, void *txdata, void *rxdata, int tx_leng
* @param[in] handler SPI interrupt handler * @param[in] handler SPI interrupt handler
* @param[in] hint A suggestion for how to use DMA with this transfer * @param[in] hint A suggestion for how to use DMA with this transfer
*/ */
void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) { void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
if( spi_active(obj) ) return; if( spi_active(obj) ) return;
/* update fill word if on 9-bit frame size */ /* update fill word if on 9-bit frame size */
@ -953,7 +958,8 @@ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_
* return: event mask. Currently only 0 or SPI_EVENT_COMPLETE upon transfer completion. * return: event mask. Currently only 0 or SPI_EVENT_COMPLETE upon transfer completion.
* *
********************************************************************/ ********************************************************************/
uint32_t spi_irq_handler_asynch(spi_t* obj) { uint32_t spi_irq_handler_asynch(spi_t* obj)
{
/* Determine whether the current scenario is DMA or IRQ, and act accordingly */ /* Determine whether the current scenario is DMA or IRQ, and act accordingly */
@ -1005,8 +1011,7 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) {
&fill_word, // When there is nothing to transmit, point to static fill word &fill_word, // When there is nothing to transmit, point to static fill word
(length_diff / 2) - 1); (length_diff / 2) - 1);
} }
} } else return 0;
else return 0;
} }
/* If there is still a TX transfer ongoing (tx_length > rx_length), wait for it to finish */ /* If there is still a TX transfer ongoing (tx_length > rx_length), wait for it to finish */
@ -1054,7 +1059,8 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) {
* *
* @param obj The SPI peripheral to stop * @param obj The SPI peripheral to stop
*/ */
void spi_abort_asynch(spi_t *obj) { void spi_abort_asynch(spi_t *obj)
{
// If we're not currently transferring, then there's nothing to do here // If we're not currently transferring, then there's nothing to do here
if(spi_active(obj) != 0) return; if(spi_active(obj) != 0) return;