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cosmetic changes: apply mbed coding style to Silicon Labs HAL.

pull/1130/head
Steven Cooreman 2015-05-22 10:47:37 +02:00
parent e8ff8e7629
commit 2c55311cfb
31 changed files with 1455 additions and 1423 deletions
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232
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.c
View File

@ -48,7 +48,7 @@ const PinMap PinMap_I2C_SCL[] = {
{PF1, I2C_0, 5},
{PE13, I2C_0, 6},
/* I2C1 */
/* I2C1 */
{PC5, I2C_1, 0},
{PB12, I2C_1, 1},
{PE1, I2C_1, 2},
@ -68,7 +68,7 @@ const PinMap PinMap_I2C_SDA[] = {
{PF0, I2C_0, 5},
{PE12, I2C_0, 6},
/* I2C1 */
/* I2C1 */
{PC4, I2C_1, 0},
{PB11, I2C_1, 1},
{PE0, I2C_1, 2},
@ -87,134 +87,134 @@ const PinMap PinMap_PWM[] = {
/*************SPI**************/
const PinMap PinMap_SPI_MOSI[] = {
/* USART0 */
{PE10, SPI_0, 0},
{PE7, SPI_0, 1},
{PC11, SPI_0, 2},
{PC0, SPI_0, 5},
/* USART1 */
{PD0, SPI_1, 1},
{PD7, SPI_1, 2},
/* USART2 */
{PC2, SPI_2, 0},
{PB3, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE10, SPI_0, 0},
{PE7, SPI_0, 1},
{PC11, SPI_0, 2},
{PC0, SPI_0, 5},
/* USART1 */
{PD0, SPI_1, 1},
{PD7, SPI_1, 2},
/* USART2 */
{PC2, SPI_2, 0},
{PB3, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_MISO[] = {
/* USART0 */
{PE11, SPI_0, 0},
{PE6, SPI_0, 1},
{PC10, SPI_0, 2},
{PC1, SPI_0, 5},
/* USART1 */
{PD1, SPI_1, 1},
{PD6, SPI_1, 2},
/* USART2 */
{PC3, SPI_2, 0},
{PB4, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE11, SPI_0, 0},
{PE6, SPI_0, 1},
{PC10, SPI_0, 2},
{PC1, SPI_0, 5},
/* USART1 */
{PD1, SPI_1, 1},
{PD6, SPI_1, 2},
/* USART2 */
{PC3, SPI_2, 0},
{PB4, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CLK[] = {
/* USART0 */
{PE12, SPI_0, 0},
{PE5, SPI_0, 1},
{PC9, SPI_0, 2},
{PB13, SPI_0, 5},
/* USART1 */
{PD2, SPI_1, 1},
{PF0, SPI_1, 2},
/* USART2 */
{PC4, SPI_2, 0},
{PB5, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE12, SPI_0, 0},
{PE5, SPI_0, 1},
{PC9, SPI_0, 2},
{PB13, SPI_0, 5},
/* USART1 */
{PD2, SPI_1, 1},
{PF0, SPI_1, 2},
/* USART2 */
{PC4, SPI_2, 0},
{PB5, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CS[] = {
/* USART0 */
{PE13, SPI_0, 0},
{PE4, SPI_0, 1},
{PC8, SPI_0, 2},
{PB14, SPI_0, 5},
/* USART1 */
{PD3, SPI_1, 1},
{PF1, SPI_1, 2},
/* USART2 */
{PC5, SPI_2, 0},
{PB6, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE13, SPI_0, 0},
{PE4, SPI_0, 1},
{PC8, SPI_0, 2},
{PB14, SPI_0, 5},
/* USART1 */
{PD3, SPI_1, 1},
{PF1, SPI_1, 2},
/* USART2 */
{PC5, SPI_2, 0},
{PB6, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
/************UART**************/
const PinMap PinMap_UART_TX[] = {
/* UART0 */
{PF6, UART_0, 0},
{PE0, UART_0, 1},
/* UART1 */
{PF10, UART_1, 1},
{PB9, UART_1, 2},
{PE2, UART_1, 3},
/* USART0 */
{PE10, USART_0, 0},
{PE7, USART_0, 1},
{PC11, USART_0, 2},
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD0, USART_1, 1},
{PD7, USART_1, 2},
/* USART2 */
{PC2, USART_2, 0},
{PB3, USART_2, 1},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PE14, LEUART_0, 2},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* LEUART1 */
{PC6, LEUART_1, 0},
{PA5, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
/* UART0 */
{PF6, UART_0, 0},
{PE0, UART_0, 1},
/* UART1 */
{PF10, UART_1, 1},
{PB9, UART_1, 2},
{PE2, UART_1, 3},
/* USART0 */
{PE10, USART_0, 0},
{PE7, USART_0, 1},
{PC11, USART_0, 2},
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD0, USART_1, 1},
{PD7, USART_1, 2},
/* USART2 */
{PC2, USART_2, 0},
{PB3, USART_2, 1},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PE14, LEUART_0, 2},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* LEUART1 */
{PC6, LEUART_1, 0},
{PA5, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_UART_RX[] = {
/* UART0 */
{PF7, UART_0, 0},
{PE1, UART_0, 1},
/* UART1 */
{PF11, UART_1, 1},
{PB10, UART_1, 2},
{PE3, UART_1, 3},
/* USART0 */
{PE11, USART_0, 0},
{PE6, USART_0, 1},
{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD1, USART_1, 1},
{PD6, USART_1, 2},
/* USART2 */
{PC3, USART_2, 0},
{PB4, USART_2, 1},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PE15, LEUART_0, 2},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* LEUART1 */
{PC7, LEUART_1, 0},
{PA6, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
/* UART0 */
{PF7, UART_0, 0},
{PE1, UART_0, 1},
/* UART1 */
{PF11, UART_1, 1},
{PB10, UART_1, 2},
{PE3, UART_1, 3},
/* USART0 */
{PE11, USART_0, 0},
{PE6, USART_0, 1},
{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD1, USART_1, 1},
{PD6, USART_1, 2},
/* USART2 */
{PC3, USART_2, 0},
{PB4, USART_2, 1},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PE15, LEUART_0, 2},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* LEUART1 */
{PC7, LEUART_1, 0},
{PA6, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
};

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralNames.h
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@ -24,7 +24,7 @@ extern "C" {
#endif
typedef enum {
ADC_0 = ADC0_BASE
ADC_0 = ADC0_BASE
} ADCName;
typedef enum {

178
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.c
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@ -60,109 +60,109 @@ const PinMap PinMap_PWM[] = {
/*************SPI**************/
const PinMap PinMap_SPI_MOSI[] = {
/* USART0 */
{PE10, SPI_0, 0},
//{NC, SPI_0, 2}, /* SPI_0 loc2 is not bonded */
{PE13, SPI_0, 3},
{PB7, SPI_0, 4},
/* USART1 */
{PC0, SPI_1, 0},
{PD7, SPI_1, 3},
{PF2, SPI_1, 4},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE10, SPI_0, 0},
//{NC, SPI_0, 2}, /* SPI_0 loc2 is not bonded */
{PE13, SPI_0, 3},
{PB7, SPI_0, 4},
/* USART1 */
{PC0, SPI_1, 0},
{PD7, SPI_1, 3},
{PF2, SPI_1, 4},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_MISO[] = {
/* USART0 */
{PE11, SPI_0, 0},
{PC10, SPI_0, 2},
{PE12, SPI_0, 3},
{PB8, SPI_0, 4},
/* USART1 */
{PC1, SPI_1, 0},
{PD6, SPI_1, 3},
{PA0, SPI_1, 4},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE11, SPI_0, 0},
{PC10, SPI_0, 2},
{PE12, SPI_0, 3},
{PB8, SPI_0, 4},
/* USART1 */
{PC1, SPI_1, 0},
{PD6, SPI_1, 3},
{PA0, SPI_1, 4},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CLK[] = {
/* USART0 */
{PE12, SPI_0, 0},
{PC9, SPI_0, 2},
//{PC15, SPI_0, 3}, /* Conflict with SPI_0 loc4 */
{PB13, SPI_0, 4},
/* USART1 */
{PB7, SPI_1, 0},
{PC15, SPI_1, 3},
{PB11, SPI_1, 4},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE12, SPI_0, 0},
{PC9, SPI_0, 2},
//{PC15, SPI_0, 3}, /* Conflict with SPI_0 loc4 */
{PB13, SPI_0, 4},
/* USART1 */
{PB7, SPI_1, 0},
{PC15, SPI_1, 3},
{PB11, SPI_1, 4},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CS[] = {
/* USART0 */
{PE13, SPI_0, 0},
{PC8, SPI_0, 2},
//{PC14, SPI_0, 3}, /* Conflict with SPI_1 loc3 */
{PB14, SPI_0, 4},
/* USART1 */
{PB8, SPI_1, 0},
{PC14, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE13, SPI_0, 0},
{PC8, SPI_0, 2},
//{PC14, SPI_0, 3}, /* Conflict with SPI_1 loc3 */
{PB14, SPI_0, 4},
/* USART1 */
{PB8, SPI_1, 0},
{PC14, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
};
/************UART**************/
const PinMap PinMap_UART_TX[] = {
/* USART0 */
{PE10, USART_0, 0},
//{NC, USART_0, 2}, /* USART_0 loc2 is not bonded */
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD7, USART_1, 3},
{PF2, USART_1, 4},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PF0, LEUART_0, 3},
{PC14, LEUART_0, 5},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE10, USART_0, 0},
//{NC, USART_0, 2}, /* USART_0 loc2 is not bonded */
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD7, USART_1, 3},
{PF2, USART_1, 4},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PF0, LEUART_0, 3},
{PC14, LEUART_0, 5},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_UART_RX[] = {
/* USART0 */
{PE11, USART_0, 0},
//{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD6, USART_1, 3},
{PA0, USART_1, 4},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PF1, LEUART_0, 3},
{PC15, LEUART_0, 5},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE11, USART_0, 0},
//{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD6, USART_1, 3},
{PA0, USART_1, 4},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PF1, LEUART_0, 3},
{PC15, LEUART_0, 5},
/* Not connected */
{NC , NC , NC}
};

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device.h
View File

@ -45,7 +45,7 @@
#define DEVICE_PWMOUT 1
#define DEVICE_SLEEP 1
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_LOWPOWERTIMER 1

232
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.c
View File

@ -48,7 +48,7 @@ const PinMap PinMap_I2C_SCL[] = {
{PF1, I2C_0, 5},
{PE13, I2C_0, 6},
/* I2C1 */
/* I2C1 */
{PC5, I2C_1, 0},
{PB12, I2C_1, 1},
{PE1, I2C_1, 2},
@ -68,7 +68,7 @@ const PinMap PinMap_I2C_SDA[] = {
{PF0, I2C_0, 5},
{PE12, I2C_0, 6},
/* I2C1 */
/* I2C1 */
{PC4, I2C_1, 0},
{PB11, I2C_1, 1},
{PE0, I2C_1, 2},
@ -87,134 +87,134 @@ const PinMap PinMap_PWM[] = {
/*************SPI**************/
const PinMap PinMap_SPI_MOSI[] = {
/* USART0 */
{PE10, SPI_0, 0},
{PE7, SPI_0, 1},
{PC11, SPI_0, 2},
{PC0, SPI_0, 5},
/* USART1 */
{PD0, SPI_1, 1},
{PD7, SPI_1, 2},
/* USART2 */
{PC2, SPI_2, 0},
{PB3, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE10, SPI_0, 0},
{PE7, SPI_0, 1},
{PC11, SPI_0, 2},
{PC0, SPI_0, 5},
/* USART1 */
{PD0, SPI_1, 1},
{PD7, SPI_1, 2},
/* USART2 */
{PC2, SPI_2, 0},
{PB3, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_MISO[] = {
/* USART0 */
{PE11, SPI_0, 0},
{PE6, SPI_0, 1},
{PC10, SPI_0, 2},
{PC1, SPI_0, 5},
/* USART1 */
{PD1, SPI_1, 1},
{PD6, SPI_1, 2},
/* USART2 */
{PC3, SPI_2, 0},
{PB4, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE11, SPI_0, 0},
{PE6, SPI_0, 1},
{PC10, SPI_0, 2},
{PC1, SPI_0, 5},
/* USART1 */
{PD1, SPI_1, 1},
{PD6, SPI_1, 2},
/* USART2 */
{PC3, SPI_2, 0},
{PB4, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CLK[] = {
/* USART0 */
{PE12, SPI_0, 0},
{PE5, SPI_0, 1},
{PC9, SPI_0, 2},
{PB13, SPI_0, 5},
/* USART1 */
{PD2, SPI_1, 1},
{PF0, SPI_1, 2},
/* USART2 */
{PC4, SPI_2, 0},
{PB5, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE12, SPI_0, 0},
{PE5, SPI_0, 1},
{PC9, SPI_0, 2},
{PB13, SPI_0, 5},
/* USART1 */
{PD2, SPI_1, 1},
{PF0, SPI_1, 2},
/* USART2 */
{PC4, SPI_2, 0},
{PB5, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CS[] = {
/* USART0 */
{PE13, SPI_0, 0},
{PE4, SPI_0, 1},
{PC8, SPI_0, 2},
{PB14, SPI_0, 5},
/* USART1 */
{PD3, SPI_1, 1},
{PF1, SPI_1, 2},
/* USART2 */
{PC5, SPI_2, 0},
{PB6, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE13, SPI_0, 0},
{PE4, SPI_0, 1},
{PC8, SPI_0, 2},
{PB14, SPI_0, 5},
/* USART1 */
{PD3, SPI_1, 1},
{PF1, SPI_1, 2},
/* USART2 */
{PC5, SPI_2, 0},
{PB6, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
/************UART**************/
const PinMap PinMap_UART_TX[] = {
/* UART0 */
{PF6, UART_0, 0},
{PE0, UART_0, 1},
/* UART1 */
{PF10, UART_1, 1},
{PB9, UART_1, 2},
{PE2, UART_1, 3},
/* USART0 */
{PE10, USART_0, 0},
{PE7, USART_0, 1},
{PC11, USART_0, 2},
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD0, USART_1, 1},
{PD7, USART_1, 2},
/* USART2 */
{PC2, USART_2, 0},
{PB3, USART_2, 1},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PE14, LEUART_0, 2},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* LEUART1 */
{PC6, LEUART_1, 0},
{PA5, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
/* UART0 */
{PF6, UART_0, 0},
{PE0, UART_0, 1},
/* UART1 */
{PF10, UART_1, 1},
{PB9, UART_1, 2},
{PE2, UART_1, 3},
/* USART0 */
{PE10, USART_0, 0},
{PE7, USART_0, 1},
{PC11, USART_0, 2},
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD0, USART_1, 1},
{PD7, USART_1, 2},
/* USART2 */
{PC2, USART_2, 0},
{PB3, USART_2, 1},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PE14, LEUART_0, 2},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* LEUART1 */
{PC6, LEUART_1, 0},
{PA5, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_UART_RX[] = {
/* UART0 */
{PF7, UART_0, 0},
{PE1, UART_0, 1},
/* UART1 */
{PF11, UART_1, 1},
{PB10, UART_1, 2},
{PE3, UART_1, 3},
/* USART0 */
{PE11, USART_0, 0},
{PE6, USART_0, 1},
{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD1, USART_1, 1},
{PD6, USART_1, 2},
/* USART2 */
{PC3, USART_2, 0},
{PB4, USART_2, 1},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PE15, LEUART_0, 2},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* LEUART1 */
{PC7, LEUART_1, 0},
{PA6, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
/* UART0 */
{PF7, UART_0, 0},
{PE1, UART_0, 1},
/* UART1 */
{PF11, UART_1, 1},
{PB10, UART_1, 2},
{PE3, UART_1, 3},
/* USART0 */
{PE11, USART_0, 0},
{PE6, USART_0, 1},
{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD1, USART_1, 1},
{PD6, USART_1, 2},
/* USART2 */
{PC3, USART_2, 0},
{PB4, USART_2, 1},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PE15, LEUART_0, 2},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* LEUART1 */
{PC7, LEUART_1, 0},
{PA6, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
};

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.h
View File

@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H

4
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h
View File

@ -92,8 +92,8 @@ typedef enum {
/* mbed modes:
* PullUp, PullDown, PullNone, OpenDrain
*
* mbed default digital input mode:
* PullDefault
* mbed default digital input mode:
* PullDefault
*
* mbed default digital output mode:
* PullNone

232
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.c
View File

@ -48,7 +48,7 @@ const PinMap PinMap_I2C_SCL[] = {
{PF1, I2C_0, 5},
{PE13, I2C_0, 6},
/* I2C1 */
/* I2C1 */
{PC5, I2C_1, 0},
{PB12, I2C_1, 1},
{PE1, I2C_1, 2},
@ -68,7 +68,7 @@ const PinMap PinMap_I2C_SDA[] = {
{PF0, I2C_0, 5},
{PE12, I2C_0, 6},
/* I2C1 */
/* I2C1 */
{PC4, I2C_1, 0},
{PB11, I2C_1, 1},
{PE0, I2C_1, 2},
@ -87,134 +87,134 @@ const PinMap PinMap_PWM[] = {
/*************SPI**************/
const PinMap PinMap_SPI_MOSI[] = {
/* USART0 */
{PE10, SPI_0, 0},
{PE7, SPI_0, 1},
{PC11, SPI_0, 2},
{PC0, SPI_0, 5},
/* USART1 */
{PD0, SPI_1, 1},
{PD7, SPI_1, 2},
/* USART2 */
{PC2, SPI_2, 0},
{PB3, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE10, SPI_0, 0},
{PE7, SPI_0, 1},
{PC11, SPI_0, 2},
{PC0, SPI_0, 5},
/* USART1 */
{PD0, SPI_1, 1},
{PD7, SPI_1, 2},
/* USART2 */
{PC2, SPI_2, 0},
{PB3, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_MISO[] = {
/* USART0 */
{PE11, SPI_0, 0},
{PE6, SPI_0, 1},
{PC10, SPI_0, 2},
{PC1, SPI_0, 5},
/* USART1 */
{PD1, SPI_1, 1},
{PD6, SPI_1, 2},
/* USART2 */
{PC3, SPI_2, 0},
{PB4, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE11, SPI_0, 0},
{PE6, SPI_0, 1},
{PC10, SPI_0, 2},
{PC1, SPI_0, 5},
/* USART1 */
{PD1, SPI_1, 1},
{PD6, SPI_1, 2},
/* USART2 */
{PC3, SPI_2, 0},
{PB4, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CLK[] = {
/* USART0 */
{PE12, SPI_0, 0},
{PE5, SPI_0, 1},
{PC9, SPI_0, 2},
{PB13, SPI_0, 5},
/* USART1 */
{PD2, SPI_1, 1},
{PF0, SPI_1, 2},
/* USART2 */
{PC4, SPI_2, 0},
{PB5, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE12, SPI_0, 0},
{PE5, SPI_0, 1},
{PC9, SPI_0, 2},
{PB13, SPI_0, 5},
/* USART1 */
{PD2, SPI_1, 1},
{PF0, SPI_1, 2},
/* USART2 */
{PC4, SPI_2, 0},
{PB5, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CS[] = {
/* USART0 */
{PE13, SPI_0, 0},
{PE4, SPI_0, 1},
{PC8, SPI_0, 2},
{PB14, SPI_0, 5},
/* USART1 */
{PD3, SPI_1, 1},
{PF1, SPI_1, 2},
/* USART2 */
{PC5, SPI_2, 0},
{PB6, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
/* USART0 */
{PE13, SPI_0, 0},
{PE4, SPI_0, 1},
{PC8, SPI_0, 2},
{PB14, SPI_0, 5},
/* USART1 */
{PD3, SPI_1, 1},
{PF1, SPI_1, 2},
/* USART2 */
{PC5, SPI_2, 0},
{PB6, SPI_2, 1},
/* Not connected */
{NC , NC , NC}
};
/************UART**************/
const PinMap PinMap_UART_TX[] = {
/* UART0 */
{PF6, UART_0, 0},
{PE0, UART_0, 1},
/* UART1 */
{PF10, UART_1, 1},
{PB9, UART_1, 2},
{PE2, UART_1, 3},
/* USART0 */
{PE10, USART_0, 0},
{PE7, USART_0, 1},
{PC11, USART_0, 2},
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD0, USART_1, 1},
{PD7, USART_1, 2},
/* USART2 */
{PC2, USART_2, 0},
{PB3, USART_2, 1},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PE14, LEUART_0, 2},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* LEUART1 */
{PC6, LEUART_1, 0},
{PA5, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
/* UART0 */
{PF6, UART_0, 0},
{PE0, UART_0, 1},
/* UART1 */
{PF10, UART_1, 1},
{PB9, UART_1, 2},
{PE2, UART_1, 3},
/* USART0 */
{PE10, USART_0, 0},
{PE7, USART_0, 1},
{PC11, USART_0, 2},
{PE13, USART_0, 3},
{PB7, USART_0, 4},
/* USART1 */
{PC0, USART_1, 0},
{PD0, USART_1, 1},
{PD7, USART_1, 2},
/* USART2 */
{PC2, USART_2, 0},
{PB3, USART_2, 1},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PE14, LEUART_0, 2},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* LEUART1 */
{PC6, LEUART_1, 0},
{PA5, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_UART_RX[] = {
/* UART0 */
{PF7, UART_0, 0},
{PE1, UART_0, 1},
/* UART1 */
{PF11, UART_1, 1},
{PB10, UART_1, 2},
{PE3, UART_1, 3},
/* USART0 */
{PE11, USART_0, 0},
{PE6, USART_0, 1},
{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD1, USART_1, 1},
{PD6, USART_1, 2},
/* USART2 */
{PC3, USART_2, 0},
{PB4, USART_2, 1},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PE15, LEUART_0, 2},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* LEUART1 */
{PC7, LEUART_1, 0},
{PA6, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
/* UART0 */
{PF7, UART_0, 0},
{PE1, UART_0, 1},
/* UART1 */
{PF11, UART_1, 1},
{PB10, UART_1, 2},
{PE3, UART_1, 3},
/* USART0 */
{PE11, USART_0, 0},
{PE6, USART_0, 1},
{PC10, USART_0, 2},
{PE12, USART_0, 3},
{PB8, USART_0, 4},
/* USART1 */
{PC1, USART_1, 0},
{PD1, USART_1, 1},
{PD6, USART_1, 2},
/* USART2 */
{PC3, USART_2, 0},
{PB4, USART_2, 1},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PE15, LEUART_0, 2},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* LEUART1 */
{PC7, LEUART_1, 0},
{PA6, LEUART_1, 1},
/* Not connected */
{NC , NC , NC}
};

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.h
View File

@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H

4
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h
View File

@ -92,8 +92,8 @@ typedef enum {
/* mbed modes:
* PullUp, PullDown, PullNone, OpenDrain
*
* mbed default digital input mode:
* PullDefault
* mbed default digital input mode:
* PullDefault
*
* mbed default digital output mode:
* PullNone

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralNames.h
View File

@ -24,7 +24,7 @@ extern "C" {
#endif
typedef enum {
ADC_0 = ADC0_BASE
ADC_0 = ADC0_BASE
} ADCName;
typedef enum {

80
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.c
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@ -60,60 +60,60 @@ const PinMap PinMap_PWM[] = {
/*************SPI**************/
const PinMap PinMap_SPI_MOSI[] = {
/* USART1 */
{PC0, SPI_1, 0},
{PD7, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
/* USART1 */
{PC0, SPI_1, 0},
{PD7, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_MISO[] = {
/* USART1 */
{PC1, SPI_1, 0},
{PD6, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
/* USART1 */
{PC1, SPI_1, 0},
{PD6, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CLK[] = {
/* USART1 */
{PB7, SPI_1, 0},
{PC15, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
/* USART1 */
{PB7, SPI_1, 0},
{PC15, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_SPI_CS[] = {
/* USART1 */
{PB8, SPI_1, 0},
{PC14, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
/* USART1 */
{PB8, SPI_1, 0},
{PC14, SPI_1, 3},
/* Not connected */
{NC , NC , NC}
};
/************UART**************/
const PinMap PinMap_UART_TX[] = {
/* USART1 */
{PC0, USART_1, 0},
{PD7, USART_1, 3},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* Not connected */
{NC , NC , NC}
/* USART1 */
{PC0, USART_1, 0},
{PD7, USART_1, 3},
/* LEUART0 */
{PD4, LEUART_0, 0},
{PB13, LEUART_0, 1},
{PF0, LEUART_0, 3},
{PF2, LEUART_0, 4},
/* Not connected */
{NC , NC , NC}
};
const PinMap PinMap_UART_RX[] = {
/* USART1 */
{PC1, USART_1, 0},
{PD6, USART_1, 3},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* Not connected */
{NC , NC , NC}
/* USART1 */
{PC1, USART_1, 0},
{PD6, USART_1, 3},
/* LEUART0 */
{PD5, LEUART_0, 0},
{PB14, LEUART_0, 1},
{PF1, LEUART_0, 3},
{PA0, LEUART_0, 4},
/* Not connected */
{NC , NC , NC}
};

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device.h
View File

@ -45,7 +45,7 @@
#define DEVICE_PWMOUT 1
#define DEVICE_SLEEP 1
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_LOWPOWERTIMER 1

6
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c
View File

@ -52,12 +52,12 @@ void analogin_init(analogin_t *obj, PinName pin)
if (!adc_initialized) {
/* Turn on the clock */
CMU_ClockEnable(cmuClock_ADC0, true);
/* Init with default settings */
ADC_Init_TypeDef init = ADC_INIT_DEFAULT;
init.prescale = 4;
ADC_Init(obj->adc, &init);
/* Init for single conversion use */
ADC_InitSingle_TypeDef singleInit = ADC_INITSINGLE_DEFAULT;
@ -67,7 +67,7 @@ void analogin_init(analogin_t *obj, PinName pin)
singleInit.acqTime = adcAcqTime32;
ADC_InitSingle(obj->adc, &singleInit);
adc_initialized = 1;
}
}

27
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c
View File

@ -37,22 +37,23 @@ void analogout_preinit(dac_t *obj, PinName pin)
{
obj->dac = (DAC_TypeDef *) pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT((int) obj->dac != NC);
obj->channel = pin_location(pin, PinMap_DAC);
MBED_ASSERT((int) obj->channel != NC);
}
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
static uint8_t dac_initialized = 0;
/* init in-memory structure */
analogout_preinit(obj, pin);
if (!dac_initialized) {
/* Initialize the DAC. Will disable both DAC channels, so should only be done once */
/* Use default settings */
CMU_ClockEnable(cmuClock_DAC0, true);
DAC_Init_TypeDef init = DAC_INIT_DEFAULT;
/* Calculate the DAC clock prescaler value that will result in a DAC clock
@ -83,7 +84,8 @@ void analogout_pins_enable(dac_t *obj, uint8_t enable)
//not avail for EFM32
}
static inline void dac_write(dac_t *obj, int value) {
static inline void dac_write(dac_t *obj, int value)
{
switch (obj->channel) {
case 0:
obj->dac->CH0DATA = value;
@ -94,7 +96,8 @@ static inline void dac_write(dac_t *obj, int value) {
}
}
static inline int dac_read(dac_t *obj) {
static inline int dac_read(dac_t *obj)
{
switch (obj->channel) {
case 0:
return obj->dac->CH0DATA;
@ -109,23 +112,27 @@ static inline int dac_read(dac_t *obj) {
}
}
void analogout_write(dac_t *obj, float value) {
void analogout_write(dac_t *obj, float value)
{
/* We multiply the float value with 0xFFF because the DAC has 12-bit resolution.
* Ie. accepts values between 0 and 0xFFF (4096). */
dac_write(obj, value*0xFFF);
}
void analogout_write_u16(dac_t *obj, uint16_t value) {
void analogout_write_u16(dac_t *obj, uint16_t value)
{
/* The DAC has 12 bit resolution, so we remove the 4 least significant bits */
dac_write(obj, value >> 4);
}
float analogout_read(dac_t *obj) {
float analogout_read(dac_t *obj)
{
/* dac_read returns a number between 0 and 0xFFF. Division gives us a float between 0 and 1 */
return dac_read(obj)/(float)0xFFF;
}
uint16_t analogout_read_u16(dac_t *obj) {
uint16_t analogout_read_u16(dac_t *obj)
{
/* dac_read returns a number with 12 significant digits,
* so we shift in 0s from right to make it a 16 bit number */
return dac_read(obj) << 4;

74
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c
View File

@ -39,55 +39,51 @@ bool enabled = false;
void dma_init(void)
{
if (enabled) return;
DMA_Init_TypeDef dmaInit;
if (enabled) return;
DMA_Init_TypeDef dmaInit;
CMU_ClockEnable(cmuClock_DMA, true);
CMU_ClockEnable(cmuClock_HFPER, true);
CMU_ClockEnable(cmuClock_DMA, true);
CMU_ClockEnable(cmuClock_HFPER, true);
/* Configure general DMA issues */
dmaInit.hprot = 0;
dmaInit.controlBlock = dmaControlBlock;
DMA_Init(&dmaInit);
enabled = true;
/* Configure general DMA issues */
dmaInit.hprot = 0;
dmaInit.controlBlock = dmaControlBlock;
DMA_Init(&dmaInit);
enabled = true;
}
int dma_channel_allocate(uint32_t capabilities)
{
int i;
// Check if 2d copy is required
if (DMA_CAP_2DCOPY & capabilities)
{
if (channels & 1)
{
// Channel already in use
return DMA_ERROR_OUT_OF_CHANNELS;
} else {
channels |= 1 << 0;
return 0;
int i;
// Check if 2d copy is required
if (DMA_CAP_2DCOPY & capabilities) {
if (channels & 1) {
// Channel already in use
return DMA_ERROR_OUT_OF_CHANNELS;
} else {
channels |= 1 << 0;
return 0;
}
}
}
for (i = 1; i < DMA_CHAN_COUNT; i++)
{
if ((channels & (1 << i)) == 0)
{
// Channel available
channels |= 1 << i;
return i;
for (i = 1; i < DMA_CHAN_COUNT; i++) {
if ((channels & (1 << i)) == 0) {
// Channel available
channels |= 1 << i;
return i;
}
}
}
// Check if channel 0 is available
if ((channels & 1 ) == 0) {
channels |= 1 << 0;
return 0;
}
// Couldn't find a channel.
return DMA_ERROR_OUT_OF_CHANNELS;
// Check if channel 0 is available
if ((channels & 1 ) == 0) {
channels |= 1 << 0;
return 0;
}
// Couldn't find a channel.
return DMA_ERROR_OUT_OF_CHANNELS;
}
int dma_channel_free(int channelid)
int dma_channel_free(int channelid)
{
channels &= ~(1 << channelid);
return 0;
channels &= ~(1 << channelid);
return 0;
}

6
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h
View File

@ -46,9 +46,9 @@ extern "C" {
#endif
typedef struct {
DMAUsage dmaUsageState;
int dmaChannel;
DMA_CB_TypeDef dmaCallback;
DMAUsage dmaUsageState;
int dmaChannel;
DMA_CB_TypeDef dmaCallback;
} DMA_OPTIONS_t;
typedef void (*DMACallback)(void);

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c
View File

@ -59,7 +59,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
{
obj->mode = mode; // Update object
pin_mode(obj->pin, mode); // Update register
//Handle pullup for input
if(mode == InputPullUp) {
//Set DOUT

61
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c
View File

@ -37,9 +37,9 @@
#define GPIOINT_MASK2IDX(mask) (countTrailingZeros(mask))
__STATIC_INLINE uint32_t countTrailingZeros(uint32_t mask)
{
uint32_t zeros;
for(zeros=0; (zeros<32) && (0 == (mask&0x1)); zeros++, mask>>=1);
return zeros;
uint32_t zeros;
for(zeros=0; (zeros<32) && (0 == (mask&0x1)); zeros++, mask>>=1);
return zeros;
}
#else
#error Unsupported architecture.
@ -85,8 +85,8 @@ void gpio_irq_preinit(gpio_irq_t *obj, PinName pin)
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
/* Init pins */
gpio_irq_preinit(obj, pin);
/* Init pins */
gpio_irq_preinit(obj, pin);
/* Initialize GPIO interrupt dispatcher */
NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
NVIC_EnableIRQ(GPIO_ODD_IRQn);
@ -128,19 +128,19 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
/* Disable, set config and enable */
gpio_irq_disable(obj);
bool was_disabled = false;
if(GPIO->IEN == 0) was_disabled = true;
GPIO_IntConfig(obj->port, obj->pin, obj->risingEdge, obj->fallingEdge, obj->risingEdge || obj->fallingEdge);
if ((GPIO->IEN != 0) && (obj->risingEdge || obj->fallingEdge) && was_disabled) {
blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
}
}
inline void gpio_irq_enable(gpio_irq_t *obj)
{
if(GPIO->IEN == 0) blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
if(GPIO->IEN == 0) blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE);
GPIO_IntEnable(1 << obj->pin); // pin mask for pins to enable
}
@ -165,19 +165,18 @@ inline void gpio_irq_disable(gpio_irq_t *obj)
******************************************************************************/
static void GPIOINT_IRQDispatcher(uint32_t iflags)
{
uint32_t irqIdx;
uint32_t irqIdx;
/* check for all flags set in IF register */
while(iflags)
{
irqIdx = GPIOINT_MASK2IDX(iflags);
/* check for all flags set in IF register */
while(iflags) {
irqIdx = GPIOINT_MASK2IDX(iflags);
/* clear flag*/
iflags &= ~(1 << irqIdx);
/* clear flag*/
iflags &= ~(1 << irqIdx);
/* call user callback */
handle_interrupt_in(irqIdx);
}
/* call user callback */
handle_interrupt_in(irqIdx);
}
}
/***************************************************************************//**
@ -188,15 +187,15 @@ static void GPIOINT_IRQDispatcher(uint32_t iflags)
******************************************************************************/
void GPIO_EVEN_IRQHandler(void)
{
uint32_t iflags;
uint32_t iflags;
/* Get all even interrupts. */
iflags = GPIO_IntGetEnabled() & 0x00005555;
/* Get all even interrupts. */
iflags = GPIO_IntGetEnabled() & 0x00005555;
/* Clean only even interrupts. */
GPIO_IntClear(iflags);
/* Clean only even interrupts. */
GPIO_IntClear(iflags);
GPIOINT_IRQDispatcher(iflags);
GPIOINT_IRQDispatcher(iflags);
}
@ -208,15 +207,15 @@ void GPIO_EVEN_IRQHandler(void)
******************************************************************************/
void GPIO_ODD_IRQHandler(void)
{
uint32_t iflags;
uint32_t iflags;
/* Get all odd interrupts. */
iflags = GPIO_IntGetEnabled() & 0x0000AAAA;
/* Get all odd interrupts. */
iflags = GPIO_IntGetEnabled() & 0x0000AAAA;
/* Clean only even interrupts. */
GPIO_IntClear(iflags);
/* Clean only even interrupts. */
GPIO_IntClear(iflags);
GPIOINT_IRQDispatcher(iflags);
GPIOINT_IRQDispatcher(iflags);
}
#endif

3
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h
View File

@ -49,7 +49,8 @@ static inline int gpio_read(gpio_t *obj)
}
}
static inline int gpio_is_connected(const gpio_t *obj) {
static inline int gpio_is_connected(const gpio_t *obj)
{
return obj->pin != (PinName)NC;
}

197
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c
View File

@ -75,7 +75,7 @@ static CMU_Clock_TypeDef i2c_get_clock(i2c_t *obj)
#endif
#ifdef I2C1
case I2C_1:
clock = cmuClock_I2C1;
clock = cmuClock_I2C1;
break;
#endif
default:
@ -104,10 +104,10 @@ void i2c_preinit(i2c_t *obj, PinName sda, PinName scl)
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
/* Assign mbed pins */
i2c_preinit(obj, sda, scl);
i2c_preinit(obj, sda, scl);
/* Enable clock for the peripheral */
CMU_ClockEnable(i2c_get_clock(obj), true);
/* Enable clock for the peripheral */
CMU_ClockEnable(i2c_get_clock(obj), true);
/* Initializing the I2C */
/* Using default settings */
@ -137,7 +137,7 @@ void i2c_enable(i2c_t *obj, uint8_t enable)
if (obj->i2c.i2c->STATE & I2C_STATE_BUSY) {
obj->i2c.i2c->CMD = I2C_CMD_ABORT;
}
}
}
@ -222,14 +222,14 @@ int i2c_stop(i2c_t *obj)
/* Returns number of bytes read */
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int retval;
int retval;
i2c_start(obj);
retval = i2c_byte_write(obj, (address | 1));
if ((!retval) || (length == 0)) { //Write address with W flag (last bit 1)
obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
while(obj->i2c.i2c->STATE & I2C_STATE_BUSY); // Wait until the bus is done
obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
while(obj->i2c.i2c->STATE & I2C_STATE_BUSY); // Wait until the bus is done
return (retval == 0 ? I2C_ERROR_NO_SLAVE : 0); //NACK or error when writing adress. Return 0 as 0 bytes were read
}
int i = 0;
@ -344,10 +344,10 @@ int block_and_wait_for_ack(I2C_TypeDef *i2c)
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
if(enable_slave){
if(enable_slave) {
obj->i2c.i2c->CTRL |= _I2C_CTRL_SLAVE_MASK;
obj->i2c.i2c->CTRL |= _I2C_CTRL_AUTOACK_MASK; //Slave implementation assumes auto acking
}else{
} else {
obj->i2c.i2c->CTRL &= ~_I2C_CTRL_SLAVE_MASK;
obj->i2c.i2c->CTRL &= ~_I2C_CTRL_AUTOACK_MASK; //Master implementation ACKs manually
}
@ -356,19 +356,19 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave)
int i2c_slave_receive(i2c_t *obj)
{
if(obj->i2c.i2c->IF & I2C_IF_ADDR){
if(obj->i2c.i2c->IF & I2C_IF_ADDR) {
obj->i2c.i2c->IFC = I2C_IF_ADDR; //Clear interrupt
/*0x00 is the address for general write.
The address the master wrote is in RXDATA now
and reading it also frees the buffer for the next
write which can then be acked. */
if(obj->i2c.i2c->RXDATA == 0x00){
if(obj->i2c.i2c->RXDATA == 0x00) {
return WriteGeneral; //Read the address;
}
if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER){
if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER) {
return ReadAddressed;
}else{
} else {
return WriteAddressed;
}
}
@ -383,7 +383,7 @@ int i2c_slave_read(i2c_t *obj, char *data, int length)
for (count = 0; count < length; count++) {
data[count] = i2c_byte_read(obj, 0);
}
return count;
@ -426,128 +426,131 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
* @param handler The I2C IRQ handler to be set
* @param hint DMA hint usage
*/
void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
I2C_TransferReturn_TypeDef retval;
if(i2c_active(obj)) return;
void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
{
I2C_TransferReturn_TypeDef retval;
if(i2c_active(obj)) return;
if((tx_length == 0) && (rx_length == 0)) return;
// For now, we are assuming a solely interrupt-driven implementation.
// For now, we are assuming a solely interrupt-driven implementation.
// Store transfer config
obj->i2c.xfer.addr = address;
// Store transfer config
obj->i2c.xfer.addr = address;
// Some combination of tx_length and rx_length will tell us what to do
if((tx_length > 0) && (rx_length == 0)) {
obj->i2c.xfer.flags = I2C_FLAG_WRITE;
//Store buffer info
obj->i2c.xfer.buf[0].data = tx;
obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
} else if ((tx_length == 0) && (rx_length > 0)) {
obj->i2c.xfer.flags = I2C_FLAG_READ;
//Store buffer info
obj->i2c.xfer.buf[0].data = rx;
obj->i2c.xfer.buf[0].len = (uint16_t) rx_length;
} else if ((tx_length > 0) && (rx_length > 0)) {
obj->i2c.xfer.flags = I2C_FLAG_WRITE_READ;
//Store buffer info
obj->i2c.xfer.buf[0].data = tx;
obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
obj->i2c.xfer.buf[1].data = rx;
obj->i2c.xfer.buf[1].len = (uint16_t) rx_length;
}
// Some combination of tx_length and rx_length will tell us what to do
if((tx_length > 0) && (rx_length == 0)) {
obj->i2c.xfer.flags = I2C_FLAG_WRITE;
//Store buffer info
obj->i2c.xfer.buf[0].data = tx;
obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
} else if ((tx_length == 0) && (rx_length > 0)) {
obj->i2c.xfer.flags = I2C_FLAG_READ;
//Store buffer info
obj->i2c.xfer.buf[0].data = rx;
obj->i2c.xfer.buf[0].len = (uint16_t) rx_length;
} else if ((tx_length > 0) && (rx_length > 0)) {
obj->i2c.xfer.flags = I2C_FLAG_WRITE_READ;
//Store buffer info
obj->i2c.xfer.buf[0].data = tx;
obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
obj->i2c.xfer.buf[1].data = rx;
obj->i2c.xfer.buf[1].len = (uint16_t) rx_length;
}
if(address > 255) obj->i2c.xfer.flags |= I2C_FLAG_10BIT_ADDR;
if(address > 255) obj->i2c.xfer.flags |= I2C_FLAG_10BIT_ADDR;
// Store event flags
obj->i2c.events = event;
// Store event flags
obj->i2c.events = event;
// Enable interrupt
i2c_enable_interrupt(obj, handler, true);
// Enable interrupt
i2c_enable_interrupt(obj, handler, true);
// Kick off the transfer
retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer));
// Kick off the transfer
retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer));
if(retval == i2cTransferInProgress) {
blockSleepMode(EM1);
}
else {
// something happened, and the transfer did not go through
// So, we need to clean up
if(retval == i2cTransferInProgress) {
blockSleepMode(EM1);
} else {
// something happened, and the transfer did not go through
// So, we need to clean up
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
// Block until free
while(i2c_active(obj));
}
// Block until free
while(i2c_active(obj));
}
}
/** The asynchronous IRQ handler
* @param obj The I2C object which holds the transfer information
* @return Returns event flags if a transfer termination condition was met or 0 otherwise.
*/
uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
{
// For now, we are assuming a solely interrupt-driven implementation.
// For now, we are assuming a solely interrupt-driven implementation.
I2C_TransferReturn_TypeDef status = I2C_Transfer(obj->i2c.i2c);
switch(status) {
case i2cTransferInProgress:
// Still busy transferring, so let it.
return 0;
case i2cTransferDone:
// Transfer has completed
I2C_TransferReturn_TypeDef status = I2C_Transfer(obj->i2c.i2c);
switch(status) {
case i2cTransferInProgress:
// Still busy transferring, so let it.
return 0;
case i2cTransferDone:
// Transfer has completed
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
unblockSleepMode(EM1);
unblockSleepMode(EM1);
return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events;
case i2cTransferNack:
// A NACK has been received while an ACK was expected. This is usually because the slave did not respond to the address.
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events;
case i2cTransferNack:
// A NACK has been received while an ACK was expected. This is usually because the slave did not respond to the address.
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
unblockSleepMode(EM1);
unblockSleepMode(EM1);
return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events;
default:
// An error situation has arisen.
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events;
default:
// An error situation has arisen.
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
unblockSleepMode(EM1);
unblockSleepMode(EM1);
// return error
return I2C_EVENT_ERROR & obj->i2c.events;
}
// return error
return I2C_EVENT_ERROR & obj->i2c.events;
}
}
/** Attempts to determine if I2C peripheral is already in use.
* @param obj The I2C object
* @return non-zero if the I2C module is active or zero if it is not
*/
uint8_t i2c_active(i2c_t *obj) {
return (obj->i2c.i2c->STATE & I2C_STATE_BUSY);
uint8_t i2c_active(i2c_t *obj)
{
return (obj->i2c.i2c->STATE & I2C_STATE_BUSY);
}
/** Abort ongoing asynchronous transaction.
* @param obj The I2C object
*/
void i2c_abort_asynch(i2c_t *obj) {
// Do not deactivate I2C twice
if (!i2c_active(obj)) return;
void i2c_abort_asynch(i2c_t *obj)
{
// Do not deactivate I2C twice
if (!i2c_active(obj)) return;
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
// Disable interrupt
i2c_enable_interrupt(obj, 0, false);
// Abort
obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
// Abort
obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
// Block until free
while(i2c_active(obj));
// Block until free
while(i2c_active(obj));
unblockSleepMode(EM1);
unblockSleepMode(EM1);
}
#endif //DEVICE_I2C ASYNCH

60
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c
View File

@ -27,53 +27,57 @@ void lp_ticker_init()
rtc_set_comp0_handler((uint32_t)lp_ticker_irq_handler);
}
void lp_ticker_set_interrupt(timestamp_t timestamp) {
uint64_t timestamp_ticks;
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
uint64_t timestamp_ticks;
uint64_t current_ticks = RTC_CounterGet();
timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT));
/* calculate offset value */
timestamp_t offset = timestamp - current_time;
if(offset > 0xEFFFFFFF) offset = 100;
/* map offset to RTC value */
// ticks = offset * RTC frequency div 1000000
timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000;
// ticks = offset * RTC frequency div 1000000
timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000;
timestamp_ticks += current_ticks;
/* RTC has 24 bit resolution */
timestamp_ticks &= 0xFFFFFF;
/* RTC has 24 bit resolution */
timestamp_ticks &= 0xFFFFFF;
/* check for RTC limitation */
if((timestamp_ticks - RTC_CounterGet()) >= 0x800000) timestamp_ticks = RTC_CounterGet() + 2;
/* Set callback */
RTC_FreezeEnable(true);
RTC_CompareSet(0, (uint32_t)timestamp_ticks);
RTC_IntEnable(RTC_IF_COMP0);
RTC_FreezeEnable(false);
/* Set callback */
RTC_FreezeEnable(true);
RTC_CompareSet(0, (uint32_t)timestamp_ticks);
RTC_IntEnable(RTC_IF_COMP0);
RTC_FreezeEnable(false);
}
inline void lp_ticker_disable_interrupt() {
RTC_IntDisable(RTC_IF_COMP0);
inline void lp_ticker_disable_interrupt()
{
RTC_IntDisable(RTC_IF_COMP0);
}
inline void lp_ticker_clear_interrupt() {
RTC_IntClear(RTC_IF_COMP0);
inline void lp_ticker_clear_interrupt()
{
RTC_IntClear(RTC_IF_COMP0);
}
timestamp_t lp_ticker_read() {
uint64_t ticks_temp;
uint64_t ticks = RTC_CounterGet();
timestamp_t lp_ticker_read()
{
uint64_t ticks_temp;
uint64_t ticks = RTC_CounterGet();
/* ticks = counter tick value
* timestamp = value in microseconds
* timestamp = ticks * 1.000.000 / RTC frequency
*/
/* ticks = counter tick value
* timestamp = value in microseconds
* timestamp = ticks * 1.000.000 / RTC frequency
*/
ticks_temp = (ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT);
return (timestamp_t) (ticks_temp & 0xFFFFFFFF);
ticks_temp = (ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT);
return (timestamp_t) (ticks_temp & 0xFFFFFFFF);
}
#endif

13
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c
View File

@ -50,11 +50,11 @@ void mbed_sdk_init()
CMU_ClockSelectSet(cmuClock_LFA, LFXO);
#endif
#ifdef CMU_LFBCLKSEL_REG
/* cmuClock_LFB (to date) only has LEUART peripherals.
* Do NOT set it up here, as LEUARTs might have been initialized
* before this code is called. (Limitation of the override mechanism of ARMCC)
*/
//TODO: Look for a more elegant fix.
/* cmuClock_LFB (to date) only has LEUART peripherals.
* Do NOT set it up here, as LEUARTs might have been initialized
* before this code is called. (Limitation of the override mechanism of ARMCC)
*/
//TODO: Look for a more elegant fix.
//CMU_ClockSelectSet(cmuClock_LFB, LFXO);
#endif
#ifdef CMU_LFECLKSEL_REG
@ -92,7 +92,8 @@ void mbed_sdk_init()
gpio_init_out_ex(&bc_enable, EFM_BC_EN, 1);
}
void check_usart_clock(USART_TypeDef* usart, uint32_t clockmask) {
void check_usart_clock(USART_TypeDef* usart, uint32_t clockmask)
{
uint32_t freq = 14000000, baudrate;
USART_OVS_TypeDef ovs;

10
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h
View File

@ -129,11 +129,11 @@ struct lp_timer_s {
#if DEVICE_SLEEP
#define NUM_SLEEP_MODES 5
typedef enum {
EM0 = 0,
EM1 = 1,
EM2 = 2,
EM3 = 3,
EM4 = 4
EM0 = 0,
EM1 = 1,
EM2 = 2,
EM3 = 3,
EM4 = 4
} sleepstate_enum;
#endif

8
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c
View File

@ -30,10 +30,10 @@ void pin_mode(PinName pin, PinMode mode)
MBED_ASSERT(pin != NC);
/* Enable GPIO clock if not already done */
if (!gpio_clock_inited) {
CMU_ClockEnable(cmuClock_GPIO, true);
gpio_clock_inited = 1;
}
if (!gpio_clock_inited) {
CMU_ClockEnable(cmuClock_GPIO, true);
gpio_clock_inited = 1;
}
/* Pin and port index encoded in one uint32.
* First four bits represent the pin number

2
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c
View File

@ -44,7 +44,7 @@ void port_preinit(port_t *obj, PortName port, int mask, PinDirection dir)
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
port_preinit(obj, port, mask, dir);
port_preinit(obj, port, mask, dir);
port_dir(obj, obj->dir);
}

102
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c
View File

@ -33,22 +33,23 @@
static int pwm_clockfreq;
static int pwm_prescaler_div;
uint32_t pwmout_get_channel_route(pwmout_t *obj) {
MBED_ASSERT(obj->channel != (PWMName) NC);
uint32_t pwmout_get_channel_route(pwmout_t *obj)
{
MBED_ASSERT(obj->channel != (PWMName) NC);
switch (obj->channel) {
case PWM_CH0:
return TIMER_ROUTE_CC0PEN;
break;
case PWM_CH1:
return TIMER_ROUTE_CC1PEN;
break;
case PWM_CH2:
return TIMER_ROUTE_CC2PEN;
break;
default:
return 0;
}
switch (obj->channel) {
case PWM_CH0:
return TIMER_ROUTE_CC0PEN;
break;
case PWM_CH1:
return TIMER_ROUTE_CC1PEN;
break;
case PWM_CH2:
return TIMER_ROUTE_CC2PEN;
break;
default:
return 0;
}
}
void pwmout_enable_pins(pwmout_t *obj, uint8_t enable)
@ -63,8 +64,8 @@ void pwmout_enable_pins(pwmout_t *obj, uint8_t enable)
void pwmout_enable(pwmout_t *obj, uint8_t enable)
{
/* Start with default CC (Compare/Capture) channel parameters */
TIMER_InitCC_TypeDef timerCCInit = TIMER_INITCC_DEFAULT;
/* Start with default CC (Compare/Capture) channel parameters */
TIMER_InitCC_TypeDef timerCCInit = TIMER_INITCC_DEFAULT;
if (enable) {
/* Set mode to PWM */
timerCCInit.mode = timerCCModePWM;
@ -76,33 +77,33 @@ void pwmout_enable(pwmout_t *obj, uint8_t enable)
void pwmout_init(pwmout_t *obj, PinName pin)
{
obj->channel = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
obj->pin = pin;
MBED_ASSERT(obj->channel != (PWMName) NC);
obj->channel = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
obj->pin = pin;
MBED_ASSERT(obj->channel != (PWMName) NC);
/* Turn on clock */
CMU_ClockEnable(PWM_TIMER_CLOCK, true);
/* Turn on clock */
CMU_ClockEnable(PWM_TIMER_CLOCK, true);
/* Turn on timer */
if(!(PWM_TIMER->STATUS & TIMER_STATUS_RUNNING)) {
TIMER_Init_TypeDef timerInit = TIMER_INIT_DEFAULT;
TIMER_Init(PWM_TIMER, &timerInit);
}
/* Turn on timer */
if(!(PWM_TIMER->STATUS & TIMER_STATUS_RUNNING)) {
TIMER_Init_TypeDef timerInit = TIMER_INIT_DEFAULT;
TIMER_Init(PWM_TIMER, &timerInit);
}
/* Enable correct channel */
uint32_t routeloc = pwmout_get_channel_route(obj);
if(PWM_TIMER->ROUTE & routeloc) {
//This channel was already in use
//TODO: gracefully handle this case
} else {
//This channel was unused up to now
PWM_TIMER->ROUTE |= routeloc;
blockSleepMode(EM1);
uint32_t routeloc = pwmout_get_channel_route(obj);
if(PWM_TIMER->ROUTE & routeloc) {
//This channel was already in use
//TODO: gracefully handle this case
} else {
//This channel was unused up to now
PWM_TIMER->ROUTE |= routeloc;
blockSleepMode(EM1);
//TODO: check if any channel was up already, then don't re-init timer
pwmout_enable(obj, true);
pwmout_enable_pins(obj, true);
}
//TODO: check if any channel was up already, then don't re-init timer
pwmout_enable(obj, true);
pwmout_enable_pins(obj, true);
}
/* Route correct channel to location 1 */
PWM_TIMER->ROUTE &= ~_TIMER_ROUTE_LOCATION_MASK;
@ -115,18 +116,19 @@ void pwmout_init(pwmout_t *obj, PinName pin)
pwmout_period(obj, 0.02);
}
void pwmout_free(pwmout_t *obj) {
uint32_t routeloc = pwmout_get_channel_route(obj);
if(PWM_TIMER->ROUTE & routeloc) {
//This channel was in use, so disable
PWM_TIMER->ROUTE &= ~routeloc;
pwmout_enable_pins(obj, false);
unblockSleepMode(EM1);
void pwmout_free(pwmout_t *obj)
{
uint32_t routeloc = pwmout_get_channel_route(obj);
if(PWM_TIMER->ROUTE & routeloc) {
//This channel was in use, so disable
PWM_TIMER->ROUTE &= ~routeloc;
pwmout_enable_pins(obj, false);
unblockSleepMode(EM1);
//TODO: check if all channels are down, then switch off timer
} else {
//This channel was disabled already
}
//TODO: check if all channels are down, then switch off timer
} else {
//This channel was disabled already
}
}
void pwmout_write(pwmout_t *obj, float value)

23
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c
View File

@ -28,7 +28,7 @@ static bool rtc_inited = false;
static time_t time_base = 0;
static uint32_t useflags = 0;
static void (*comp0_handler)(void) = NULL;
static void (*comp0_handler)(void) = NULL;
#define RTC_LEAST_ACTIVE_SLEEPMODE EM2
@ -37,17 +37,14 @@ void RTC_IRQHandler(void)
{
uint32_t flags;
flags = RTC_IntGet();
if (flags & RTC_IF_OF)
{
if (flags & RTC_IF_OF) {
RTC_IntClear(RTC_IF_OF);
/* RTC has overflowed (24 bits). Use time_base as software counter for upper 8 bits. */
time_base += 1 << 24;
}
if (flags & RTC_IF_COMP0)
{
if (flags & RTC_IF_COMP0) {
RTC_IntClear(RTC_IF_COMP0);
if (comp0_handler != NULL)
{
if (comp0_handler != NULL) {
comp0_handler();
}
}
@ -58,7 +55,7 @@ void rtc_set_comp0_handler(uint32_t handler)
comp0_handler = (void (*)(void)) handler;
}
void rtc_init(void)
void rtc_init(void)
{
/* Register that the RTC is used for timekeeping. */
rtc_init_real(RTC_INIT_RTC);
@ -69,8 +66,7 @@ void rtc_init_real(uint32_t flags)
{
useflags |= flags;
if (!rtc_inited)
{
if (!rtc_inited) {
/* Start LFXO and wait until it is stable */
CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
@ -103,7 +99,7 @@ void rtc_init_real(uint32_t flags)
}
}
void rtc_free(void)
void rtc_free(void)
{
rtc_free_real(RTC_INIT_RTC);
}
@ -111,11 +107,10 @@ void rtc_free(void)
void rtc_free_real(uint32_t flags)
{
/* Clear use flag */
flags &= ~flags;
flags &= ~flags;
/* Disable the RTC if it was inited and is no longer in use by anyone. */
if (rtc_inited && (flags == 0))
{
if (rtc_inited && (flags == 0)) {
NVIC_DisableIRQ(RTC_IRQn);
RTC_Reset();
CMU_ClockEnable(cmuClock_RTC, false);

731
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c
View File

File diff suppressed because it is too large Load Diff

47
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c
View File

@ -34,19 +34,19 @@ uint32_t sleep_block_counter[NUM_SLEEP_MODES] = {0};
*/
void sleep(void)
{
if (sleep_block_counter[0] > 0) {
// Blocked everything below EM0, so just return
return;
} else if (sleep_block_counter[1] > 0) {
// Blocked everything below EM1, enter EM1
EMU_EnterEM1();
} else if (sleep_block_counter[2] > 0) {
// Blocked everything below EM2, enter EM2
EMU_EnterEM2(true);
} else if (sleep_block_counter[3] > 0) {
// Blocked everything below EM3, enter EM3
EMU_EnterEM3(true);
}
if (sleep_block_counter[0] > 0) {
// Blocked everything below EM0, so just return
return;
} else if (sleep_block_counter[1] > 0) {
// Blocked everything below EM1, enter EM1
EMU_EnterEM1();
} else if (sleep_block_counter[2] > 0) {
// Blocked everything below EM2, enter EM2
EMU_EnterEM2(true);
} else if (sleep_block_counter[3] > 0) {
// Blocked everything below EM3, enter EM3
EMU_EnterEM3(true);
}
return;
}
@ -74,11 +74,11 @@ void deepsleep(void)
* After the peripheral is finished with the operation, it should call unblock with the same state
*
*/
void blockSleepMode(sleepstate_enum minimumMode)
void blockSleepMode(sleepstate_enum minimumMode)
{
INT_Disable();
sleep_block_counter[minimumMode]++;
INT_Enable();
INT_Disable();
sleep_block_counter[minimumMode]++;
INT_Enable();
}
/** Unblock the microcontroller from sleeping below a certain mode
@ -88,14 +88,13 @@ void blockSleepMode(sleepstate_enum minimumMode)
*
* This should be called after all transactions on a peripheral are done.
*/
void unblockSleepMode(sleepstate_enum minimumMode)
void unblockSleepMode(sleepstate_enum minimumMode)
{
INT_Disable();
if(sleep_block_counter[minimumMode] > 0)
{
sleep_block_counter[minimumMode]--;
}
INT_Enable();
INT_Disable();
if(sleep_block_counter[minimumMode] > 0) {
sleep_block_counter[minimumMode]--;
}
INT_Enable();
}
#endif

532
libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c
View File

@ -35,7 +35,8 @@
static uint16_t fill_word = SPI_FILL_WORD;
#define SPI_LEAST_ACTIVE_SLEEPMODE EM1
inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj) {
inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj)
{
switch ((int)obj->spi.spi) {
#ifdef USART0
case SPI_0:
@ -81,7 +82,8 @@ inline uint8_t spi_get_index(spi_t *obj)
return index;
}
uint8_t spi_get_module(spi_t *obj) {
uint8_t spi_get_module(spi_t *obj)
{
return spi_get_index(obj);
}
@ -200,12 +202,12 @@ void spi_enable(spi_t *obj, uint8_t enable)
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs)
{
CMU_ClockEnable(cmuClock_HFPER, true);
spi_preinit(obj, mosi, miso, clk, cs);
CMU_ClockEnable(spi_get_clock_tree(obj), true);
usart_init(obj, 100000, usartDatabits8, true, usartClockMode0);
CMU_ClockEnable(cmuClock_HFPER, true);
spi_preinit(obj, mosi, miso, clk, cs);
CMU_ClockEnable(spi_get_clock_tree(obj), true);
usart_init(obj, 100000, usartDatabits8, true, usartClockMode0);
spi_enable_pins(obj, true, mosi, miso, clk, cs);
spi_enable_pins(obj, true, mosi, miso, clk, cs);
spi_enable(obj, true);
}
@ -254,8 +256,7 @@ void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
NVIC_SetVector(IRQvector, handler);
USART_IntEnable(obj->spi.spi, USART_IEN_RXDATAV);
NVIC_EnableIRQ(IRQvector);
}
else {
} else {
NVIC_SetVector(IRQvector, handler);
USART_IntDisable(obj->spi.spi, USART_IEN_RXDATAV);
NVIC_DisableIRQ(IRQvector);
@ -400,11 +401,11 @@ uint8_t spi_active(spi_t *obj)
void spi_buffer_set(spi_t *obj, void *tx, uint32_t tx_length, void *rx, uint32_t rx_length, uint8_t bit_width)
{
uint32_t i;
uint16_t *tx_ptr = (uint16_t *) tx;
uint32_t i;
uint16_t *tx_ptr = (uint16_t *) tx;
tx_length *= (bit_width >> 3);
rx_length *= (bit_width >> 3);
tx_length *= (bit_width >> 3);
rx_length *= (bit_width >> 3);
obj->tx_buff.buffer = tx;
obj->rx_buff.buffer = rx;
@ -416,123 +417,123 @@ void spi_buffer_set(spi_t *obj, void *tx, uint32_t tx_length, void *rx, uint32_t
obj->rx_buff.width = bit_width;
if((obj->spi.bits == 9) && (tx != 0)) {
// Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
for(i = 0; i < (tx_length / 2); i++) {
tx_ptr[i] &= 0x1FF;
}
// Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
for(i = 0; i < (tx_length / 2); i++) {
tx_ptr[i] &= 0x1FF;
}
}
}
static void spi_buffer_tx_write(spi_t *obj)
{
uint32_t data;
// This routine gets triggered on TXBL (= buffer empty), so check to see if we can write a double value
if (obj->spi.bits % 9 != 0) {
// No special 9-bit scenario
if((obj->tx_buff.pos < obj->tx_buff.length - 1) && ((obj->tx_buff.pos & 0x1) == 0)) {
// write double frame
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD;
} else {
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos / 2] & 0xFFFF;
}
obj->tx_buff.pos += 2;
obj->spi.spi->TXDOUBLE = data;
} else if (obj->tx_buff.pos < obj->tx_buff.length) {
// write single frame
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD & 0xFF;
} else {
uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos] & 0xFF;
}
obj->tx_buff.pos++;
obj->spi.spi->TXDATA = data;
}
} else {
// 9-bit frame
if(obj->tx_buff.pos < obj->tx_buff.length - 3) {
// write double frame
if (obj->tx_buff.buffer == (void *)0) {
data = ((SPI_FILL_WORD & 0x01FF) << 16) | (SPI_FILL_WORD & 0x1FF);
} else {
uint32_t *tx = (uint32_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos / 4] & 0x01FF01FF;
}
obj->tx_buff.pos += 4;
obj->spi.spi->TXDOUBLEX = data;
} else if (obj->tx_buff.pos < obj->tx_buff.length - 1) {
// write single frame
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD & 0x01FF;
} else {
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos / 2] & 0x01FF;
}
obj->tx_buff.pos += 2;
obj->spi.spi->TXDATAX = data;
}
}
uint32_t data;
// This routine gets triggered on TXBL (= buffer empty), so check to see if we can write a double value
if (obj->spi.bits % 9 != 0) {
// No special 9-bit scenario
if((obj->tx_buff.pos < obj->tx_buff.length - 1) && ((obj->tx_buff.pos & 0x1) == 0)) {
// write double frame
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD;
} else {
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos / 2] & 0xFFFF;
}
obj->tx_buff.pos += 2;
obj->spi.spi->TXDOUBLE = data;
} else if (obj->tx_buff.pos < obj->tx_buff.length) {
// write single frame
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD & 0xFF;
} else {
uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos] & 0xFF;
}
obj->tx_buff.pos++;
obj->spi.spi->TXDATA = data;
}
} else {
// 9-bit frame
if(obj->tx_buff.pos < obj->tx_buff.length - 3) {
// write double frame
if (obj->tx_buff.buffer == (void *)0) {
data = ((SPI_FILL_WORD & 0x01FF) << 16) | (SPI_FILL_WORD & 0x1FF);
} else {
uint32_t *tx = (uint32_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos / 4] & 0x01FF01FF;
}
obj->tx_buff.pos += 4;
obj->spi.spi->TXDOUBLEX = data;
} else if (obj->tx_buff.pos < obj->tx_buff.length - 1) {
// write single frame
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD & 0x01FF;
} else {
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos / 2] & 0x01FF;
}
obj->tx_buff.pos += 2;
obj->spi.spi->TXDATAX = data;
}
}
}
static void spi_buffer_rx_read(spi_t *obj)
{
if (obj->spi.bits % 9 != 0) {
if ((obj->spi.spi->STATUS & USART_STATUS_RXFULL) && (obj->rx_buff.pos < obj->rx_buff.length - 1) && ((obj->rx_buff.pos % 2) == 0)) {
// Read max 16 bits from buffer to speed things up
uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLE; //read the data but store only if rx is set and not full
if (obj->rx_buff.buffer) {
uint16_t *rx = (uint16_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos / 2] = data & 0xFFFF;
obj->rx_buff.pos += 2;
}
} else if ((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length)) {
// Read 8 bits from buffer
while((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length)) {
uint32_t data = (uint32_t)obj->spi.spi->RXDATA; //read the data but store only if rx is set and not full
if (obj->rx_buff.buffer) {
uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos] = data & 0xFF;
obj->rx_buff.pos++;
}
}
} else if (obj->spi.spi->STATUS & USART_STATUS_RXFULL) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLE;
} else if (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDATA;
}
} else {
// Data bits is multiple of 9, so use the extended registers
if ((obj->spi.spi->STATUS & USART_STATUS_RXFULL) && (obj->rx_buff.pos < obj->rx_buff.length - 3) && ((obj->rx_buff.pos % 4) == 0)) {
// Read max 18 bits from buffer to speed things up
uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLEX; //read the data but store only if rx is set and will not overflow
if (obj->rx_buff.buffer) {
uint16_t *rx = (uint16_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos / 2] = data & 0x000001FF;
rx[(obj->rx_buff.pos / 2) + 1] = (data & 0x01FF0000) >> 16;
obj->rx_buff.pos += 4;
}
} else if ((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length - 1)) {
// Read 9 bits from buffer
while((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length - 1)) {
uint32_t data = (uint32_t)obj->spi.spi->RXDATAX; //read the data but store only if rx is set and not full
if (obj->rx_buff.buffer) {
uint16_t *rx = (uint16_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos / 2] = data & 0x01FF;
obj->rx_buff.pos += 2;
}
}
} else if (obj->spi.spi->STATUS & USART_STATUS_RXFULL) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLEX;
} else if (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDATAX;
}
}
if (obj->spi.bits % 9 != 0) {
if ((obj->spi.spi->STATUS & USART_STATUS_RXFULL) && (obj->rx_buff.pos < obj->rx_buff.length - 1) && ((obj->rx_buff.pos % 2) == 0)) {
// Read max 16 bits from buffer to speed things up
uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLE; //read the data but store only if rx is set and not full
if (obj->rx_buff.buffer) {
uint16_t *rx = (uint16_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos / 2] = data & 0xFFFF;
obj->rx_buff.pos += 2;
}
} else if ((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length)) {
// Read 8 bits from buffer
while((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length)) {
uint32_t data = (uint32_t)obj->spi.spi->RXDATA; //read the data but store only if rx is set and not full
if (obj->rx_buff.buffer) {
uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos] = data & 0xFF;
obj->rx_buff.pos++;
}
}
} else if (obj->spi.spi->STATUS & USART_STATUS_RXFULL) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLE;
} else if (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDATA;
}
} else {
// Data bits is multiple of 9, so use the extended registers
if ((obj->spi.spi->STATUS & USART_STATUS_RXFULL) && (obj->rx_buff.pos < obj->rx_buff.length - 3) && ((obj->rx_buff.pos % 4) == 0)) {
// Read max 18 bits from buffer to speed things up
uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLEX; //read the data but store only if rx is set and will not overflow
if (obj->rx_buff.buffer) {
uint16_t *rx = (uint16_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos / 2] = data & 0x000001FF;
rx[(obj->rx_buff.pos / 2) + 1] = (data & 0x01FF0000) >> 16;
obj->rx_buff.pos += 4;
}
} else if ((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length - 1)) {
// Read 9 bits from buffer
while((obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL)) && (obj->rx_buff.pos < obj->rx_buff.length - 1)) {
uint32_t data = (uint32_t)obj->spi.spi->RXDATAX; //read the data but store only if rx is set and not full
if (obj->rx_buff.buffer) {
uint16_t *rx = (uint16_t *)(obj->rx_buff.buffer);
rx[obj->rx_buff.pos / 2] = data & 0x01FF;
obj->rx_buff.pos += 2;
}
}
} else if (obj->spi.spi->STATUS & USART_STATUS_RXFULL) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDOUBLEX;
} else if (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) {
// Read from the buffer to lower the interrupt flag
volatile uint32_t data = (uint32_t)obj->spi.spi->RXDATAX;
}
}
}
int spi_master_write_asynch(spi_t *obj)
@ -602,7 +603,7 @@ uint32_t spi_event_check(spi_t *obj)
}
if(quit == true) {
event |= SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
event |= SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
}
return event;
@ -633,7 +634,8 @@ void transferComplete(unsigned int channel, bool primary, void *user)
*
* return value: whether the channels were acquired successfully (true) or not.
******************************************/
bool spi_allocate_dma(spi_t *obj) {
bool spi_allocate_dma(spi_t *obj)
{
int dmaChannelIn, dmaChannelOut;
dmaChannelIn = dma_channel_allocate(DMA_CAP_NONE);
if (dmaChannelIn == DMA_ERROR_OUT_OF_CHANNELS) {
@ -722,7 +724,7 @@ static void spi_master_dma_channel_setup(spi_t *obj, void* callback)
txChnlCfg.enableInt = true;
txChnlCfg.cb = &(obj->spi.dmaOptionsTX.dmaCallback);
switch ((int)obj->spi.spi) {
switch ((int)obj->spi.spi) {
#ifdef USART0
case SPI_0:
rxChnlCfg.select = DMAREQ_USART0_RXDATAV;
@ -759,7 +761,8 @@ static void spi_master_dma_channel_setup(spi_t *obj, void* callback)
* * tx_length: how many bytes will get sent.
* * rx_length: how many bytes will get received. If > tx_length, TX will get padded with n lower bits of SPI_FILL_WORD.
******************************************/
static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_length, int rx_length) {
static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_length, int rx_length)
{
/* DMA descriptors */
DMA_CfgDescr_TypeDef rxDescrCfg;
DMA_CfgDescr_TypeDef txDescrCfg;
@ -768,81 +771,81 @@ static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_leng
obj->tx_buff.pos = tx_length;
if(obj->spi.bits != 9) {
/* Only activate RX DMA if a receive buffer is specified */
if (rxdata != NULL) {
// Setting up channel descriptor
rxDescrCfg.dstInc = dmaDataInc1;
rxDescrCfg.srcInc = dmaDataIncNone;
rxDescrCfg.size = dmaDataSize1;
rxDescrCfg.arbRate = dmaArbitrate1;
rxDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg);
/* Only activate RX DMA if a receive buffer is specified */
if (rxdata != NULL) {
// Setting up channel descriptor
rxDescrCfg.dstInc = dmaDataInc1;
rxDescrCfg.srcInc = dmaDataIncNone;
rxDescrCfg.size = dmaDataSize1;
rxDescrCfg.arbRate = dmaArbitrate1;
rxDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg);
// Clear RX registers - Useful if previous command transfered don't
obj->spi.spi->CMD = USART_CMD_CLEARRX;
// Clear RX registers - Useful if previous command transfered don't
obj->spi.spi->CMD = USART_CMD_CLEARRX;
/* Activate RX channel */
DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, true, false, rxdata, (void *)&(obj->spi.spi->RXDATA),
rx_length - 1);
}
/* Activate RX channel */
DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, true, false, rxdata, (void *)&(obj->spi.spi->RXDATA),
rx_length - 1);
}
// buffer with all FFs.
/* Setting up channel descriptor */
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = (txdata == 0 ? dmaDataIncNone : (obj->spi.bits <= 8 ? dmaDataInc1 : dmaDataInc2)); //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
// buffer with all FFs.
/* Setting up channel descriptor */
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = (txdata == 0 ? dmaDataIncNone : (obj->spi.bits <= 8 ? dmaDataInc1 : dmaDataInc2)); //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
/* Clear TX registers */
obj->spi.spi->CMD = USART_CMD_CLEARTX;
/* Clear TX registers */
obj->spi.spi->CMD = USART_CMD_CLEARTX;
/* Activate TX channel */
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(obj->spi.bits <= 8 ? (void *)&(obj->spi.spi->TXDATA) : (void *)&(obj->spi.spi->TXDOUBLE)), //When frame size > 9, point to TXDOUBLE
(txdata == 0 ? &fill_word : txdata), // When there is nothing to transmit, point to static fill word
(obj->spi.bits <= 8 ? tx_length - 1 : (tx_length / 2) - 1)); // When using TXDOUBLE, recalculate transfer length
/* Activate TX channel */
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(obj->spi.bits <= 8 ? (void *)&(obj->spi.spi->TXDATA) : (void *)&(obj->spi.spi->TXDOUBLE)), //When frame size > 9, point to TXDOUBLE
(txdata == 0 ? &fill_word : txdata), // When there is nothing to transmit, point to static fill word
(obj->spi.bits <= 8 ? tx_length - 1 : (tx_length / 2) - 1)); // When using TXDOUBLE, recalculate transfer length
} else {
/* Frame size == 9 */
/* Only activate RX DMA if a receive buffer is specified */
if (rxdata != NULL) {
// Setting up channel descriptor
rxDescrCfg.dstInc = dmaDataInc2;
rxDescrCfg.srcInc = dmaDataIncNone;
rxDescrCfg.size = dmaDataSize2;
rxDescrCfg.arbRate = dmaArbitrate1;
rxDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg);
/* Frame size == 9 */
/* Only activate RX DMA if a receive buffer is specified */
if (rxdata != NULL) {
// Setting up channel descriptor
rxDescrCfg.dstInc = dmaDataInc2;
rxDescrCfg.srcInc = dmaDataIncNone;
rxDescrCfg.size = dmaDataSize2;
rxDescrCfg.arbRate = dmaArbitrate1;
rxDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg);
// Clear RX registers - Useful if previous command transfered don't
obj->spi.spi->CMD = USART_CMD_CLEARRX;
// Clear RX registers - Useful if previous command transfered don't
obj->spi.spi->CMD = USART_CMD_CLEARRX;
/* Activate RX channel */
DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, true, false, rxdata, (void *)&(obj->spi.spi->RXDATAX),
(rx_length / 2) - 1);
}
/* Activate RX channel */
DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, true, false, rxdata, (void *)&(obj->spi.spi->RXDATAX),
(rx_length / 2) - 1);
}
/* Setting up channel descriptor */
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = (txdata == 0 ? dmaDataIncNone : dmaDataInc2); //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = dmaDataSize2; //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
/* Setting up channel descriptor */
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = (txdata == 0 ? dmaDataIncNone : dmaDataInc2); //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = dmaDataSize2; //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
/* Clear TX registers */
obj->spi.spi->CMD = USART_CMD_CLEARTX;
/* Clear TX registers */
obj->spi.spi->CMD = USART_CMD_CLEARTX;
/* Activate TX channel */
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(void *)&(obj->spi.spi->TXDATAX), //When frame size > 9, point to TXDOUBLE
(txdata == 0 ? &fill_word : txdata), // When there is nothing to transmit, point to static fill word
(tx_length / 2) - 1); // When using TXDOUBLE, recalculate transfer length
/* Activate TX channel */
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(void *)&(obj->spi.spi->TXDATAX), //When frame size > 9, point to TXDOUBLE
(txdata == 0 ? &fill_word : txdata), // When there is nothing to transmit, point to static fill word
(tx_length / 2) - 1); // When using TXDOUBLE, recalculate transfer length
}
}
@ -863,9 +866,10 @@ static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_leng
* If the previous transfer has kept the channel, that channel will continue to get used.
*
********************************************************************/
void spi_master_transfer_dma(spi_t *obj, void *txdata, void *rxdata, int tx_length, int rx_length, void* cb, DMAUsage hint) {
/* Init DMA here to include it in the power figure */
dma_init();
void spi_master_transfer_dma(spi_t *obj, void *txdata, void *rxdata, int tx_length, int rx_length, void* cb, DMAUsage hint)
{
/* Init DMA here to include it in the power figure */
dma_init();
/* If the DMA channels are already allocated, we can assume they have been setup already */
if (hint != DMA_USAGE_NEVER && obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED) {
/* setup has already been done, so just activate the transfer */
@ -910,36 +914,37 @@ void spi_master_transfer_dma(spi_t *obj, void *txdata, void *rxdata, int tx_leng
* @param[in] handler SPI interrupt handler
* @param[in] hint A suggestion for how to use DMA with this transfer
*/
void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) {
if( spi_active(obj) ) return;
void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
if( spi_active(obj) ) return;
/* update fill word if on 9-bit frame size */
if(obj->spi.bits == 9) fill_word = SPI_FILL_WORD & 0x1FF;
else fill_word = SPI_FILL_WORD;
/* update fill word if on 9-bit frame size */
if(obj->spi.bits == 9) fill_word = SPI_FILL_WORD & 0x1FF;
else fill_word = SPI_FILL_WORD;
/* check corner case */
if(tx_length == 0) {
tx_length = rx_length;
tx = (void*) 0;
}
/* check corner case */
if(tx_length == 0) {
tx_length = rx_length;
tx = (void*) 0;
}
/* First, set the buffer */
spi_buffer_set(obj, tx, tx_length, rx, rx_length, bit_width);
/* First, set the buffer */
spi_buffer_set(obj, tx, tx_length, rx, rx_length, bit_width);
/* Then, enable the events */
spi_enable_event(obj, SPI_EVENT_ALL, false);
spi_enable_event(obj, event, true);
/* Then, enable the events */
spi_enable_event(obj, SPI_EVENT_ALL, false);
spi_enable_event(obj, event, true);
/* Be tricky on how we handle increased bit widths in the buffer... Handling on byte-basis */
// div 8 = shift right 3
tx_length = tx_length * (bit_width >> 3);
rx_length = rx_length * (bit_width >> 3);
/* Be tricky on how we handle increased bit widths in the buffer... Handling on byte-basis */
// div 8 = shift right 3
tx_length = tx_length * (bit_width >> 3);
rx_length = rx_length * (bit_width >> 3);
// Set the sleep mode
blockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
// Set the sleep mode
blockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
/* And kick off the transfer */
spi_master_transfer_dma(obj, tx, rx, tx_length, rx_length, (void*)handler, hint);
/* And kick off the transfer */
spi_master_transfer_dma(obj, tx, rx, tx_length, rx_length, (void*)handler, hint);
}
@ -953,7 +958,8 @@ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_
* return: event mask. Currently only 0 or SPI_EVENT_COMPLETE upon transfer completion.
*
********************************************************************/
uint32_t spi_irq_handler_asynch(spi_t* obj) {
uint32_t spi_irq_handler_asynch(spi_t* obj)
{
/* Determine whether the current scenario is DMA or IRQ, and act accordingly */
@ -962,56 +968,55 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) {
/* If there is an RX transfer ongoing, wait for it to finish */
if (DMA_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)) {
/* Check if we need to kick off TX transfer again to force more incoming data. */
if (!DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) && (obj->tx_buff.pos < obj->rx_buff.length)) {
//Save state of TX transfer amount
int length_diff = obj->rx_buff.length - obj->tx_buff.pos;
obj->tx_buff.pos = obj->rx_buff.length;
/* Check if we need to kick off TX transfer again to force more incoming data. */
if (!DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) && (obj->tx_buff.pos < obj->rx_buff.length)) {
//Save state of TX transfer amount
int length_diff = obj->rx_buff.length - obj->tx_buff.pos;
obj->tx_buff.pos = obj->rx_buff.length;
//Kick off a new DMA transfer
DMA_CfgDescr_TypeDef txDescrCfg;
//Kick off a new DMA transfer
DMA_CfgDescr_TypeDef txDescrCfg;
if(obj->spi.bits != 9) {
fill_word = SPI_FILL_WORD;
/* Setting up channel descriptor */
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = dmaDataIncNone; //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
if(obj->spi.bits != 9) {
fill_word = SPI_FILL_WORD;
/* Setting up channel descriptor */
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = dmaDataIncNone; //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
/* Activate TX channel */
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(obj->spi.bits <= 8 ? (void *)&(obj->spi.spi->TXDATA) : (void *)&(obj->spi.spi->TXDOUBLE)), //When frame size > 9, point to TXDOUBLE
&fill_word, // When there is nothing to transmit, point to static fill word
(obj->spi.bits <= 8 ? length_diff - 1 : (length_diff / 2) - 1)); // When using TXDOUBLE, recalculate transfer length
} else {
/* Setting up channel descriptor */
fill_word = SPI_FILL_WORD & 0x1FF;
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = dmaDataIncNone; //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = dmaDataSize2; //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
/* Activate TX channel */
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(obj->spi.bits <= 8 ? (void *)&(obj->spi.spi->TXDATA) : (void *)&(obj->spi.spi->TXDOUBLE)), //When frame size > 9, point to TXDOUBLE
&fill_word, // When there is nothing to transmit, point to static fill word
(obj->spi.bits <= 8 ? length_diff - 1 : (length_diff / 2) - 1)); // When using TXDOUBLE, recalculate transfer length
} else {
/* Setting up channel descriptor */
fill_word = SPI_FILL_WORD & 0x1FF;
txDescrCfg.dstInc = dmaDataIncNone;
txDescrCfg.srcInc = dmaDataIncNone; //Do not increment source pointer when there is no transmit buffer
txDescrCfg.size = dmaDataSize2; //When frame size > 9, we can use TXDOUBLE to save bandwidth
txDescrCfg.arbRate = dmaArbitrate1;
txDescrCfg.hprot = 0;
DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg);
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(void *)&(obj->spi.spi->TXDATAX), //When frame size > 9, point to TXDOUBLE
&fill_word, // When there is nothing to transmit, point to static fill word
(length_diff / 2) - 1);
}
}
else return 0;
DMA_ActivateBasic( obj->spi.dmaOptionsTX.dmaChannel,
true,
false,
(void *)&(obj->spi.spi->TXDATAX), //When frame size > 9, point to TXDOUBLE
&fill_word, // When there is nothing to transmit, point to static fill word
(length_diff / 2) - 1);
}
} else return 0;
}
/* If there is still a TX transfer ongoing (tx_length > rx_length), wait for it to finish */
if (DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel)) {
return 0;
return 0;
}
/* Release the dma channels if they were opportunistically allocated */
@ -1054,28 +1059,29 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) {
*
* @param obj The SPI peripheral to stop
*/
void spi_abort_asynch(spi_t *obj) {
void spi_abort_asynch(spi_t *obj)
{
// If we're not currently transferring, then there's nothing to do here
if(spi_active(obj) != 0) return;
// Determine whether we're running DMA or interrupt
if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
// Cancel the DMA transfers
DMA_ChannelEnable(obj->spi.dmaOptionsTX.dmaChannel, false);
DMA_ChannelEnable(obj->spi.dmaOptionsRX.dmaChannel, false);
/* Release the dma channels if they were opportunistically allocated */
if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel);
dma_channel_free(obj->spi.dmaOptionsRX.dmaChannel);
obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
}
} else {
// Interrupt implementation: switch off interrupts
spi_enable_interrupt(obj, (uint32_t)NULL, false);
}
// Release sleep mode block
unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE);
}