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Add SCLK and SIN stats to SPIMasterTester. 

It has been found that there is a problem with the new K66F SPI driver when clock polarity is high.
After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high.
SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails.

The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.
pull/10660/head
Przemyslaw Stekiel 2019-05-24 14:35:45 +02:00
parent a4738fa9a8
commit 87902a8e76
3 changed files with 24 additions and 0 deletions
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8
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp
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@ -68,3 +68,11 @@ uint32_t SPIMasterTester::get_last_clk_edge_to_cs_ns()
return (delay_ns * 10); return (delay_ns * 10);
} }
uint8_t SPIMasterTester::get_start_stop_stats()
{
uint8_t start_stop_stats;
read(TESTER_SPI_MASTER_START_STOP_STATS, (uint8_t *)&start_stop_stats, TESTER_SPI_MASTER_START_STOP_STATS_SIZE);
return start_stop_stats;
}

14
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.h
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@ -104,6 +104,20 @@ public:
*/ */
uint32_t get_last_clk_edge_to_cs_ns(); uint32_t get_last_clk_edge_to_cs_ns();
/**
* Get SCLK and SIN states on transmission start and stop.
*
* @return latched SCLK and SIN states on transmission start and stop.
*
* @note Stats are encoded as fallows (bit 0 - LSB):
* - bit 0: start SCLK
* - bit 1: start SIN
* - bit 2: stop SCLK,
* - bit 3: stop SIN,
* - other: unused
*/
uint8_t get_start_stop_stats();
}; };
#endif #endif

2
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h
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@ -56,6 +56,8 @@
#define TESTER_SPI_MASTER_STOPS 0x00102009 #define TESTER_SPI_MASTER_STOPS 0x00102009
#define TESTER_SPI_MASTER_TRANSFERS 0x0010200A #define TESTER_SPI_MASTER_TRANSFERS 0x0010200A
#define TESTER_SPI_MASTER_TRANSFERS_SIZE 2 #define TESTER_SPI_MASTER_TRANSFERS_SIZE 2
#define TESTER_SPI_MASTER_START_STOP_STATS 0x0010200C
#define TESTER_SPI_MASTER_START_STOP_STATS_SIZE 1
#define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM 0x00102012 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM 0x00102012
#define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM_SIZE 4 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM_SIZE 4
#define TESTER_SPI_MASTER_CTRL 0x00102016 #define TESTER_SPI_MASTER_CTRL 0x00102016