From 87902a8e76bdbd8e3e198a4eb46ec0902c95ecac Mon Sep 17 00:00:00 2001 From: Przemyslaw Stekiel Date: Fri, 24 May 2019 14:35:45 +0200 Subject: [PATCH] Add SCLK and SIN stats to SPIMasterTester. It has been found that there is a problem with the new K66F SPI driver when clock polarity is high. After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high. SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails. The idea is to add support to the FPGA test shield to catch such errors and verify this in the test. --- .../SPIMasterTester.cpp | 8 ++++++++ .../SPIMasterTester.h | 14 ++++++++++++++ .../COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h | 2 ++ 3 files changed, 24 insertions(+) diff --git a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp index 05cd94a387..9d9ca7c389 100644 --- a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp +++ b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp @@ -68,3 +68,11 @@ uint32_t SPIMasterTester::get_last_clk_edge_to_cs_ns() return (delay_ns * 10); } + +uint8_t SPIMasterTester::get_start_stop_stats() +{ + uint8_t start_stop_stats; + read(TESTER_SPI_MASTER_START_STOP_STATS, (uint8_t *)&start_stop_stats, TESTER_SPI_MASTER_START_STOP_STATS_SIZE); + + return start_stop_stats; +} diff --git a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.h b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.h index a1b73b687c..bc75ab2f55 100644 --- a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.h +++ b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.h @@ -104,6 +104,20 @@ public: */ uint32_t get_last_clk_edge_to_cs_ns(); + /** + * Get SCLK and SIN states on transmission start and stop. + * + * @return latched SCLK and SIN states on transmission start and stop. + * + * @note Stats are encoded as fallows (bit 0 - LSB): + * - bit 0: start SCLK + * - bit 1: start SIN + * - bit 2: stop SCLK, + * - bit 3: stop SIN, + * - other: unused + */ + uint8_t get_start_stop_stats(); + }; #endif diff --git a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h index d54f268796..4d0a11cdf3 100644 --- a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h +++ b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h @@ -56,6 +56,8 @@ #define TESTER_SPI_MASTER_STOPS 0x00102009 #define TESTER_SPI_MASTER_TRANSFERS 0x0010200A #define TESTER_SPI_MASTER_TRANSFERS_SIZE 2 +#define TESTER_SPI_MASTER_START_STOP_STATS 0x0010200C +#define TESTER_SPI_MASTER_START_STOP_STATS_SIZE 1 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM 0x00102012 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM_SIZE 4 #define TESTER_SPI_MASTER_CTRL 0x00102016