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Merge pull request #15385 from UNSW-Sunswift/master 

Added extra HSE Values for STM32G431xB
pull/15388/head
Martin Kojtal 2023-03-08 13:08:04 +00:00 committed by GitHub
parent 17dc3dc2e6 ac8204c85f
commit 7e3ea686fb
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 10 additions and 1 deletions
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11
targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c
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@ -88,7 +88,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
#if HSE_VALUE != 24000000
#if HSE_VALUE != 4000000 && HSE_VALUE != 8000000 && HSE_VALUE != 16000000 && HSE_VALUE != 24000000
#error Unsupported externall clock value, check HSE_VALUE define
#endif
@ -100,7 +100,16 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
#if HSE_VALUE == 4000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
#elif HSE_VALUE == 8000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
#elif HSE_VALUE == 16000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
#elif HSE_VALUE == 24000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6;
#endif
//! 170MHz as a core frequency for FDCAN is not suitable for many frequencies,
//! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz
//! should be standard.