From 7c87d7c2398740efb035ba9e30fc38004e4ce225 Mon Sep 17 00:00:00 2001 From: Leonard Chiang Date: Sun, 26 Feb 2023 20:29:01 +1100 Subject: [PATCH 1/3] removed HSE speed limitation for STM32G431RB --- .../TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c index dd367f3636..5e76a51759 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c @@ -88,9 +88,9 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 }; -#if HSE_VALUE != 24000000 -#error Unsupported externall clock value, check HSE_VALUE define -#endif +//#if HSE_VALUE != 24000000 +//#error Unsupported externall clock value, check HSE_VALUE define +//#endif /* Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); From 7fcec27a4aa1c141b4bd6a8ef766e4396a79fc30 Mon Sep 17 00:00:00 2001 From: Leonard Date: Thu, 2 Mar 2023 12:40:16 +1100 Subject: [PATCH 2/3] Added HSE range validation for STM32g431xB --- .../TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c index 5e76a51759..c03f959704 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c @@ -88,9 +88,9 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 }; -//#if HSE_VALUE != 24000000 -//#error Unsupported externall clock value, check HSE_VALUE define -//#endif +#if HSE_VALUE > 48000000 || HSE_VALUE < 4000000 +#error Unsupported externall clock value, check HSE_VALUE define +#endif /* Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); From ac8204c85fcee1b8d07d61a981dd8008b39dcd75 Mon Sep 17 00:00:00 2001 From: Leonard Chiang Date: Sat, 4 Mar 2023 23:19:06 +1100 Subject: [PATCH 3/3] added support for 4, 8 and 16MHz --- .../TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c index c03f959704..dcbffe13fb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c @@ -88,7 +88,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 }; -#if HSE_VALUE > 48000000 || HSE_VALUE < 4000000 +#if HSE_VALUE != 4000000 && HSE_VALUE != 8000000 && HSE_VALUE != 16000000 && HSE_VALUE != 24000000 #error Unsupported externall clock value, check HSE_VALUE define #endif @@ -100,7 +100,16 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#if HSE_VALUE == 4000000 + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; +#elif HSE_VALUE == 8000000 + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; +#elif HSE_VALUE == 16000000 + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; +#elif HSE_VALUE == 24000000 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6; +#endif + //! 170MHz as a core frequency for FDCAN is not suitable for many frequencies, //! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz //! should be standard.