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LPTMR timer - OSCEN set, GCC startup vectors add

pull/135/head
0xc0170 2013-12-25 20:02:56 +01:00
parent b73b57db26
commit 78140c4aa1
7 changed files with 72 additions and 62 deletions
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2
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/MK20D5.sct
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@ -5,7 +5,7 @@ LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(61 vect * 4 bytes) = 8_byte_aligned(0xF4) = 0xF8
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
; 0x4000 - 0xF8 = 0x3F08
RW_IRAM1 0x1FFFE0F8 0x3F08 {
.ANY (+RW +ZI)

79
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
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@ -86,39 +86,52 @@ __isr_vector:
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long WDT_IRQHandler /* 0: Watchdog Timer */
.long RTC_IRQHandler /* 1: Real Time Clock */
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
.long MCIA_IRQHandler /* 4: MCIa */
.long MCIB_IRQHandler /* 5: MCIb */
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
.long UART4_IRQHandler /* 9: UART4 - not connected */
.long AACI_IRQHandler /* 10: AACI / AC97 */
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
.long ENET_IRQHandler /* 12: Ethernet */
.long USBDC_IRQHandler /* 13: USB Device */
.long USBHC_IRQHandler /* 14: USB Host Controller */
.long CHLCD_IRQHandler /* 15: Character LCD */
.long FLEXRAY_IRQHandler /* 16: Flexray */
.long CAN_IRQHandler /* 17: CAN */
.long LIN_IRQHandler /* 18: LIN */
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
.long 0 /* 20: Reserved */
.long 0 /* 21: Reserved */
.long 0 /* 22: Reserved */
.long 0 /* 23: Reserved */
.long 0 /* 24: Reserved */
.long 0 /* 25: Reserved */
.long 0 /* 26: Reserved */
.long 0 /* 27: Reserved */
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
.long 0 /* 29: Reserved - CPU FPGA */
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
.long DMA0_IRQHandler /* 0: Watchdog Timer */
.long DMA1_IRQHandler /* 1: Real Time Clock */
.long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
.long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
.long DMA_Error_IRQHandler /* 4: MCIa */
.long 0 /* 5: MCIb */
.long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
.long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
.long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
.long LLW_IRQHandler /* 9: UART4 - not connected */
.long Watchdog_IRQHandler /* 10: AACI / AC97 */
.long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
.long SPI0_IRQHandler /* 12: Ethernet */
.long I2S0_Tx_IRQHandler /* 13: USB Device */
.long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
.long UART0_LON_IRQHandler /* 15: Character LCD */
.long UART0_RX_TX_IRQHandler /* 16: Flexray */
.long UART0_ERR_IRQHandler /* 17: CAN */
.long UART1_RX_TX_IRQHandler /* 18: LIN */
.long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
.long UART2_RX_TX_IRQHandler /* 20: Reserved */
.long UART2_ERR_IRQHandler /* 21: Reserved */
.long ADC0_IRQHandler /* 22: Reserved */
.long CMP0_IRQHandler /* 23: Reserved */
.long CMP1_IRQHandler /* 24: Reserved */
.long FTM0_IRQHandler /* 25: Reserved */
.long FTM1_IRQHandler /* 26: Reserved */
.long CMT_IRQHandler /* 27: Reserved */
.long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
.long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
.long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
.long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
.long PIT2_IRQHandler
.long PIT3_IRQHandler
.long PDB0_IRQHandler
.long USB0_IRQHandler
.long USBDCD_IRQHandler
.long TSI0_IRQHandler
.long MCG_IRQHandler
.long LPTimer_IRQHandler
.long PORTA_IRQHandler
.long PORTB_IRQHandler
.long PORTC_IRQHandler
.long PORTD_IRQHandler
.long PORTE_IRQHandler
.long SWI_IRQHandler
.size __isr_vector, . - __isr_vector
.text

4
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis_nvic.h
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@ -2,12 +2,12 @@
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"

4
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/analogin_api.c
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@ -35,9 +35,8 @@ static const PinMap PinMap_ADC[] = {
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
if (obj->adc == (ADCName)NC) {
if (obj->adc == (ADCName)NC)
error("ADC pin mapping failed");
}
SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK;
@ -72,7 +71,6 @@ uint16_t analogin_read_u16(analogin_t *obj) {
// Wait Conversion Complete
while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK);
// Return value
return (uint16_t)ADC0->R[0];
}

9
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/gpio_irq_api.c
View File

@ -37,7 +37,8 @@ static void handle_interrupt_in(PORT_Type *port, int ch_base) {
if (port->ISFR & pmask) {
mask |= pmask;
uint32_t id = channel_ids[ch_base + i];
if (id == 0) continue;
if (id == 0)
continue;
GPIO_Type *gpio = PTA;
gpio_irq_event event = IRQ_NONE;
@ -70,7 +71,8 @@ void gpio_irqD(void) {handle_interrupt_in(PORTD, 96);}
void gpio_irqE(void) {handle_interrupt_in(PORTE, 128);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) return -1;
if (pin == NC)
return -1;
irq_handler = handler;
@ -129,9 +131,8 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
case IRQ_DISABLED:
if (enable) {
if (enable)
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
}
break;
case IRQ_RAISING_EDGE:

32
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/i2c_api.c
View File

@ -79,12 +79,11 @@ int i2c_start(i2c_t *obj) {
// if we are in the middle of a transaction
// activate the repeat_start flag
if (obj->i2c->S & I2C_S_BUSY_MASK) {
// KL25Z errata sheet: repeat start cannot be generated if the
// I2Cx_F[MULT] field is set to a non-zero value
temp = obj->i2c->F >> 6;
obj->i2c->F &= 0x3F;
obj->i2c->C1 |= 0x04;
for (i = 0; i < 100; i ++) __NOP();
for (i = 0; i < 100; i ++)
__NOP();
obj->i2c->F |= temp << 6;
} else {
obj->i2c->C1 |= I2C_C1_MST_MASK;
@ -274,9 +273,8 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
}
}
if (stop) {
if (stop)
i2c_stop(obj);
}
return length;
}
@ -333,12 +331,15 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
int i2c_slave_receive(i2c_t *obj) {
switch(obj->i2c->S) {
// read addressed
case 0xE6: return 1;
case 0xE6:
return 1;
// write addressed
case 0xE2: return 3;
case 0xE2:
return 3;
default: return 0;
default:
return 0;
}
}
@ -352,22 +353,19 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
// first dummy read
dummy_read = obj->i2c->D;
if(i2c_wait_end_rx_transfer(obj)) {
if (i2c_wait_end_rx_transfer(obj))
return 0;
}
// read address
dummy_read = obj->i2c->D;
if(i2c_wait_end_rx_transfer(obj)) {
if (i2c_wait_end_rx_transfer(obj))
return 0;
}
// read (length - 1) bytes
for (count = 0; count < (length - 1); count++) {
data[count] = obj->i2c->D;
if (i2c_wait_end_rx_transfer(obj)) {
if (i2c_wait_end_rx_transfer(obj))
return count;
}
}
// read last byte
@ -384,9 +382,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
obj->i2c->C1 |= I2C_C1_TX_MASK;
for (i = 0; i < length; i++) {
if(i2c_do_write(obj, data[count++]) == 2) {
if (i2c_do_write(obj, data[count++]) == 2)
return i;
}
}
// set rx mode
@ -395,9 +392,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
// dummy rx transfer needed
// otherwise the master cannot generate a stop bit
obj->i2c->D;
if(i2c_wait_end_rx_transfer(obj) == 2) {
if (i2c_wait_end_rx_transfer(obj) == 2)
return count;
}
return count;
}

4
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/us_ticker.c
View File

@ -82,7 +82,9 @@ static void lptmr_init(void) {
NVIC_EnableIRQ(LPTimer_IRQn);
/* Clock at (1)MHz -> (1)tick/us */
LPTMR0->PSR = LPTMR_PSR_PCS(3); // OSCERCLK -> 8MHz
OSC0->CR |= OSC_CR_ERCLKEN_MASK;
LPTMR0->PSR = 0;
LPTMR0->PSR |= LPTMR_PSR_PCS(3); // OSCERCLK -> 8MHz
LPTMR0->PSR |= LPTMR_PSR_PRESCALE(2); // divide by 8
}