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Merge pull request #10610 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.12.4
mbed-os-5.12 mbed-os-5.12.4
Martin Kojtal 2019-05-20 14:18:06 +01:00 committed by GitHub
parent 0f959dbe47 618297fac2
commit 73f096399b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
69 changed files with 1246 additions and 976 deletions
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2
.travis.yml
View File

@ -164,7 +164,6 @@ matrix:
pylint>=1.9,<2
hypothesis>=3,<4
coverage>=4.5,<5
coveralls>=1.5,<2
"
- python -m pip install --upgrade pip==18.1
- python -m pip install --upgrade setuptools==40.4.3
@ -176,7 +175,6 @@ matrix:
- python tools/test/pylint.py
- coverage run -a tools/project.py -S | sed -n '/^Total/p'
- coverage html
- coveralls
- <<: *pytools-vm
name: "tools-py35"

2
TESTS/host_tests/rtc_reset.py
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@ -40,7 +40,7 @@ class RtcResetTest(BaseHostTest):
"""Register callbacks required for the test"""
self._error = False
generator = self.rtc_reset_test()
generator.next()
next(generator)
def run_gen(key, value, time):
"""Run the generator, and fail testing if the iterator stops"""

8
TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
View File

@ -40,6 +40,14 @@
#undef QSPI_CMD_WRITE_DPI
#undef QSPI_CMD_WRITE_QPI
#elif defined(TARGET_RHOMBIO_L476DMW1K)
#include "MT25Q_config.h" // MT25QL128ABA1EW7
/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
#undef QSPI_CMD_READ_DPI
#undef QSPI_CMD_READ_QPI
#undef QSPI_CMD_WRITE_DPI
#undef QSPI_CMD_WRITE_QPI
#elif defined(TARGET_DISCO_L496AG)
#include "MX25RXX35F_config.h" // MX25R6435F

2
TESTS/netsocket/udp/udpsocket_echotest.cpp
View File

@ -29,7 +29,7 @@ namespace {
static const int SIGNAL_SIGIO_RX = 0x1;
static const int SIGNAL_SIGIO_TX = 0x2;
static const int SIGIO_TIMEOUT = 5000; //[ms]
static const int WAIT2RECV_TIMEOUT = 2000; //[ms]
static const int WAIT2RECV_TIMEOUT = 5000; //[ms]
static const int RETRIES = 2;
static const double EXPECTED_LOSS_RATIO = 0.0;

6
components/TARGET_PSA/TARGET_TFM/tf-m-integration.md
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@ -26,12 +26,12 @@ TF-M is built as bare-metal in a secure target, in order to build a secure targe
## Build hooks
Mbed-OS testing tools are designed to work with a single image (`.bin` or `.hex`).
When building mbed-os for ARMv8-M targets two images are created. One for normal world(NW) and one for TrustZone(TZ).
When building mbed-os for TF-M targets two images are created. One for normal world(NW) and one for TrustZone(TZ).
Mbed-OS build system provides `post_binary_hook` that allows executing arbitrary Python script for merging NW and TZ images. Typically `post_binary_hook` is added to NW target and assumes TZ target images as a prerequisite.
## Porting ARMv8-M targets
## Porting TF-M targets
Typically firmware for ARMv8-M targets consist of 2 or more images: normal world and TrustZone image. More images can be present in case boot loaders are used.
Typically firmware for TF-M targets consist of 2 or more images: normal world and TrustZone image. More images can be present in case boot loaders are used.
Two images must be built and linked separately. TrustZone image must be built first.
There may be code and/or header files sharing between the two targets.

20
components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json
View File

@ -32,25 +32,25 @@
"SPI_CLK": "PE_12",
"SPI_CS": "PE_11"
},
"MTB_ADV_WISE_1530": {
"MTB_ADV_WISE_1530": {
"SPI_MOSI": "PC_3",
"SPI_MISO": "PC_2",
"SPI_CLK": "PB_13",
"SPI_CS": "PC_12"
"SPI_CS": "PC_12"
},
"MTB_MXCHIP_EMW3166": {
"MTB_MXCHIP_EMW3166": {
"SPI_MOSI": "PB_15",
"SPI_MISO": "PB_14",
"SPI_CLK": "PB_13",
"SPI_CS": "PA_10"
"SPI_CS": "PA_10"
},
"MTB_USI_WM_BN_BM_22": {
"MTB_USI_WM_BN_BM_22": {
"SPI_MOSI": "PC_3",
"SPI_MISO": "PC_2",
"SPI_CLK": "PB_13",
"SPI_CS": "PA_6"
"SPI_CS": "PA_6"
},
"MTB_ADV_WISE_1570": {
"MTB_ADV_WISE_1570": {
"SPI_MOSI": "PA_7",
"SPI_MISO": "PA_6",
"SPI_CLK": "PA_5",
@ -62,6 +62,12 @@
"SPI_MISO": "PE_13",
"SPI_CLK": "PE_12",
"SPI_CS": "PE_11"
},
"MTS_DRAGONFLY_F411RE": {
"SPI_MOSI": "SPI3_MOSI",
"SPI_MISO": "SPI3_MISO",
"SPI_CLK": "SPI3_SCK",
"SPI_CS": "SPI_CS1"
}
}
}

6
drivers/SPI.cpp
View File

@ -83,6 +83,12 @@ void SPI::_do_construct()
_peripheral->name = name;
}
core_util_critical_section_exit();
#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
// prime the SingletonPtr, so we don't have a problem trying to
// construct the buffer if asynch operation initiated from IRQ
_peripheral->transaction_buffer.get();
#endif
// we don't need to _acquire at this stage.
// this will be done anyway before any operation.
}

4
features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp
View File

@ -510,7 +510,7 @@ ble_error_t GattServer::insert_descriptor(
#endif // BLE_FEATURE_SECURITY
}
if (properties & READ_PROPERTY) {
if (properties & READ_PROPERTY && !(attribute_it->settings & ATTS_SET_CCC)) {
attribute_it->settings |= ATTS_SET_READ_CBACK;
}
}
@ -543,7 +543,7 @@ ble_error_t GattServer::insert_descriptor(
#endif // BLE_FEATURE_SECURITY
}
if (properties & WRITABLE_PROPERTIES) {
if (properties & WRITABLE_PROPERTIES && !(attribute_it->settings & ATTS_SET_CCC)) {
attribute_it->settings |= ATTS_SET_WRITE_CBACK;
}
}

2
features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp
View File

@ -70,6 +70,7 @@ nsapi_error_t QUECTEL_BG96_CellularStack::socket_connect(nsapi_socket_t handle,
if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) {
if (err == BG96_SOCKET_BIND_FAIL) {
socket->created = false;
_at.unlock();
return NSAPI_ERROR_PARAMETER;
}
_at.cmd_start("AT+QICLOSE=");
@ -177,6 +178,7 @@ void QUECTEL_BG96_CellularStack::handle_open_socket_response(int &modem_connect_
modem_connect_id = _at.read_int();
err = _at.read_int();
}
nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *socket)
{
int modem_connect_id = -1;

2
features/lwipstack/lwip-sys/arch/cc.h
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@ -110,7 +110,7 @@ MBED_NORETURN void lwip_mbed_assert_fail(const char *msg, const char *func, cons
#else // MBED_CONF_LWIP_USE_MBED_TRACE
#include <stdio.h>
MBED_NORETURN void assert_printf(char *msg, int line, char *file);
MBED_NORETURN void assert_printf(const char *msg, int line, const char *file);
/* Plaform specific diagnostic output */
#define LWIP_PLATFORM_DIAG(vars) printf vars

2
features/lwipstack/lwip-sys/arch/lwip_sys_arch.c
View File

@ -605,7 +605,7 @@ MBED_NORETURN void lwip_mbed_assert_fail(const char *msg, const char *func, cons
\param[in] line Line number in file with error
\param[in] file Filename with error
*/
MBED_NORETURN void assert_printf(char *msg, int line, char *file) {
MBED_NORETURN void assert_printf(const char *msg, int line, const char *file) {
if (msg)
error("%s:%d in file %s\n", msg, line, file);
else

2
features/lwipstack/lwipopts.h
View File

@ -83,7 +83,9 @@
#define SYS_LIGHTWEIGHT_PROT 1
#ifndef LWIP_RAW
#define LWIP_RAW 0
#endif
#define TCPIP_MBOX_SIZE 8
#define DEFAULT_TCP_RECVMBOX_SIZE 8

3
features/lwipstack/mbed_lib.json
View File

@ -176,6 +176,9 @@
},
"FVP_MPS2_M3": {
"mem-size": 36560
},
"MTS_DRAGONFLY_F411RE": {
"tcpip-thread-stacksize": 1600
}
}
}

78
features/storage/TESTS/filesystem/general_filesystem/main.cpp
View File

@ -26,9 +26,6 @@
#elif COMPONENT_SD
#include "SDBlockDevice.h"
#include "FATFileSystem.h"
#elif COMPONENT_FLASHIAP
#include "FlashIAPBlockDevice.h"
#include "LittleFileSystem.h"
#else
#error [NOT_SUPPORTED] storage test not supported on this platform
#endif
@ -76,14 +73,12 @@ static void deinit()
static void bd_init_fs_reformat()
{
bd_type = bd->get_type();
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
init();
}
//fopen path without fs prefix
static void FS_fopen_path_not_valid()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(1, res);
@ -92,7 +87,6 @@ static void FS_fopen_path_not_valid()
//fopen empty file name with r mode
static void FS_fopen_empty_path_r_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "", "rb")) != NULL);
TEST_ASSERT_EQUAL(1, res);
}
@ -100,7 +94,6 @@ static void FS_fopen_empty_path_r_mode()
//fopen empty file name with w mode
static void FS_fopen_empty_path_w_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "", "wb")) != NULL);
TEST_ASSERT_EQUAL(1, res);
}
@ -108,7 +101,6 @@ static void FS_fopen_empty_path_w_mode()
//fopen empty mode
static void FS_fopen_invalid_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "Invalid_mode", "")) != NULL);
TEST_ASSERT_EQUAL(1, res);
}
@ -116,7 +108,6 @@ static void FS_fopen_invalid_mode()
//fopen with valid flowSystemStorage
static void FS_fopen_supported_wb_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -130,7 +121,6 @@ static void FS_fopen_supported_wb_mode()
//fopen with append mode
static void FS_fopen_supported_a_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "a")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -144,7 +134,6 @@ static void FS_fopen_supported_a_mode()
//fopen with read mode
static void FS_fopen_supported_r_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "r")) != NULL);
TEST_ASSERT_EQUAL(1, res);
}
@ -152,7 +141,6 @@ static void FS_fopen_supported_r_mode()
//fopen with append update mode
static void FS_fopen_supported_a_update_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "a+")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -166,7 +154,6 @@ static void FS_fopen_supported_a_update_mode()
//fopen with read update mode
static void FS_fopen_supported_r_update_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "r+")) != NULL);
TEST_ASSERT_EQUAL(1, res);
}
@ -174,7 +161,6 @@ static void FS_fopen_supported_r_update_mode()
//fopen with write update mode
static void FS_fopen_supported_w_update_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "w+")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -188,7 +174,6 @@ static void FS_fopen_supported_w_update_mode()
//fopen with read update create, check contents exist
static void FS_fopen_read_update_create()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = "";
@ -218,7 +203,6 @@ static void FS_fopen_read_update_create()
//fopen with write update create, check contents doesnt exist
static void FS_fopen_write_update_create()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = "";
@ -248,7 +232,6 @@ static void FS_fopen_write_update_create()
//fclose valid flow
static void FS_fclose_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -264,7 +247,6 @@ static void FS_fclose_valid_flow()
//fwrite with nmemb zero
static void FS_fwrite_nmemb_zero()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -283,7 +265,6 @@ static void FS_fwrite_nmemb_zero()
//fwrite valid flow
static void FS_fwrite_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "good_day";
char read_buf[small_buf_size] = {};
@ -313,7 +294,6 @@ static void FS_fwrite_valid_flow()
//fwrite to fopen mode r
static void FS_fwrite_with_fopen_r_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -340,7 +320,6 @@ static void FS_fwrite_with_fopen_r_mode()
//fread with size zero
static void FS_fread_size_zero()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -368,7 +347,6 @@ static void FS_fread_size_zero()
//fread with nmemb zero
static void FS_fread_nmemb_zero()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -396,7 +374,6 @@ static void FS_fread_nmemb_zero()
//fread to fopen mode w
static void FS_fread_with_fopen_w_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = {};
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -421,7 +398,6 @@ static void FS_fread_with_fopen_w_mode()
//fread to fwrite file
static void FS_fread_to_fwrite_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = {};
char write_buf[small_buf_size] = "123456789";
@ -444,7 +420,6 @@ static void FS_fread_to_fwrite_file()
//fread empty file
static void FS_fread_empty_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = {};
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -469,7 +444,6 @@ static void FS_fread_empty_file()
//fread valid flow small file
static void FS_fread_valid_flow_small_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "good_day";
char read_buf[small_buf_size] = {};
@ -500,7 +474,6 @@ static void FS_fread_valid_flow_small_file()
//fread valid flow medium file
static void FS_fread_valid_flow_medium_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[medium_buf_size] = { 1 };
char read_buf[medium_buf_size] = {};
@ -530,7 +503,6 @@ static void FS_fread_valid_flow_medium_file()
//fread valid flow large file
static void FS_fread_valid_flow_large_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[large_buf_size] = { 1 };
char read_buf[large_buf_size] = {};
@ -560,7 +532,6 @@ static void FS_fread_valid_flow_large_file()
//fread valid flow small file read more than write
static void FS_fread_valid_flow_small_file_read_more_than_write()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "good_day";
char read_buf[small_buf_size + 10] = {};
@ -592,7 +563,6 @@ static void FS_fread_valid_flow_small_file_read_more_than_write()
//fgetc to an empty file
static void FS_fgetc_empty_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -615,7 +585,6 @@ static void FS_fgetc_empty_file()
//fgetc valid flow
static void FS_fgetc_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "good_day";
char read_buf[small_buf_size] = {};
int ch = 0;
@ -650,7 +619,6 @@ static void FS_fgetc_valid_flow()
//fgetc to fopen mode w
static void FS_fgetc_with_fopen_w_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -675,7 +643,6 @@ static void FS_fgetc_with_fopen_w_mode()
//fgets to an empty file
static void FS_fgets_empty_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = {};
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -699,7 +666,6 @@ static void FS_fgets_empty_file()
//fgets with buffer null with zero len of buffer string
static void FS_fgets_null_buffer_zero_len()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -721,7 +687,6 @@ static void FS_fgets_null_buffer_zero_len()
//fgets with buffer null
static void FS_fgets_null_buffer()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -743,7 +708,6 @@ static void FS_fgets_null_buffer()
//fgets valid flow
static void FS_fgets_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "good_day";
char read_buf[small_buf_size] = {};
@ -772,7 +736,6 @@ static void FS_fgets_valid_flow()
//fgets up to new line character
static void FS_fgets_new_line()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "good_day";
char read_buf[small_buf_size] = {};
@ -803,7 +766,6 @@ static void FS_fgets_new_line()
//fgets to fopen mode w
static void FS_fgets_with_fopen_w_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = {};
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -829,7 +791,6 @@ static void FS_fgets_with_fopen_w_mode()
//fflush with null
static void FS_fflush_null_stream()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = fflush(NULL);
TEST_ASSERT_EQUAL(0, res);
}
@ -838,7 +799,6 @@ static void FS_fflush_null_stream()
//fflush valid flow
static void FS_fflush_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -861,7 +821,6 @@ static void FS_fflush_valid_flow()
//fflush twice
static void FS_fflush_twice()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -888,7 +847,6 @@ static void FS_fflush_twice()
//fputc valid flow
static void FS_fputc_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int write_ch = 10, read_ch = 0;
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -916,7 +874,6 @@ static void FS_fputc_valid_flow()
//fputc with file open for read mode
static void FS_fputc_in_read_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int write_ch = 10;
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -943,7 +900,6 @@ static void FS_fputc_in_read_mode()
//fputs valid flow
static void FS_fputs_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = {};
@ -973,7 +929,6 @@ static void FS_fputs_valid_flow()
//fputs with file open for read mode
static void FS_fputs_in_read_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char buffer[small_buf_size] = "good_day";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1000,7 +955,6 @@ static void FS_fputs_in_read_mode()
//fseek empty file, SEEK_SET, offset 0
static void FS_fseek_empty_file_seek_set()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -1026,7 +980,6 @@ static void FS_fseek_empty_file_seek_set()
//fseek non empty file, SEEK_SET, offset 0
static void FS_fseek_non_empty_file_seek_set()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1057,7 +1010,6 @@ static void FS_fseek_non_empty_file_seek_set()
//fseek empty file, SEEK_SET, offset 1 - beyond end of file
static void FS_fseek_beyond_empty_file_seek_set()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = "";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1088,7 +1040,6 @@ static void FS_fseek_beyond_empty_file_seek_set()
//fseek non empty file, SEEK_SET, offset data_size + 1 - beyond end of file
static void FS_fseek_beyond_non_empty_file_seek_set()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = "";
@ -1123,7 +1074,6 @@ static void FS_fseek_beyond_non_empty_file_seek_set()
//fseek empty file, SEEK_CUR, offset 0
static void FS_fseek_empty_file_seek_cur()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -1149,7 +1099,6 @@ static void FS_fseek_empty_file_seek_cur()
//fseek non empty file, SEEK_CUR, offset 0
static void FS_fseek_non_empty_file_seek_cur()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1180,7 +1129,6 @@ static void FS_fseek_non_empty_file_seek_cur()
//fseek empty file, SEEK_CUR, offset 1 - beyond end of file
static void FS_fseek_beyond_empty_file_seek_cur()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = {};
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1211,7 +1159,6 @@ static void FS_fseek_beyond_empty_file_seek_cur()
//fseek non empty file, SEEK_CUR, offset data_size + 1 - beyond end of file
static void FS_fseek_beyond_non_empty_file_seek_cur()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = {};
char write_buf[small_buf_size] = "123456789";
@ -1246,7 +1193,6 @@ static void FS_fseek_beyond_non_empty_file_seek_cur()
//fseek empty file, SEEK_END, offset 0
static void FS_fseek_empty_file_seek_end()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -1272,7 +1218,6 @@ static void FS_fseek_empty_file_seek_end()
//fseek non empty file, SEEK_END, offset 0
static void FS_fseek_non_empty_file_seek_end()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1303,7 +1248,6 @@ static void FS_fseek_non_empty_file_seek_end()
//fseek empty file, SEEK_END, offset 1 - beyond end of file
static void FS_fseek_beyond_empty_file_seek_end()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = {};
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1334,7 +1278,6 @@ static void FS_fseek_beyond_empty_file_seek_end()
//fseek non empty file, SEEK_END, offset data_size + 1 - beyond end of file
static void FS_fseek_beyond_non_empty_file_seek_end()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char read_buf[small_buf_size] = {};
char write_buf[small_buf_size] = "123456789";
@ -1369,7 +1312,6 @@ static void FS_fseek_beyond_non_empty_file_seek_end()
//fseek non empty file, SEEK_END, offset negative
static void FS_fseek_negative_non_empty_file_seek_end()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1402,7 +1344,6 @@ static void FS_fseek_negative_non_empty_file_seek_end()
//fgetpos rewrite file and check data
static void FS_fgetpos_rewrite_check_data()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char rewrite_buf[small_buf_size] = "987654321";
char read_buf[small_buf_size] = {};
@ -1445,7 +1386,6 @@ static void FS_fgetpos_rewrite_check_data()
//fscanf valid flow
static void FS_fscanf_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = {};
int num = 0;
@ -1480,7 +1420,6 @@ static void FS_fscanf_valid_flow()
//fscanf empty file
static void FS_fscanf_empty_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int num = 0;
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
@ -1499,7 +1438,6 @@ static void FS_fscanf_empty_file()
//fscanf more fields than exist
static void FS_fscanf_more_fields_than_exist()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = {};
int num = 0;
@ -1539,7 +1477,6 @@ static void FS_fscanf_more_fields_than_exist()
//fprintf in mode r
static void FS_fprintf_read_mode()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -1564,7 +1501,6 @@ static void FS_fprintf_read_mode()
//freopen point to the same file with two file handler
static void FS_freopen_point_to_same_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int res = !((fd[0] = fopen("/default/" "filename", "wb")) != NULL);
TEST_ASSERT_EQUAL(0, res);
@ -1583,7 +1519,6 @@ static void FS_freopen_point_to_same_file()
//freopen valid flow
static void FS_freopen_valid_flow()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[small_buf_size] = "123456789";
char read_buf[small_buf_size] = {};
@ -1612,7 +1547,6 @@ static void FS_freopen_valid_flow()
//create a 1 byte file
static void FS_fopen_write_one_byte_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf = 1;
char read_buf[1] = {};
@ -1642,7 +1576,6 @@ static void FS_fopen_write_one_byte_file()
//create a 2 bytes file
static void FS_fopen_write_two_byte_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[2] = "1";
char read_buf[2] = {};
@ -1672,7 +1605,6 @@ static void FS_fopen_write_two_byte_file()
//create a 5 bytes file
static void FS_fopen_write_five_byte_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[5] = "1234";
char read_buf[5] = {};
@ -1702,7 +1634,6 @@ static void FS_fopen_write_five_byte_file()
//create a 15 bytes file
static void FS_fopen_write_fifteen_byte_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[15] = "12345678901234";
char read_buf[15] = {};
@ -1732,7 +1663,6 @@ static void FS_fopen_write_fifteen_byte_file()
//create a 5000 bytes file
static void FS_fopen_write_five_Kbyte_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
int buf_sz = 5000;
char *write_buf = (char *)malloc(buf_sz);
char read_buf[10] = {};
@ -1765,7 +1695,6 @@ static void FS_fopen_write_five_Kbyte_file()
//rewrite file begining
static void FS_fseek_rewrite_non_empty_file_begining()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[15] = "12345678901234";
char rewrite_buf[6] = "abcde";
char check_buf[15] = "abcde678901234";
@ -1812,7 +1741,6 @@ static void FS_fseek_rewrite_non_empty_file_begining()
//rewrite file middle
static void FS_fseek_rewrite_non_empty_file_middle()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[15] = "12345678901234";
char rewrite_buf[6] = "abcde";
char check_buf[15] = "12345abcde1234";
@ -1859,7 +1787,6 @@ static void FS_fseek_rewrite_non_empty_file_middle()
//rewrite file end
static void FS_fseek_rewrite_non_empty_file_end()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[15] = "12345678901234";
char rewrite_buf[6] = "abcde";
char check_buf[15] = "123456789abcde";
@ -1906,7 +1833,6 @@ static void FS_fseek_rewrite_non_empty_file_end()
//append buffer to empty file
static void FS_append_empty_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[17] = "1234567890123456";
char read_buf[17] = {};
@ -1936,7 +1862,6 @@ static void FS_append_empty_file()
//append buffer to non empty file
static void FS_append_non_empty_file()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[17] = "1234567890123456";
char rewrite_buf[17] = "abcdefghijklmnop";
char read_buf[34] = {};
@ -1980,7 +1905,6 @@ static void FS_append_non_empty_file()
//fill write_buf buffer with random data, read back the data from the file
static void FS_write_read_random_data()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
char write_buf[medium_buf_size] = {};
unsigned int i;
@ -2016,7 +1940,6 @@ static void FS_write_read_random_data()
//fill write_buf buffer with random data, read back the data from the file
static void FS_fill_data_and_seek()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
unsigned int i, j;
int res = !((fd[0] = fopen("/default/" "filename", "w")) != NULL);
@ -2067,7 +1990,6 @@ static void FS_fill_data_and_seek()
//deinit the blockdevice and unmount the filesystem
static void bd_deinit_fs_unmount()
{
TEST_SKIP_UNLESS_MESSAGE(strcmp(bd_type, "FLASHIAP") != 0, "Skip FS tests on FlashIAP");
deinit();
}

2
features/storage/filesystem/littlefs/TESTS/host_tests/unexpected_reset.py
View File

@ -38,7 +38,7 @@ class UnexpectedResetTest(BaseHostTest):
"""Register callbacks required for the test"""
self._error = False
generator = self.unexpected_reset_test()
generator.next()
next(generator)
def run_gen(key, value, time):
"""Run the generator, and fail testing if the iterator stops"""

4
platform/mbed_lib.json
View File

@ -198,6 +198,10 @@
"NUCLEO_F411RE": {
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true
},
"DISCO_F407VG": {
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true
}
}
}

2
platform/mbed_version.h
View File

@ -44,7 +44,7 @@
*
* @note 99 is default value for development version (master branch)
*/
#define MBED_PATCH_VERSION 3
#define MBED_PATCH_VERSION 4
#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))

2
requirements.txt
View File

@ -1,5 +1,5 @@
colorama==0.3.9
urllib3[secure]==1.23
urllib3[secure]==1.24.2
prettytable==0.7.2
junit-xml==1.8
pyyaml==4.2b1

2
rtos/Mutex.cpp
View File

@ -42,7 +42,7 @@ void Mutex::constructor(const char *name)
{
osMutexAttr_t attr =
{ 0 };
attr.name = name ? name : "aplication_unnamed_mutex";
attr.name = name ? name : "application_unnamed_mutex";
attr.cb_mem = &_obj_mem;
attr.cb_size = sizeof(_obj_mem);
attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/device/system_psoc6_cm4.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -43,10 +39,6 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -271,41 +263,6 @@ void SystemInit(void)
}
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
mailbox_init();
#endif
/* Set up the device based on configurator selections */
init_cycfg_all();
/* Enable global interrupts */
__enable_irq();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -43,10 +39,6 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -271,41 +263,6 @@ void SystemInit(void)
}
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
mailbox_init();
#endif
/* Set up the device based on configurator selections */
init_cycfg_all();
/* Enable global interrupts */
__enable_irq();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**

42
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -44,10 +40,6 @@
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -165,38 +157,6 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
/* Configure mailbox IPC interrupts */
mailbox_init();
#else
/* Enable global interrupts */
__enable_irq();
#endif
}
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -43,10 +39,6 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -271,41 +263,6 @@ void SystemInit(void)
}
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
mailbox_init();
#endif
/* Set up the device based on configurator selections */
init_cycfg_all();
/* Enable global interrupts */
__enable_irq();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6_cm4.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -43,10 +39,6 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -271,41 +263,6 @@ void SystemInit(void)
}
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
mailbox_init();
#endif
/* Set up the device based on configurator selections */
init_cycfg_all();
/* Enable global interrupts */
__enable_irq();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**

42
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -44,10 +40,6 @@
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -165,38 +157,6 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
/* Configure mailbox IPC interrupts */
mailbox_init();
#else
/* Enable global interrupts */
__enable_irq();
#endif
}
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c
View File

@ -22,16 +22,12 @@
* limitations under the License.
*******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "cy_device.h"
#include "device.h"
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "psoc6_utils.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cycfg.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
@ -43,10 +39,6 @@
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* SystemCoreClockUpdate()
@ -271,41 +263,6 @@ void SystemInit(void)
}
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
#if !defined(COMPONENT_SPM_MAILBOX)
/* Disable global interrupts */
__disable_irq();
#endif
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
mailbox_init();
#endif
/* Set up the device based on configurator selections */
init_cycfg_all();
/* Enable global interrupts */
__enable_irq();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**

55
targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c Normal file
View File

@ -0,0 +1,55 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "psoc6_utils.h"
#include "cycfg.h"
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
#endif
/*******************************************************************************
* Function Name: mbed_sdk_init
****************************************************************************//**
*
* Mbed's post-memory-initialization function.
* Used here to initialize common parts of the Cypress libraries.
*
*******************************************************************************/
void mbed_sdk_init(void)
{
/* Initialize shared resource manager */
cy_srm_initialize();
/* Initialize system and clocks. */
/* Placed here as it must be done after proper LIBC initialization. */
SystemInit();
#if defined(COMPONENT_SPM_MAILBOX)
mailbox_init();
#endif
#if (!CY_CPU_CORTEX_M0P)
/* Set up the device based on configurator selections */
init_cycfg_all();
/* Enable global interrupts (disabled in CM4 startup assembly) */
__enable_irq();
#endif
}

3
targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf
View File

@ -19,6 +19,7 @@ define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block ROMVEC with alignment = 8 { readonly section .intvec };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
@ -26,7 +27,7 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { block ROMVEC };
place in ROM_region { readonly };
place at start of IRAM_region { block CSTACK };

24
targets/TARGET_NUVOTON/TARGET_NANO100/device/cmsis_nvic.h
View File

@ -23,18 +23,26 @@
#define NVIC_USER_IRQ_NUMBER 32
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
/* Avoid optimization error on e.g. ARMC6
*
* If NVIC_FLASH_VECTOR_ADDRESS is directly defined as 0, the compiler would see it
* as NULL, and deliberately optimize NVIC_GetVector to an undefined instruction -
* trapping because we're accessing an array at NULL.
*
* A suggested solution by Arm is to define NVIC_FLASH_VECTOR_ADDRESS as a symbol
* instead to avoid such unwanted optimization.
*/
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ER_IROM1$$Base;
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IROM1$$Base)
#elif defined(__ICCARM__)
# pragma section = "IRAMVEC"
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
#pragma section = "ROMVEC"
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t) __section_begin("ROMVEC"))
#elif defined(__GNUC__)
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
extern uint32_t __vector_table;
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t) &__vector_table)
#endif
#define NVIC_FLASH_VECTOR_ADDRESS 0
#ifdef __cplusplus
extern "C" {
#endif

11
targets/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/ublox_low_level_api.c
View File

@ -59,12 +59,14 @@ void ublox_mdm_powerOn(int usb)
// turn on the mode by enabling power with power on pin low and correct USB detect level
gpio_init_out_ex(&gpio, MDMUSBDET, usb ? 1 : 0); // USBDET: 0=disabled, 1=enabled
if (!modemOn) { // enable modem
modemOn = true;
gpio_init_out_ex(&gpio, MDMEN, 1); // LDOEN: 1=on
wait_ms(1); // wait until supply switched off
// now we can safely enable the level shifters
gpio_init_out_ex(&gpio, MDMLVLOE, 0); // LVLEN: 0=enabled (uart/gpio)
if (gpsOn)
if (gpsOn) {
gpio_init_out_ex(&gpio, MDMILVLOE, 1); // ILVLEN: 1=enabled (i2c)
}
}
}
@ -78,13 +80,13 @@ void ublox_mdm_powerOff(void)
{
gpio_t gpio;
if (modemOn) {
modemOn = false;
// diable all level shifters
gpio_init_out_ex(&gpio, MDMILVLOE, 0); // ILVLEN: 0=disabled (i2c)
gpio_init_out_ex(&gpio, MDMLVLOE, 1); // LVLEN: 1=disabled (uart/gpio)
gpio_init_out_ex(&gpio,MDMUSBDET, 0); // USBDET: 0=disabled
// now we can savely switch off the ldo
gpio_init_out_ex(&gpio, MDMEN, 0); // LDOEN: 0=off
modemOn = false;
}
}
@ -92,11 +94,13 @@ void ublox_gps_powerOn(void)
{
gpio_t gpio;
if (!gpsOn) {
gpsOn = true;
// switch on power supply
gpio_init_out_ex(&gpio, GPSEN, 1); // LDOEN: 1=on
wait_ms(1); // wait until supply switched off
if (modemOn)
if (modemOn) {
gpio_init_out_ex(&gpio, MDMILVLOE, 1); // ILVLEN: 1=enabled (i2c)
}
}
}
@ -104,6 +108,7 @@ void ublox_gps_powerOff(void)
{
gpio_t gpio;
if (gpsOn) {
gpsOn = false;
gpio_init_out_ex(&gpio, MDMILVLOE, 0); // ILVLEN: 0=disabled (i2c)
gpio_init_out_ex(&gpio, GPSEN, 0); // LDOEN: 0=off
}

36
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct
View File

@ -28,29 +28,51 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
#if !defined(MBED_APP_START)
#ifdef DISABLE_POST_BINARY_HOOK
#define MBED_APP_START 0x08000000
#else
#define MBED_APP_START 0x08010000
#endif
#endif
#if !defined(MBED_APP_SIZE)
#ifdef DISABLE_POST_BINARY_HOOK
#define MBED_APP_SIZE 0x80000
#else
#define MBED_APP_SIZE (0x80000 - 0x10000)
#endif
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
; FIRST 64 KB FLASH FOR BOOTLOADER
; REST 448 KB FLASH FOR APPLICATION
LR_IROM1 0x08010000 0x70000 { ; load region size_region
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x20000
#define MBED_VECTTABLE_RAM_START (MBED_RAM_START)
#define MBED_VECTTABLE_RAM_SIZE 0x198
#define MBED_RAM0_START (MBED_RAM_START + MBED_VECTTABLE_RAM_SIZE)
#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE)
ER_IROM1 0x08010000 0x70000 { ; load address = execution address
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) if not using MTS bootloader
; If using MTS bootloader, FIRST 64 KB FLASH FOR BOOTLOADER, REST 448 KB FLASH FOR APPLICATION
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
RW_IRAM1 (0x20000000+0x198) (0x20000-0x198-Stack_Size) { ; RW data
RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x20000000+0x20000) EMPTY -Stack_Size { ; stack
ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
}
}

23
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
View File

@ -1,17 +1,32 @@
/* Linker script for STM32F411 */
#if !defined(MBED_APP_START)
#ifdef DISABLE_POST_BINARY_HOOK
#define MBED_APP_START 0x08000000
#else
#define MBED_APP_START 0x08010000
#endif
#endif
#if !defined(MBED_APP_SIZE)
#ifdef DISABLE_POST_BINARY_HOOK
#define MBED_APP_SIZE 0x80000
#else
#define MBED_APP_SIZE (0x80000 - 0x10000)
#endif
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
/* First 64kB of flash reserved for bootloader */
/* Other 448kB for application */
FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
}

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S
View File

@ -66,8 +66,8 @@ __HeapLimit:
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.globl g_pfnVectors
g_pfnVectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
@ -171,7 +171,7 @@ __isr_vector:
.long SPI4_IRQHandler /* SPI4 */
.long SPI5_IRQHandler /* SPI5 */
.size __isr_vector, . - __isr_vector
.size g_pfnVectors, . - g_pfnVectors
.text
.thumb

11
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf
View File

@ -1,7 +1,12 @@
if ((!isdefinedsymbol(MBED_APP_START)) && isdefinedsymbol(DISABLE_POST_BINARY_HOOK)) { define symbol MBED_APP_START = 0x08000000; }
if ((!isdefinedsymbol(MBED_APP_START)) && !isdefinedsymbol(DISABLE_POST_BINARY_HOOK)) { define symbol MBED_APP_START = 0x08010000; }
if ((!isdefinedsymbol(MBED_APP_SIZE)) && isdefinedsymbol(DISABLE_POST_BINARY_HOOK)) { define symbol MBED_APP_SIZE = 0x80000; }
if ((!isdefinedsymbol(MBED_APP_SIZE)) && !isdefinedsymbol(DISABLE_POST_BINARY_HOOK)) { define symbol MBED_APP_SIZE = 0x70000; }
/* [ROM = 512kb = 0x80000] */
define symbol __intvec_start__ = 0x08010000;
define symbol __region_ROM_start__ = 0x08010000;
define symbol __region_ROM_end__ = 0x0807FFFF;
define symbol __intvec_start__ = MBED_APP_START;
define symbol __region_ROM_start__ = MBED_APP_START;
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;

55
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/flash_data.h Normal file
View File

@ -0,0 +1,55 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_FLASH_DATA_H
#define MBED_FLASH_DATA_H
#include "device.h"
#include <stdint.h>
#if DEVICE_FLASH
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* FLASH SIZE */
#define FLASH_SIZE (uint32_t) 0x80000
/* Base address of the Flash sectors Bank 1 */
#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
#endif
#endif

3
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c
View File

@ -36,6 +36,7 @@
#include "stm32f4xx.h"
#include "mbed_debug.h"
#include "nvic_addr.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@ -96,7 +97,7 @@ void SystemInit(void)
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
#endif
}

13
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct
View File

@ -29,7 +29,13 @@
#define VECTOR_SIZE 0x188
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
#define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
#define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE+MBED_CRASH_REPORT_RAM_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
@ -39,7 +45,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
}
RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
.ANY (+RW +ZI)
}

32
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct
View File

@ -3,24 +3,50 @@
; *** Scatter-Loading Description File ***
; *****************************************
; 1 MB FLASH (0x100000) + 192 KB SRAM (0x30000) + 64 KB CCBRAM (0x10000)+ 4 KB BKPSRAM
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x30000
#define MBED_VECTTABLE_RAM_START (MBED_RAM_START)
#define MBED_VECTTABLE_RAM_SIZE 0x1B0
#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE)
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000188 0x0001FE78-Stack_Size {
; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x10000000 0x00010000 { ; CCM
.ANY (CCMRAM)
}
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
}
ARM_LIB_STACK (0x20000188+0x0001FE78) EMPTY -Stack_Size { ; stack
}
}

14
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld
View File

@ -6,6 +6,8 @@
STACK_SIZE = MBED_BOOT_STACK_SIZE;
M_CRASH_DATA_RAM_SIZE = 0x100;
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
@ -85,6 +87,18 @@ SECTIONS
__etext = .;
_sidata = .;
.crash_data_ram :
{
. = ALIGN(8);
__CRASH_DATA_RAM__ = .;
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
KEEP(*(.keep.crash_data_ram))
*(.m_crash_data_ram) /* This is a user defined section */
. += M_CRASH_DATA_RAM_SIZE;
. = ALIGN(8);
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
} > RAM
.data : AT (__etext)
{
__data_start__ = .;

9
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf
View File

@ -8,7 +8,9 @@ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
define symbol __NVIC_start__ = 0x20000000;
define symbol __NVIC_end__ = 0x20000187;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000188;
define symbol __region_CRASH_DATA_RAM_start__ = 0x20000188;
define symbol __region_CRASH_DATA_RAM_end__ = 0x20000287;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000288;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
@ -20,8 +22,13 @@ define symbol __ICFEDIT_size_heap__ = 0x8000;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
/* Define Crash Data Symbols */
define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__;
define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__;
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

2
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ONBOARD_UBLOX.cpp
View File

@ -25,7 +25,7 @@ using namespace mbed;
CellularDevice *CellularDevice::get_target_default_instance()
{
#if defined(TARGET_UBLOX_C030_R410M)
#if defined(TARGET_UBLOX_C030_R41XM)
static UARTSerial serial(MDMTXD, MDMRXD, MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
static ONBOARD_UBLOX_AT device(&serial);
#elif defined(TARGET_UBLOX_C030_N211)

2
targets/TARGET_STM/TARGET_STM32F7/flash_api.c
View File

@ -284,7 +284,7 @@ static uint32_t GetSectorBase(uint32_t SectorId)
int i = 0;
uint32_t address_sector = FLASH_BASE;
for(i=0;i<SectorId;i++){
for (i = 0; i < SectorId; i++) {
address_sector += GetSectorSize(i);
}
return address_sector;

12
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c
View File

@ -347,36 +347,36 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io NMI
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to W25Q128JVPIQ
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io AD3
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to W25Q128JVPIQ
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io SPI_A_MOSI
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to W25Q128JVPIQ
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io SPI_A_MISO
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to W25Q128JVPIQ
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io IO2
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to W25Q128JVPIQ
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_CS0
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to W25Q128JVPIQ
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to MT25QL128ABA1EW7
{NC, NC, 0}
};

24
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/PeripheralPins.c
View File

@ -141,38 +141,38 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
{PA_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
{PB_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
{PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
{PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PA_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
{PA_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
{PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
{PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
{PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JTDO
{PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};

128
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/system_clock.c
View File

@ -62,7 +62,7 @@ static void Configure_RF_Clock_Sources(void)
{
static uint8_t RF_ON = 0;
if ( !RF_ON ) {
if (!RF_ON) {
// Reset backup domain
if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
// Write twice the value to flush the APB-AHB bridge
@ -97,18 +97,17 @@ static void Configure_RF_Clock_Sources(void)
static void Config_HSE(void)
{
OTP_ID0_t * p_otp;
OTP_ID0_t *p_otp;
/**
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
if (p_otp)
{
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
}
/**
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
if (p_otp) {
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
}
return;
return;
}
@ -122,7 +121,7 @@ static void Config_HSE(void)
void SetSysClock(void)
{
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
if (SetSysClock_PLL_HSE(1) == 0)
@ -157,7 +156,7 @@ void SetSysClock(void)
#if DEBUG_MCO == 1
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 64 MHz
#endif
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
@ -166,66 +165,63 @@ void SetSysClock(void)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
Config_HSE();
Config_HSE();
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
/** Initializes the peripherals clocks
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0; // FAIL
}
/** Initializes the peripherals clocks
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
return 0; // FAIL
}
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
/**
* Set RNG on HSI48
*/
LL_RCC_HSI48_Enable();
while(!LL_RCC_HSI48_IsReady());
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
/**
* Set RNG on HSI48
*/
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady());
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
return 1;
return 1;
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

6
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_MICRO/stm32wb55xx.sct
View File

@ -34,11 +34,11 @@
#endif
#if !defined(MBED_APP_SIZE)
; 512KB FLASH
#define MBED_APP_SIZE 0x80000
; 768KB FLASH
#define MBED_APP_SIZE 0xC0000
#endif
; 512KB FLASH (0x80000) + 192KB SRAM (0x30000) + Shared mem
; 768KB FLASH (0xC0000) + 192KB SRAM (0x30000) + Shared mem
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address

6
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_STD/stm32wb55xx.sct
View File

@ -34,8 +34,8 @@
#endif
#if !defined(MBED_APP_SIZE)
; 512KB FLASH
#define MBED_APP_SIZE 0x80000
; 768KB FLASH
#define MBED_APP_SIZE 0xC0000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
@ -44,7 +44,7 @@
#define Stack_Size MBED_BOOT_STACK_SIZE
; 512KB FLASH (0x80000) + 192KB SRAM (0x30000) + Shared mem
; 768KB FLASH (0xC0000) + 192KB SRAM (0x30000) + Shared mem
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address

2
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld
View File

@ -3,7 +3,7 @@
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 512K
#define MBED_APP_SIZE 768K
#endif
#if !defined(MBED_BOOT_STACK_SIZE)

4
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_IAR/stm32wb55xx.icf
View File

@ -17,9 +17,9 @@
*/
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0xC0000; }
/* [ROM = 512kb = 0x80000] */
/* [ROM = 768kb = 0xC0000] */
define symbol __intvec_start__ = MBED_APP_START;
define symbol __region_ROM_start__ = MBED_APP_START;
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;

4
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/flash_data.h
View File

@ -37,8 +37,8 @@
#undef FLASH_SIZE
#endif
// Only the first 128 pages are accessible when security is enabled
#define FLASH_SIZE ((uint32_t)0x80000) // 128 pages x 4 Kbytes = 512 Kbytes
// Only the first the application side is accessible.
#define FLASH_SIZE ((uint32_t)0xC0000) // 768 Kbytes
#endif
#endif

8
targets/TARGET_STM/TARGET_STM32WB/flash_api.c
View File

@ -77,7 +77,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
#if defined(CFG_HW_FLASH_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID));
#endif
/* Unlock the Flash to enable the flash control register access */
@ -109,7 +109,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
HAL_FLASH_Lock();
#if defined(CFG_HW_FLASH_SEMID)
LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
#endif
return status;
@ -141,7 +141,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
#if defined(CFG_HW_FLASH_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID));
#endif
/* Unlock the Flash to enable the flash control register access */
@ -182,7 +182,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
HAL_FLASH_Lock();
#if defined(CFG_HW_FLASH_SEMID)
LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
#endif
return status;

120
targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c
View File

@ -44,103 +44,95 @@ extern void restore_timer_ctx(void);
extern int serial_is_tx_ongoing(void);
extern int mbed_sdk_inited;
static void Switch_On_HSI( void )
static void Switch_On_HSI(void)
{
LL_RCC_HSI_Enable();
while(!LL_RCC_HSI_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
LL_RCC_HSI_Enable();
while (!LL_RCC_HSI_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
return;
return;
}
static void LPM_EnterStopMode(void)
{
/**
* This function is called from CRITICAL SECTION
*/
/**
* This function is called from CRITICAL SECTION
*/
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
{
if( LL_PWR_IsActiveFlag_C2DS() )
{
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
if (! LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID)) {
if (LL_PWR_IsActiveFlag_C2DS()) {
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
Switch_On_HSI();
Switch_On_HSI();
}
} else {
Switch_On_HSI();
}
}
else
{
Switch_On_HSI();
}
/* Release RCC semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
/* Release RCC semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
return;
return;
}
static void LPM_ExitStopMode(void)
{
/**
* This function is called from CRITICAL SECTION
*/
/**
* This function is called from CRITICAL SECTION
*/
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
if( (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) || (LL_PWR_IsActiveFlag_C1STOP() != 0) )
{
LL_PWR_ClearFlag_C1STOP_C1STB();
if ((LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) || (LL_PWR_IsActiveFlag_C1STOP() != 0)) {
LL_PWR_ClearFlag_C1STOP_C1STB();
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
if(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{
LL_RCC_HSE_Enable();
while(!LL_RCC_HSE_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
}
else
{
/**
* As long as the current application is fine with HSE as system clock source,
* there is nothing to do here
*/
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
LL_RCC_HSE_Enable();
while (!LL_RCC_HSE_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
} else {
/**
* As long as the current application is fine with HSE as system clock source,
* there is nothing to do here
*/
}
/* Release RCC semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
/* Release RCC semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
}
return;
return;
}
void HW_LPM_StopMode(void)
{
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
/**
* This option is used to ensure that store operations are completed
*/
/**
* This option is used to ensure that store operations are completed
*/
#if defined ( __CC_ARM)
__force_stores();
__force_stores();
#endif
__WFI();
__WFI();
return;
return;
}
/* STM32WB has very specific needs to handling STOP mode.

48
targets/TARGET_STM/mbed_crc_api.c
View File

@ -25,7 +25,7 @@ static uint32_t crc_mask;
+-------------------------+---------------------------------------+---------------+
| Polynomial coefficients | Fixed to 0x4C11DB7 | Programmable |
+-------------------------+---------------------------------------+---------------+
#1 The STM32F0 series which supported polynomial in 7, 8, 16, 32 bits as below list:
STM32F071xB
STM32F072xB
@ -77,24 +77,23 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
current_state.Init.InitValue = config->initial_xor;
current_state.Init.GeneratingPolynomial = config->polynomial;
switch (config->width)
{
case HAL_CRC_LENGTH_32B:
current_state.Init.CRCLength = CRC_POLYLENGTH_32B;
break;
case HAL_CRC_LENGTH_16B:
current_state.Init.CRCLength = CRC_POLYLENGTH_16B;
break;
case HAL_CRC_LENGTH_8B:
current_state.Init.CRCLength = CRC_POLYLENGTH_8B;
break;
case HAL_CRC_LENGTH_7B:
current_state.Init.CRCLength = CRC_POLYLENGTH_7B;
break;
default:
MBED_ASSERT(false);
break;
}
switch (config->width) {
case HAL_CRC_LENGTH_32B:
current_state.Init.CRCLength = CRC_POLYLENGTH_32B;
break;
case HAL_CRC_LENGTH_16B:
current_state.Init.CRCLength = CRC_POLYLENGTH_16B;
break;
case HAL_CRC_LENGTH_8B:
current_state.Init.CRCLength = CRC_POLYLENGTH_8B;
break;
case HAL_CRC_LENGTH_7B:
current_state.Init.CRCLength = CRC_POLYLENGTH_7B;
break;
default:
MBED_ASSERT(false);
break;
}
current_state.Init.InputDataInversionMode =
config->reflect_in ? CRC_INPUTDATA_INVERSION_BYTE
@ -104,7 +103,7 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
: CRC_OUTPUTDATA_INVERSION_DISABLE;
#endif
if (HAL_CRC_Init(&current_state) != HAL_OK) {
if (HAL_CRC_Init(&current_state) != HAL_OK) {
MBED_ASSERT(false);
}
}
@ -124,21 +123,22 @@ uint32_t hal_crc_get_result(void)
/* The CRC-7 SD needs to shift left by 1 bit after obtaining the result, but the output
* inversion of CRC peripheral will convert the result before shift left by 1 bit, so
* the result seems to have shifted after the conversion.
*
*
* Example:
* [Gerenal setps]
* 1. Before output inversion: 0x75 (0111 0101)
* 2. Left shift by 1 bit: 0xEA (1110 1010)
* 3. After output inversion: 0x57 (0101 0111)
*
*
* [STM32 CRC peripheral steps]
* 1. Before output inversion: 0x75 (0111 0101)
* 2. After output inversion: 0x57 (0101 0111) <= no needs shift again
*/
if (current_state.Init.CRCLength == CRC_POLYLENGTH_7B &&
current_state.Init.GeneratingPolynomial == POLY_7BIT_SD &&
current_state.Init.OutputDataInversionMode == CRC_OUTPUTDATA_INVERSION_DISABLE)
current_state.Init.GeneratingPolynomial == POLY_7BIT_SD &&
current_state.Init.OutputDataInversionMode == CRC_OUTPUTDATA_INVERSION_DISABLE) {
result = result << 1;
}
#endif
return (result ^ final_xor) & crc_mask;
}

8
targets/TARGET_STM/mbed_rtx.h
View File

@ -141,10 +141,10 @@
#if (defined(TARGET_STM32L475VG) || defined(TARGET_STM32L443RC))
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
#define HEAP_START Image$$ARM_LIB_HEAP$$ZI$$Base
#define HEAP_SIZE Image$$ARM_LIB_HEAP$$ZI$$Length
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
#define HEAP_START Image$$ARM_LIB_HEAP$$ZI$$Base
#define HEAP_SIZE Image$$ARM_LIB_HEAP$$ZI$$Length
#endif
#endif

3
targets/TARGET_STM/stm_spi_api.c
View File

@ -92,7 +92,8 @@ void init_spi(spi_t *obj)
}
}
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
{
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);

14
targets/TARGET_STM/trng_api.c
View File

@ -43,7 +43,7 @@ void trng_init(trng_t *obj)
}
#if !defined(TARGET_STM32WB)
/* Because M0 core of WB also needs RG RNG is already clocked by default */
/* Because M0 core of WB also needs RG RNG is already clocked by default */
#if defined(RCC_PERIPHCLK_RNG)
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
@ -70,7 +70,7 @@ void trng_init(trng_t *obj)
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RNG_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
#endif
HAL_RNG_Init(&obj->handle);
@ -78,7 +78,7 @@ void trng_init(trng_t *obj)
HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy);
#if defined(CFG_HW_RNG_SEMID)
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RNG_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RNG_SEMID, 0);
#endif
}
@ -86,14 +86,14 @@ void trng_free(trng_t *obj)
{
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RNG_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
#endif
/*Disable the RNG peripheral */
HAL_RNG_DeInit(&obj->handle);
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RNG_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RNG_SEMID, 0);
#else
/* RNG Peripheral clock disable - assume we're the only users of RNG */
__HAL_RCC_RNG_CLK_DISABLE();
@ -110,7 +110,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RNG_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
#endif
/* Get Random byte */
@ -133,7 +133,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RNG_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RNG_SEMID, 0);
#endif
return (ret);

11
targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralNames.h
View File

@ -136,6 +136,17 @@ typedef enum {
} UARTName;
#endif
#if DEVICE_CAN
typedef enum {
#ifdef CAN0_BASE
CAN_0 = (int)CAN0_BASE,
#endif
#ifdef CAN1_BASE
CAN_1 = (int)CAN1_BASE,
#endif
} CANName;
#endif
#if DEVICE_QSPI
typedef enum {
#ifdef QSPI0_BASE

331
targets/TARGET_Silicon_Labs/TARGET_EFM32/can_api.c Normal file
View File

@ -0,0 +1,331 @@
/* mbed Microcontroller Library
* Copyright (c) 2019 ToolSense
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "can_api.h"
#include "clocking.h"
#if DEVICE_CAN
#include "cmsis.h"
#include "pinmap.h"
#include "pinmap_function.h"
#include "PeripheralPins.h"
#include "mbed_assert.h"
#include "em_cmu.h"
#include "em_can.h"
static uint32_t can_irq_ids[CAN_COUNT] = {0};
static can_irq_handler irq_handler;
// CAN bus interfaces
#define CAN_TX_IF 0
#define CAN_RX_IF 1
void can_init(can_t *obj, PinName rd, PinName td)
{
can_init_freq(obj, rd, td, 100000);
}
void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
{
CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RX);
CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TX);
obj->instance = (CAN_TypeDef *)pinmap_merge(can_rd, can_td);
CMU_Clock_TypeDef cmuClock_number;
switch ((CANName)obj->instance) {
#ifdef CAN0
case CAN_0:
cmuClock_number = cmuClock_CAN0;
break;
#endif
#ifdef CAN1
case CAN_1:
cmuClock_number = cmuClock_CAN1;
break;
#endif
}
MBED_ASSERT((unsigned int)rd != NC);
MBED_ASSERT((unsigned int)td != NC);
// Configure CAN pins
pinmap_pinout(rd, PinMap_CAN_RX);
pinmap_pinout(td, PinMap_CAN_TX);
CMU_ClockEnable(cmuClock_number, true);
CAN_Init_TypeDef CanInit = CAN_INIT_DEFAULT;
CanInit.bitrate=hz;
CAN_Init(obj->instance, &CanInit);
CAN_SetMode(obj->instance, canModeNormal);
uint32_t loc_rd = pin_location(rd, PinMap_CAN_RX);
uint32_t loc_td = pin_location(td, PinMap_CAN_TX);
CAN_SetRoute(obj->instance, true, loc_rd, loc_td);
// Add pull-ups
if (rd != NC) {
pin_mode(rd, gpioModeInput);
}
if (td != NC) {
pin_mode(td, gpioModePushPull);
}
CAN_ConfigureMessageObject(obj->instance, CAN_TX_IF, 1, true, true, false, true, true);
CAN_ConfigureMessageObject(obj->instance, CAN_RX_IF, 2, true, false, false, true, true);
CAN_MessageObject_TypeDef receiver;
receiver.msgNum = 2;
receiver.id = 0;
receiver.mask = 0;
receiver.extended = false;
receiver.extendedMask = false;
CAN_SetIdAndFilter(obj->instance, CAN_RX_IF, true, &receiver, true);
}
void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
{
int index = 0;
switch ((CANName)obj->instance) {
#ifdef CAN0
case CAN_0:
index = 0;
break;
#endif
#ifdef CAN1
case CAN_1:
index = 1;
break;
#endif
}
irq_handler = handler;
can_irq_ids[index] = id;
}
void can_irq_free(can_t *obj)
{
CAN_MessageIntDisable(obj->instance, _CAN_IF0IEN_MESSAGE_MASK);
CAN_MessageIntClear(obj->instance, 0xFFFFFFFF);
switch ((CANName)obj->instance) {
#ifdef CAN0
case CAN_0:
NVIC_DisableIRQ(CAN0_IRQn);
break;
#endif
#ifdef CAN1
case CAN_1:
NVIC_DisableIRQ(CAN1_IRQn);
break;
#endif
}
}
void can_free(can_t *obj)
{
CAN_Enable(obj->instance, false);
}
int can_frequency(can_t *obj, int f)
{
CAN_Init_TypeDef CanInit = CAN_INIT_DEFAULT;
CanInit.bitrate=f;
CAN_SetBitTiming(obj->instance,
CanInit.bitrate,
CanInit.propagationTimeSegment,
CanInit.phaseBufferSegment1,
CanInit.phaseBufferSegment2,
CanInit.synchronisationJumpWidth);
return 0;
}
int can_write(can_t *obj, CAN_Message msg, int cc)
{
CAN_MessageObject_TypeDef message;
message.id = msg.id;
message.msgNum = 1;
if (msg.format == 0) message.extended = false;
else message.extended = true;
message.dlc = msg.len;
for (int i = 0; i < message.dlc; ++i) {
message.data[i] = (uint32_t)msg.data[i];
}
CAN_SendMessage(obj->instance, CAN_TX_IF, &message, true);
return 1;
}
int can_read(can_t *obj, CAN_Message *msg, int handle)
{
CAN_MessageObject_TypeDef receiver;
if (CAN_HasNewdata(obj->instance)) {
receiver.msgNum = 2;
receiver.extended = false;
receiver.extendedMask = false;
CAN_ReadMessage(obj->instance, CAN_RX_IF, &receiver);
msg->id = receiver.id;
msg->len = receiver.dlc;
for (int i = 0; i < receiver.dlc; ++i) {
msg->data[i] = (unsigned char)receiver.data[i];
}
return 1;
}
return 0;
}
void can_reset(can_t *obj)
{
CAN_Reset(obj->instance);
}
unsigned char can_rderror(can_t *obj)
{
return ((obj->instance->ERRCNT>>_CAN_ERRCNT_REC_SHIFT)&0xFF);
}
unsigned char can_tderror(can_t *obj)
{
return ((obj->instance->ERRCNT)&0xFF);
}
void can_monitor(can_t *obj, int silent)
{
CanMode mode = MODE_NORMAL;
if (silent) {
mode = MODE_SILENT;
}
CAN_SetMode(obj->instance, mode);
}
int can_mode(can_t *obj, CanMode mode)
{
CAN_SetMode(obj->instance, mode);
return 1;
}
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
{
CAN_MessageObject_TypeDef message;
message.msgNum = 2;
message.id = id;
message.mask = mask;
if (format == CANStandard) {
message.extended = false;
message.extendedMask = false;
} else {
message.extended = true;
message.extendedMask = true;
}
CAN_SetIdAndFilter(obj->instance, CAN_RX_IF, true, &message, true);
return handle;
}
void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
{
uint32_t ier = _CAN_IF0IEN_MESSAGE_MASK;
if (enable) {
CAN_MessageIntEnable(obj->instance, ier);
} else {
CAN_MessageIntDisable(obj->instance, ier);
}
switch ((CANName)obj->instance) {
#ifdef CAN0
case CAN_0:
NVIC_SetVector(CAN0_IRQn, (uint32_t)CAN0_IRQHandler);
NVIC_EnableIRQ(CAN0_IRQn);
break;
#endif
#ifdef CAN1
case CAN_1:
NVIC_SetVector(CAN1_IRQn, (uint32_t)CAN1_IRQHandler);
NVIC_EnableIRQ(CAN1_IRQn);
break;
#endif
}
}
static void can_irq(CANName name, int id)
{
CAN_TypeDef *can;
can = (CAN_TypeDef *)name;
if (can->STATUS & CAN_STATUS_RXOK) {
irq_handler(can_irq_ids[id], IRQ_RX);
CAN_MessageIntClear(can, 0xFFFFFFFF);
}
if (can->STATUS & CAN_STATUS_TXOK) {
irq_handler(can_irq_ids[id], IRQ_TX);
CAN_MessageIntClear(can, 0xFFFFFFFF);
}
}
#ifdef CAN0
void CAN0_IRQHandler(void)
{
can_irq(CAN_0, 0);
}
#endif
#ifdef CAN1
void CAN1_IRQHandler(void)
{
can_irq(CAN_1, 1);
}
#endif
const PinMap *can_rd_pinmap()
{
return PinMap_CAN_TX;
}
const PinMap *can_td_pinmap()
{
return PinMap_CAN_RX;
}
#endif //DEVICE_CAN

165
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_can.h
View File

@ -1,33 +1,32 @@
/***************************************************************************//**
* @file em_can.h
* @file
* @brief Controller Area Network API
* @version 5.3.3
* @version 5.7.2
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_CAN_H
@ -61,9 +60,9 @@ extern "C" {
******************************** ENUMS ************************************
******************************************************************************/
/** CAN Status codes */
/** CAN Status codes. */
typedef enum {
/** No error occurred during last CAN bus event. */
/** No error occurred during the last CAN bus event. */
canErrorNoError = CAN_STATUS_LEC_NONE,
/**
@ -78,36 +77,36 @@ typedef enum {
/** The message this CAN Core transmitted was not acknowledged by another node. */
canErrorAck = CAN_STATUS_LEC_ACK,
/** Wrong monitored bus value : dominant when the module wanted to send a recessive. */
/** A wrong monitored bus value : dominant when the module wants to send a recessive. */
canErrorBit1 = CAN_STATUS_LEC_BIT1,
/** Wrong monitored bus value : recessive when the module intended to send a dominant. */
/** A wrong monitored bus value : recessive when the module intends to send a dominant. */
canErrorBit0 = CAN_STATUS_LEC_BIT0,
/** CRC check sum incorrect. */
canErrorCrc = CAN_STATUS_LEC_CRC,
/** Unused. No new error since the cpu wrote this value */
/** Unused. No new error since the CPU wrote this value. */
canErrorUnused = CAN_STATUS_LEC_UNUSED
} CAN_ErrorCode_TypeDef;
/** CAN peripheral mode */
/** CAN peripheral mode. */
typedef enum {
/** CAN peripheral in Normal mode : ready to send and receive messages */
/** CAN peripheral in Normal mode : ready to send and receive messages. */
canModeNormal,
/** CAN peripheral in Basic mode : no use of the RAM */
/** CAN peripheral in Basic mode : no use of the RAM. */
canModeBasic,
/**
* CAN peripheral in Loopback mode : input from the CAN bus is disregarded
* and comes from TX instead
* and comes from TX instead.
*/
canModeLoopBack,
/**
* CAN peripheral in SilentLoopback mode : input from the CAN bus is
* disregarded and comes from TX instead ; no output on the CAN bus
* disregarded and comes from TX instead ; no output on the CAN bus.
*/
canModeSilentLoopBack,
@ -122,57 +121,57 @@ typedef enum {
******************************* STRUCTS ***********************************
******************************************************************************/
/** CAN Message Object TypeDef structure. LSBs is used */
/** CAN Message Object TypeDef structure. LSBs is used. */
typedef struct {
/** Message number of this Message Object, [1 - 32] */
/** A message number of this Message Object, [1 - 32]. */
uint8_t msgNum;
/** Id extended if true, standard if false */
/** ID extended if true, standard if false. */
bool extended;
/**
* Id of the message, with 11 bits (standard) or 28 bits (extended).
* LSBs are used for both of them
* ID of the message with 11 bits (standard) or 28 bits (extended).
* LSBs are used for both.
*/
uint32_t id;
/** Data Length Code [0 - 8] */
/** Data Length Code [0 - 8]. */
uint8_t dlc;
/** Pointer to the data, [0 - 8] bytes */
/** A pointer to data, [0 - 8] bytes. */
uint8_t data[8];
/** Mask for id filtering */
/** A mask for ID filtering. */
uint32_t mask;
/** Enable the use of 'extended' value for filtering */
/** Enable the use of 'extended' value for filtering. */
bool extendedMask;
/** Enable the use of 'direction' value for filtering */
/** Enable the use of 'direction' value for filtering. */
bool directionMask;
} CAN_MessageObject_TypeDef;
/** CAN initialization structure. */
typedef struct {
/** true to set the CAN Device in normal mode after init */
/** True to set the CAN Device in normal mode after initialization. */
bool enable;
/** True to reset messages during initialization */
/** True to reset messages during initialization. */
bool resetMessages;
/** Default bitrate */
/** Default bitrate. */
uint32_t bitrate;
/** Default Propagation Time Segment */
/** Default Propagation Time Segment. */
uint8_t propagationTimeSegment;
/** Default Phase Buffer Segment 1 */
/** Default Phase Buffer Segment 1. */
uint8_t phaseBufferSegment1;
/** Default Phase Buffer Segment 2 */
/** Default Phase Buffer Segment 2. */
uint8_t phaseBufferSegment2;
/** Default Synchronisation Jump Width */
/** Default Synchronisation Jump Width. */
uint8_t synchronisationJumpWidth;
} CAN_Init_TypeDef;
@ -180,17 +179,17 @@ typedef struct {
* Default initialization of CAN_Init_TypeDef. The total duration of a bit with
* these default parameters is 10 tq (time quantum : tq = brp/fsys, brp being
* the baudrate prescaler and being set according to the wanted bitrate, fsys
* beeing the CAN Device frequency).
* beeing the CAN device frequency).
*/
#define CAN_INIT_DEFAULT \
{ \
true, /** Set the CAN Device in normal mode after init */ \
true, /** Reset messages during initialization */ \
100000, /** Set bitrate to 100 000 */ \
1, /** Set the Propagation Time Segment to 1 */ \
4, /** Set the Phase Buffer Segment 1 to 4 */ \
4, /** Set the Phase Buffer Segment 2 to 4 */ \
1 /** Set the Synchronization Jump Width to 1 */ \
#define CAN_INIT_DEFAULT \
{ \
true, /** Set the CAN Device in normal mode after initialization. */ \
true, /** Reset messages during initialization. */ \
100000, /** Set bitrate to 100 000 */ \
1, /** Set the Propagation Time Segment to 1. */ \
4, /** Set the Phase Buffer Segment 1 to 4. */ \
4, /** Set the Phase Buffer Segment 2 to 4. */ \
1 /** Set the Synchronization Jump Width to 1. */ \
}
/*******************************************************************************
@ -264,11 +263,11 @@ void CAN_SendRequest(CAN_TypeDef *can,
* Enable the Host Controller to send messages.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] enable
* true to enable CAN device, false to disable it. If the CAN device is
* enabled, it goes in normal mode (the default working mode).
* True to enable CAN device, false to disable it. If the CAN device is
* enabled, it goes to normal mode (the default working mode).
******************************************************************************/
__STATIC_INLINE void CAN_Enable(CAN_TypeDef *can, bool enable)
{
@ -277,13 +276,13 @@ __STATIC_INLINE void CAN_Enable(CAN_TypeDef *can, bool enable)
/***************************************************************************//**
* @brief
* Gives the communication capabilities state.
* Give the communication capabilities state.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* true if the Host Controller can send messages, false otherwise.
* True if the Host Controller can send messages, false otherwise.
******************************************************************************/
__STATIC_INLINE bool CAN_IsEnabled(CAN_TypeDef *can)
{
@ -295,7 +294,7 @@ __STATIC_INLINE bool CAN_IsEnabled(CAN_TypeDef *can)
* Waiting function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
@ -328,13 +327,13 @@ __STATIC_INLINE CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(CAN_TypeDef *can)
/***************************************************************************//**
* @brief
* Indicates which messages objects have received new data.
* Indicates which message objects have received new data.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* State of MESSAGEDATA register indicating which messages objects have received
* State of MESSAGEDATA register indicating which message objects have received
* new data.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_HasNewdata(CAN_TypeDef *can)
@ -347,7 +346,7 @@ __STATIC_INLINE uint32_t CAN_HasNewdata(CAN_TypeDef *can)
* Clear one or more pending CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* Pending CAN status interrupt source(s) to clear.
@ -362,7 +361,7 @@ __STATIC_INLINE void CAN_StatusIntClear(CAN_TypeDef *can, uint32_t flags)
* Disable CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to disable.
@ -377,7 +376,7 @@ __STATIC_INLINE void CAN_StatusIntDisable(CAN_TypeDef *can, uint32_t flags)
* Enable CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to enable.
@ -392,10 +391,10 @@ __STATIC_INLINE void CAN_StatusIntEnable(CAN_TypeDef *can, uint32_t flags)
* Get pending CAN status interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
* This function does not clear event bits.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* CAN interrupt source(s) pending.
@ -410,10 +409,10 @@ __STATIC_INLINE uint32_t CAN_StatusIntGet(CAN_TypeDef *can)
* Get pending and enabled CAN status interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
* This function does not clear event bits.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* CAN interrupt source(s) pending and enabled.
@ -431,7 +430,7 @@ __STATIC_INLINE uint32_t CAN_StatusIntGetEnabled(CAN_TypeDef *can)
* Set one or more CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to set to pending.
@ -446,10 +445,10 @@ __STATIC_INLINE void CAN_StatusIntSet(CAN_TypeDef *can, uint32_t flags)
* Get CAN status.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* Value of CAN register STATUS.
* A value of CAN register STATUS.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusGet(CAN_TypeDef *can)
{
@ -461,7 +460,7 @@ __STATIC_INLINE uint32_t CAN_StatusGet(CAN_TypeDef *can)
* Clear CAN status.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN status bits to clear.
@ -476,7 +475,7 @@ __STATIC_INLINE void CAN_StatusClear(CAN_TypeDef *can, uint32_t flags)
* Get the error count.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* Error count.
@ -491,7 +490,7 @@ __STATIC_INLINE uint32_t CAN_GetErrorCount(CAN_TypeDef *can)
* Clear one or more pending CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* Pending CAN message interrupt source(s) to clear.
@ -506,7 +505,7 @@ __STATIC_INLINE void CAN_MessageIntClear(CAN_TypeDef *can, uint32_t flags)
* Disable CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to disable.
@ -521,7 +520,7 @@ __STATIC_INLINE void CAN_MessageIntDisable(CAN_TypeDef *can, uint32_t flags)
* Enable CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to enable.
@ -536,10 +535,10 @@ __STATIC_INLINE void CAN_MessageIntEnable(CAN_TypeDef *can, uint32_t flags)
* Get pending CAN message interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
* This function does not clear event bits.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* CAN message interrupt source(s) pending.
@ -554,10 +553,10 @@ __STATIC_INLINE uint32_t CAN_MessageIntGet(CAN_TypeDef *can)
* Get CAN message interrupt flags that are pending and enabled.
*
* @note
* The event bits are not cleared by the use of this function.
* This function does not clear event bits.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* CAN message interrupt source(s) pending and enabled.
@ -575,10 +574,10 @@ __STATIC_INLINE uint32_t CAN_MessageIntGetEnabled(CAN_TypeDef *can)
* Set one or more CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to set to pending.
* CAN message interrupt source(s) to set as pending.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntSet(CAN_TypeDef *can, uint32_t flags)
{

363
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_can.c
View File

@ -1,33 +1,32 @@
/***************************************************************************//**
* @file em_can.c
* @file
* @brief Controller Area Network API
* @version 5.3.3
* @version 5.7.2
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#include "em_can.h"
@ -40,9 +39,9 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Macros to use the ID field in the CANn_MIRx_ARB register as a 11 bit
* standard id. The register field can be used for both an 11 bit standard
* id and a 29 bit extended id. */
/* Macros to use for the ID field in the CANn_MIRx_ARB register as an 11 bit
* standard ID. The register field can be used for both an 11 bit standard
* ID and a 29 bit extended ID. */
#define _CAN_MIR_ARB_STD_ID_SHIFT 18
#define _CAN_MIR_MASK_STD_SHIFT 18
#define _CAN_MIR_ARB_STD_ID_MASK 0x1FFC0000UL
@ -71,8 +70,8 @@
* multi-master serial bus for connecting microcontrollers and devices, also
* known as nodes, to communicate with each other in applications without a host
* computer. CAN is a message-based protocol, designed originally for automotive
* applications, but meanwhile used also in many other surroundings.
* The complexity of the node can range from a simple I/O device up to an
* applications, but also used in many other scenarios.
* The complexity of a node can range from a simple I/O device up to an
* embedded computer with a CAN interface and sophisticated software. The node
* may also be a gateway allowing a standard computer to communicate over a USB
* or Ethernet port to the devices on a CAN network. Devices are connected to
@ -92,10 +91,10 @@
* Initialize CAN.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] init
* Pointer to CAN initialization structure.
* A pointer to the CAN initialization structure.
******************************************************************************/
void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init)
{
@ -122,13 +121,13 @@ void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init)
* Get the CAN module frequency.
*
* @details
* There is an internal prescaler of 2 inside the CAN module.
* An internal prescaler of 2 is inside the CAN module.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @return
* Clock value
* A clock value.
******************************************************************************/
uint32_t CAN_GetClockFrequency(CAN_TypeDef *can)
{
@ -153,33 +152,33 @@ uint32_t CAN_GetClockFrequency(CAN_TypeDef *can)
* 'Message Lost' flag.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of the Message Object, [1 - 32].
* A message number of the Message Object, [1 - 32].
*
* @return
* true if a message was lost, false otherwise.
* True if a message was lost, false otherwise.
******************************************************************************/
bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
bool messageLost;
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in the correct range. */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_CONTROL
| CAN_MIR_CMDMASK_CLRINTPND;
/* Send reading request and wait (3 to 6 cpu cycle) */
/* Send reading request and wait (3 to 6 cpu cycle). */
CAN_SendRequest(can, interface, msgNum, true);
messageLost = mir->CTRL & _CAN_MIR_CTRL_MESSAGEOF_MASK;
@ -187,14 +186,14 @@ bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum)
if (messageLost) {
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD | CAN_MIR_CMDMASK_CONTROL;
/* Reset the 'MessageLost' bit */
/* Reset the 'MessageLost' bit. */
mir->CTRL &= ~_CAN_MIR_CTRL_MESSAGEOF_MASK;
/* Send reading request and wait (3 to 6 cpu cycle) */
/* Send reading request and wait (3 to 6 cpu cycle). */
CAN_SendRequest(can, interface, msgNum, true);
}
/* Return the state of the MESSAGEOF bit */
/* Return the state of the MESSAGEOF bit. */
return messageLost;
}
@ -203,16 +202,16 @@ bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum)
* Set the ROUTE registers.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] active
* Boolean to activate or not the ROUTE registers.
* A boolean indicating whether or not to activate the ROUTE registers.
*
* @param[in] pinRxLoc
* Location of the rx pin.
* A location of the RX pin.
*
* @param[in] pinTxLoc
* Location of the tx pin.
* A location of the TX pin.
******************************************************************************/
void CAN_SetRoute(CAN_TypeDef *can,
bool active,
@ -232,34 +231,34 @@ void CAN_SetRoute(CAN_TypeDef *can,
/***************************************************************************//**
* @brief
* Set the bitrate and its parameters
* Set the bitrate and its parameters.
*
* @details
* There are multiple parameters which need to be properly configured.
* Please refer to the reference manual for a detailed description.
* Multiple parameters need to be properly configured.
* See the reference manual for a detailed description.
* Careful : the BRP (Baud Rate Prescaler) is calculated by:
* 'brp = freq / (period * bitrate);'. freq is the frequency of the CAN
* device, period the time of transmission of a bit. The result is an uint32_t
* hence it's truncated, causing an approximation error. This error is non
* negligeable when period is high, bitrate is high and freq is low.
* device, period the time of transmission of a bit. The result is an uint32_t.
* Hence it's truncated, causing an approximation error. This error is non
* negligible when the period is high, the bitrate is high, and frequency is low.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] bitrate
* Wanted bitrate on the CAN bus.
* A wanted bitrate on the CAN bus.
*
* @param[in] propagationTimeSegment
* Value for the Propagation Time Segment.
* A value for the Propagation Time Segment.
*
* @param[in] phaseBufferSegment1
* Value for the Phase Buffer Segment 1.
* A value for the Phase Buffer Segment 1.
*
* @param[in] phaseBufferSegment2
* Value for the Phase Buffer Segment 2.
* A value for the Phase Buffer Segment 2.
*
* @param[in] synchronisationJumpWidth
* Value for the Synchronisation Jump Width.
* A value for the Synchronization Jump Width.
******************************************************************************/
void CAN_SetBitTiming(CAN_TypeDef *can,
uint32_t bitrate,
@ -270,7 +269,7 @@ void CAN_SetBitTiming(CAN_TypeDef *can,
{
uint32_t sum, brp, period, freq, brpHigh, brpLow;
/* Verification that the parameters are within range */
/* Verification that the parameters are in range. */
EFM_ASSERT((propagationTimeSegment <= 8) && (propagationTimeSegment > 0));
EFM_ASSERT((phaseBufferSegment1 <= 8) && (phaseBufferSegment1 > 0));
EFM_ASSERT((phaseBufferSegment2 <= 8) && (phaseBufferSegment2 > 0));
@ -280,29 +279,29 @@ void CAN_SetBitTiming(CAN_TypeDef *can,
&& (synchronisationJumpWidth > 0));
/* propagationTimeSegment is counted as part of phaseBufferSegment1 in the
BITTIMING register */
BITTIMING register. */
sum = phaseBufferSegment1 + propagationTimeSegment;
/* period is the total length of one CAN bit. 1 is the Sync_seg */
/* Period is the total length of one CAN bit. 1 is the Sync_seg. */
period = 1 + sum + phaseBufferSegment2;
freq = CAN_GetClockFrequency(can);
brp = freq / (period * bitrate);
EFM_ASSERT(brp != 0);
/* -1 because the hardware reads 'written value + 1' */
/* -1 because the hardware reads 'written value + 1'. */
brp = brp - 1;
/* brp is divided between two registers */
/* brp is divided between two registers. */
brpHigh = brp / 64;
brpLow = brp % 64;
/* Checking register limit */
/* Checking register limit. */
EFM_ASSERT(brpHigh <= 15);
bool enabled = CAN_IsEnabled(can);
/* Enable access to the bittiming registers */
/* Enable access to the bittiming registers. */
can->CTRL |= CAN_CTRL_CCE | CAN_CTRL_INIT;
can->BITTIMING = (brpLow << _CAN_BITTIMING_BRP_SHIFT)
@ -323,12 +322,12 @@ void CAN_SetBitTiming(CAN_TypeDef *can,
* Set the CAN operation mode.
*
* @details
* In Init mode, the CAN module is deactivated. Reset of the Messages in all
* the other modes to be sure that there are no leftover data and that they
* need to be configured before being of use.
* In initialization mode, the CAN module is deactivated. Reset the messages in all
* other modes to be sure that there is no leftover data that
* needs to be configured before use.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] mode
* Mode of operation : Init, Normal, Loopback, SilentLoopback, Silent, Basic.
@ -385,22 +384,22 @@ void CAN_SetMode(CAN_TypeDef *can, CAN_Mode_TypeDef mode)
/***************************************************************************//**
* @brief
* Set the Id and the filter for a specific Message Object.
* Set the ID and the filter for a specific Message Object.
*
* @details
* The Init bit have to be 0 to use this function.
* The initialization bit has to be 0 to use this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] useMask
* Boolean to choose whether or not to use the masks.
* A boolean to choose whether or not to use the masks.
*
* @param[in] message
* Message Object
* A Message Object.
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
@ -413,89 +412,90 @@ void CAN_SetIdAndFilter(CAN_TypeDef *can,
const CAN_MessageObject_TypeDef *message,
bool wait)
{
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in the correct range. */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
CAN_MIR_TypeDef * mir = &can->MIR[interface];
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
/* Send reading request and wait (3 to 6 CPU cycle). */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Reset MSGVAL */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
/* Reset MSGVAL. */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD_WRITE;
mir->ARB &= ~(0x1U << _CAN_MIR_ARB_MSGVAL_SHIFT);
CAN_SendRequest(can, interface, message->msgNum, true);
/* Set which registers to write to the RAM */
/* Set which registers to write to RAM. */
mir->CMDMASK |= CAN_MIR_CMDMASK_MASKACC;
/* Set UMASK bit */
/* Set UMASK bit. */
BUS_RegBitWrite(&mir->CTRL, _CAN_MIR_CTRL_UMASK_SHIFT, useMask);
/* Configure the id */
/* Configure the ID. */
if (message->extended) {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
| (message->id << _CAN_MIR_ARB_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (0x1UL << _CAN_MIR_ARB_MSGVAL_SHIFT)
| CAN_MIR_ARB_XTD_EXT;
} else {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | CAN_MIR_ARB_XTD_STD))
| (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
| (_CAN_MIR_ARB_STD_ID_SHIFT)
| (0x1UL << _CAN_MIR_ARB_MSGVAL_SHIFT);
}
if (message->extendedMask) {
mir->MASK = (message->mask << _CAN_MIR_MASK_MASK_SHIFT);
mir->MASK = (message->mask << _CAN_MIR_MASK_MASK_SHIFT)
& _CAN_MIR_MASK_MASK_MASK;
} else {
mir->MASK = (message->mask << _CAN_MIR_MASK_STD_SHIFT)
& _CAN_MIR_ARB_STD_ID_MASK;
}
/* Configure the masks */
/* Configure the masks. */
mir->MASK |= (message->extendedMask << _CAN_MIR_MASK_MXTD_SHIFT)
| (message->directionMask << _CAN_MIR_MASK_MDIR_SHIFT);
/* Send writing request */
/* Send a writing request. */
CAN_SendRequest(can, interface, message->msgNum, wait);
}
/***************************************************************************//**
* @brief
* Configure valid, tx/rx, remoteTransfer for a specific Message Object.
* Configure valid, TX/RX, remoteTransfer for a specific Message Object.
*
* @details
* The Init bit have to be 0 to use this function.
* The initialization bit has to be 0 to use this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of this Message Object, [1 - 32].
* A message number of this Message Object, [1 - 32].
*
* @param[in] valid
* true if Message Object is valid, false otherwise.
* True if the Message Object is valid, false otherwise.
*
* @param[in] tx
* true if Message Object is used for transmission, false if used for
* True if the Message Object is used for transmission, false if used for
* reception.
*
* @param[in] remoteTransfer
* true if Message Object is used for remote transmission, false otherwise.
* True if the Message Object is used for remote transmission, false otherwise.
*
* @param[in] endOfBuffer
* true if it is for a single Message Object or the end of a fifo buffer,
* false if the Message Object is part of a fifo buffer and not the last.
* True if it is for a single Message Object or the end of a FIFO buffer,
* false if the Message Object is part of a FIFO buffer and not the last.
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
@ -513,64 +513,64 @@ void CAN_ConfigureMessageObject(CAN_TypeDef *can,
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in correct range. */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
/* Send reading request and wait (3 to 6 CPU cycle). */
CAN_SendRequest(can, interface, msgNum, true);
/* Set which registers to write to the RAM */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
/* Set which registers to write to RAM. */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD_WRITE;
/* Configure valid message and direction */
/* Configure a valid message and direction. */
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_DIR_MASK | _CAN_MIR_ARB_MSGVAL_MASK))
| (valid << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (tx << _CAN_MIR_ARB_DIR_SHIFT);
/* Set eob bit, rx and tx interrupts */
/* Set EOB bit, RX, and TX interrupts. */
mir->CTRL = (endOfBuffer << _CAN_MIR_CTRL_EOB_SHIFT)
| _CAN_MIR_CTRL_TXIE_MASK
| _CAN_MIR_CTRL_RXIE_MASK
| (remoteTransfer << _CAN_MIR_CTRL_RMTEN_SHIFT);
/* Send writing request */
/* Send a writing request. */
CAN_SendRequest(can, interface, msgNum, wait);
}
/***************************************************************************//**
* @brief
* Send the data from the Message Object message.
* Send data from the Message Object message.
*
* @details
* If message is configured as tx and remoteTransfer = 0, calling this function
* If the message is configured as TX and remoteTransfer = 0, calling this function
* will send the data of this Message Object if its parameters are correct.
* If message is tx and remoteTransfer = 1, this function will set the data of
* message to the RAM and exit, the data will be automatically sent after
* If the message is TX and remoteTransfer = 1, this function will set the data of
* message to RAM and exit. Data will be automatically sent after
* reception of a remote frame.
* If message is rx and remoteTransfer = 1, this function will send a remote
* frame to the corresponding id.
* If message is rx and remoteTransfer = 0, the user shouldn't call this
* If the message is RX and remoteTransfer = 1, this function will send a remote
* frame to the corresponding ID.
* If the message is RX and remoteTransfer = 0, the user shouldn't call this
* function. It will also send a remote frame.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
* A Message Object.
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* RAM to exit. If false, exit immediately. The transfer can still be
* in progress.
******************************************************************************/
void CAN_SendMessage(CAN_TypeDef *can,
@ -580,85 +580,85 @@ void CAN_SendMessage(CAN_TypeDef *can,
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in correct range. */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
/* Make sure dlc is in the correct range */
/* Make sure dlc is in correct range. */
EFM_ASSERT(message->dlc <= _CAN_MIR_CTRL_DLC_MASK);
CAN_ReadyWait(can, interface);
/* Set LEC to unused value to be sure it is reset to 0 after sending */
/* Set LEC to an unused value to be sure it is reset to 0 after sending. */
BUS_RegMaskedWrite(&can->STATUS, _CAN_STATUS_LEC_MASK, 0x7);
/* Set which registers to read from the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
/* Send a reading request and wait (3 to 6 CPU cycle). */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Reset MSGVAL */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
/* Reset MSGVAL. */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD_WRITE;
mir->ARB &= ~(0x1UL << _CAN_MIR_ARB_MSGVAL_SHIFT);
CAN_SendRequest(can, interface, message->msgNum, true);
/* Set which registers to write to the RAM */
/* Set which registers to write to RAM. */
mir->CMDMASK |= CAN_MIR_CMDMASK_DATAA
| CAN_MIR_CMDMASK_DATAB;
/* If tx = 1 and remoteTransfer = 1, nothing is sent */
/* If TX = 1 and remoteTransfer = 1, nothing is sent. */
if ( ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0)
|| ((mir->ARB & _CAN_MIR_ARB_DIR_MASK) == _CAN_MIR_ARB_DIR_RX)) {
mir->CTRL |= CAN_MIR_CTRL_TXRQST;
/* DATAVALID is set only if it is not sending a remote message */
/* DATAVALID is set only if it is not sending a remote message. */
if ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0) {
mir->CTRL |= CAN_MIR_CTRL_DATAVALID;
}
}
/* Set the Data length Code */
/* Set the data length code. */
mir->CTRL = (mir->CTRL & ~_CAN_MIR_CTRL_DLC_MASK)
| message->dlc;
/* Configure the id */
/* Configure the ID. */
if (message->extended) {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
| (message->id << _CAN_MIR_ARB_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (0x1UL << _CAN_MIR_ARB_MSGVAL_SHIFT)
| CAN_MIR_ARB_XTD_EXT;
} else {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | _CAN_MIR_ARB_XTD_MASK))
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (0x1UL << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
| CAN_MIR_ARB_XTD_STD;
}
/* Set the data */
/* Set data. */
CAN_WriteData(can, interface, message);
/* Send writing request */
/* Send a writing request. */
CAN_SendRequest(can, interface, message->msgNum, wait);
}
/***************************************************************************//**
* @brief
* Read the data from a Message Object in the RAM and store it in message.
* Read data from a Message Object in RAM and store it in a message.
*
* @details
* Read all the information from the RAM on this Message Object : the data but
* Read the information from RAM on this Message Object : data but
* also the configuration of the other registers.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
* A Message Object.
******************************************************************************/
void CAN_ReadMessage(CAN_TypeDef *can,
uint8_t interface,
@ -668,12 +668,12 @@ void CAN_ReadMessage(CAN_TypeDef *can,
uint32_t buffer;
uint32_t i;
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in correct range. */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_MASKACC
| CAN_MIR_CMDMASK_ARBACC
@ -683,16 +683,23 @@ void CAN_ReadMessage(CAN_TypeDef *can,
| CAN_MIR_CMDMASK_DATAA
| CAN_MIR_CMDMASK_DATAB;
/* Send reading request and wait (3 to 6 cpu cycle) */
/* Send a reading request and wait (3 to 6 cpu cycle). */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Get dlc from the control register */
/* Get dlc from the control register. */
message->dlc = ((mir->CTRL & _CAN_MIR_CTRL_DLC_MASK) >> _CAN_MIR_CTRL_DLC_SHIFT);
/* Make sure dlc is in the correct range */
/* Make sure dlc is in correct range. */
EFM_ASSERT(message->dlc <= 8);
/* Copy the data from the MIR registers to the Message Object message */
/* Get id from the control register */
if (message->extended) {
message->id = (mir->ARB & _CAN_MIR_ARB_ID_MASK);
} else {
message->id = ((mir->ARB & _CAN_MIR_ARB_STD_ID_MASK) >> _CAN_MIR_ARB_STD_ID_SHIFT);
}
/* Copy data from the MIR registers to the Message Object message. */
buffer = mir->DATAL;
for (i = 0; i < SL_MIN(message->dlc, 4U); ++i) {
message->data[i] = buffer & 0xFF;
@ -709,25 +716,25 @@ void CAN_ReadMessage(CAN_TypeDef *can,
/***************************************************************************//**
* @brief
* Abort the sending of a message
* Abort sending a message.
*
* @details
* Set the TXRQST of the CTRL register to 0. Doesn't touch the data ot the
* others parameters. The user can reuse CAN_SendMessage() to send the object
* Set the TXRQST of the CTRL register to 0. Doesn't touch data or the
* other parameters. The user can call CAN_SendMessage() to send the object
* after using CAN_AbortSendMessage().
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of this Message Object, [1 - 32].
* A message number of this Message Object, [1 - 32].
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* the RAM to exit. If false, exit immediately. The transfer can still be
* in progress.
******************************************************************************/
void CAN_AbortSendMessage(CAN_TypeDef *can,
@ -735,29 +742,36 @@ void CAN_AbortSendMessage(CAN_TypeDef *can,
uint8_t msgNum,
bool wait)
{
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in correct range. */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
CAN_MIR_TypeDef * mir = &can->MIR[interface];
CAN_ReadyWait(can, interface);
/* Set which registers to write to the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_CONTROL;
/* Send a reading request and wait (3 to 6 cpu cycle). */
CAN_SendRequest(can, interface, msgNum, true);
/* Set which registers to write to RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD
| CAN_MIR_CMDMASK_ARBACC;
| CAN_MIR_CMDMASK_CONTROL;
/* Set TXRQST bit to 0 */
mir->ARB &= ~_CAN_MIR_CTRL_TXRQST_MASK;
/* Set TXRQST bit to 0. */
mir->CTRL &= ~_CAN_MIR_CTRL_TXRQST_MASK;
/* Send writing request */
/* Send a writing request. */
CAN_SendRequest(can, interface, msgNum, wait);
}
/***************************************************************************//**
* @brief
* Reset all the Message Objects and set their data to 0.
* Reset all Message Objects and set their data to 0.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
@ -767,7 +781,7 @@ void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface)
CAN_MIR_TypeDef * mir = &can->MIR[interface];
CAN_ReadyWait(can, interface);
/* Set which registers to read from the RAM */
/* Set which registers to read from RAM. */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD
| CAN_MIR_CMDMASK_MASKACC
| CAN_MIR_CMDMASK_ARBACC
@ -781,7 +795,7 @@ void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface)
mir->DATAL = 0x00000000;
mir->DATAH = 0x00000000;
/* Write each reset Message Object to the RAM */
/* Write each reset Message Object to RAM. */
for (int i = 1; i <= 32; ++i) {
CAN_SendRequest(can, interface, i, true);
}
@ -789,10 +803,10 @@ void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface)
/***************************************************************************//**
* @brief
* Set all the CAN registers to RESETVALUE. Leave the CAN Device disabled.
* Set all CAN registers to RESETVALUE. Leave the CAN device disabled.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
******************************************************************************/
void CAN_Reset(CAN_TypeDef *can)
{
@ -833,56 +847,61 @@ void CAN_Reset(CAN_TypeDef *can)
/***************************************************************************//**
* @brief
* Write the data from message to the MIRx registers
* Write data from a message to the MIRx registers.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
* A Message Object.
******************************************************************************/
void CAN_WriteData(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
uint32_t tmp;
uint8_t data[8] = { 0 };
size_t length = SL_MIN(8, message->dlc);
CAN_MIR_TypeDef * mir = &can->MIR[interface];
for (size_t i = 0; i < length; i++) {
data[i] = message->data[i];
}
CAN_ReadyWait(can, interface);
mir->DATAL = (data[3] << 24)
| (data[2] << 16)
| (data[1] << 8)
| (data[0] << 0);
mir->DATAH = (data[7] << 24)
| (data[6] << 16)
| (data[5] << 8)
| (data[4] << 0);
tmp = data[0];
tmp |= data[1] << 8;
tmp |= data[2] << 16;
tmp |= data[3] << 24;
mir->DATAL = tmp;
tmp = data[4];
tmp |= data[5] << 8;
tmp |= data[6] << 16;
tmp |= data[7] << 24;
mir->DATAH = tmp;
}
/***************************************************************************//**
* @brief
* Send request for writing or reading the RAM of Message Object msgNum.
* Send a request for writing or reading RAM of the Message Object msgNum.
*
* @param[in] can
* Pointer to CAN peripheral register block.
* A pointer to the CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] msgNum
* Message number of the Message Object, [1 - 32].
* A message number of the Message Object, [1 - 32].
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* the RAM to exit. If false, exit immediately. The transfer can still be
* in progress.
******************************************************************************/
void CAN_SendRequest(CAN_TypeDef *can,
@ -892,13 +911,13 @@ void CAN_SendRequest(CAN_TypeDef *can,
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
/* Make sure msgNum is in correct range. */
EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
/* Make sure the MIRx registers aren't busy */
/* Make sure the MIRx registers aren't busy. */
CAN_ReadyWait(can, interface);
/* Write msgNum to the CMDREQ register */
/* Write msgNum to the CMDREQ register. */
mir->CMDREQ = msgNum << _CAN_MIR_CMDREQ_MSGNUM_SHIFT;
if (wait) {

43
targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h
View File

@ -62,19 +62,19 @@ typedef enum {
PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7,
// Other mbed Pin Names
LED1 = PK4,
LED2 = PK5,
LED3 = PK6,
LED4 = PK7,
LED0 = PK4,
LED1 = PK5,
LED2 = PK6,
LED3 = PK7,
// External data bus Pin Names
D0 = PV7,
D1 = PV6,
D2 = PC4,
D3 = PK2,
D4 = PC3,
D5 = PJ0,
D6 = PN0,
D0 = PG3,
D1 = PG4,
D2 = PG5,
D3 = PG2,
D4 = PG6,
D5 = PA0,
D6 = PL5,
D7 = PL6,
D8 = PT0,
D9 = PP0,
@ -85,16 +85,15 @@ typedef enum {
D14 = PA5,
D15 = PA4,
// Analogue out pins
A0 = PF2,
A1 = PF3,
A2 = PF4,
A3 = PF5,
A4 = PF6,
A5 = PF7,
DAC0 = PG0,
DAC1 = PG1,
// Analogue out pins
A0 = PF7,
A1 = PF6,
A2 = PF5,
A3 = PF4,
A4 = PF3,
A5 = PF2,
// DAP_UART
USBTX = PJ1,
@ -103,10 +102,8 @@ typedef enum {
MBEDIF_RXD = USBRX,
// Switches
SW1 = PV0,
SW2 = PV1,
SW3 = PV2,
SW4 = PV3,
SW2 = PV3,
USER_BUTTON = PV3,
// I2C pins
SDA = D14,

13
targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h
View File

@ -60,10 +60,10 @@ typedef enum {
PY0 = 19 << 3, PY1, PY2, PY3, PY4,
// Other mbed Pin Names
LED1 = PE4,
LED2 = PE5,
LED3 = PE6,
LED4 = PE7,
LED0 = PE4,
LED1 = PE5,
LED2 = PE6,
LED3 = PE7,
// External data bus Pin Names
D0 = PJ0,
@ -101,11 +101,8 @@ typedef enum {
MBED_CONF_APP_UART0_RX = PE2,
// Switches
SW2 = PL4,
USER_BUTTON = PL4,
SW1 = PL4,
SW2 = PL5,
SW3 = PV0,
SW4 = PV1,
// I2C pins
SDA = PG2,

18
targets/targets.json
View File

@ -1,6 +1,7 @@
{
"Target": {
"core": null,
"trustzone": false,
"default_toolchain": "ARM",
"supported_toolchains": null,
"extra_labels": [],
@ -4227,8 +4228,8 @@
"device_name": "STM32L476VG",
"bootloader_supported": true
},
"RHOMBIO_L476DMW1K": {
"components_add": ["FLASHIAP"],
"RHOMBIO_L476DMW1K": {
"components_add": ["QSPIF", "FLASHIAP"],
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
@ -4256,6 +4257,7 @@
"SERIAL_FC",
"TRNG",
"FLASH",
"QSPI",
"MPU"
],
"release_versions": ["2", "5"],
@ -4296,6 +4298,7 @@
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F4", "STM32F411RE"],
"components_add": ["FLASHIAP"],
"config": {
"modem_is_on_board": {
"help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
@ -4309,17 +4312,18 @@
}
},
"overrides": { "lse_available": 0 },
"macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
"macros_add": ["HSE_VALUE=26000000"],
"post_binary_hook": {
"function": "MTSCode.combine_bins_mts_dragonfly",
"toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
},
"device_has_add": ["MPU"],
"device_has_add": ["MPU", "FLASH"],
"device_has_remove": [
"SERIAL_FC"
],
"release_versions": ["2", "5"],
"device_name": "STM32F411RE"
"device_name": "STM32F411RE",
"bootloader_supported": true
},
"MTS_DRAGONFLY_L471QG": {
"inherits": ["FAMILY_STM32"],
@ -6500,6 +6504,7 @@
"device_name": "EFM32GG11B820F2048GL192",
"device_has": [
"ANALOGIN",
"CAN",
"CRC",
"EMAC",
"I2C",
@ -7417,6 +7422,7 @@
"FLASH",
"MPU"
],
"components_add": ["FLASHIAP"],
"release_versions": ["2", "5"],
"device_name": "M453VG6AE",
"bootloader_supported": true,
@ -8033,6 +8039,7 @@
"MBED_TZ_DEFAULT_ACCESS=1",
"LPTICKER_DELAY_TICKS=3"
],
"trustzone": true,
"is_disk_virtual": true,
"supported_toolchains": ["ARMC6"],
"config": {
@ -8083,6 +8090,7 @@
"FLASH",
"MPU"
],
"components_add": ["FLASHIAP"],
"detect_code": ["1305"],
"release_versions": ["5"],
"device_name": "M2351KIAAEES",

5
tools/build_api.py
View File

@ -604,10 +604,7 @@ def build_project(src_paths, build_path, target, toolchain_name,
if into_dir:
copy_when_different(res[0], into_dir)
if not extra_artifacts:
if (
CORE_ARCH[toolchain.target.core] == 8 and
not toolchain.target.core.endswith("NS")
):
if toolchain.target.is_TrustZone_secure_target:
cmse_lib = join(dirname(res[0]), "cmse_lib.o")
copy_when_different(cmse_lib, into_dir)
else:

29
tools/targets/__init__.py
View File

@ -379,6 +379,32 @@ class Target(namedtuple(
labels = (names + CORE_LABELS[self.core] + self.extra_labels)
return labels
@property
def core_without_NS(self):
if self.core.endswith('-NS'):
return self.core[:-3]
else:
return self.core
# Mechanism for specifying TrustZone is subject to change - see
# discussion on https://github.com/ARMmbed/mbed-os/issues/9460
# In the interim, we follow heuristics that support existing
# documentation for ARMv8-M TF-M integration (check the "TFM" label),
# plus an extra "trustzone" flag set by M2351, and looking at the "-NS"
# suffix. This now permits non-TrustZone ARMv8 builds if
# having trustzone = false (default), no TFM flag, and no -NS suffix.
@property
def is_TrustZone_secure_target(self):
return (getattr(self, 'trustzone', False) or 'TFM' in self.labels) and not self.core.endswith('-NS')
@property
def is_TrustZone_non_secure_target(self):
return self.core.endswith('-NS')
@property
def is_TrustZone_target(self):
return self.is_TrustZone_secure_target or self.is_TrustZone_non_secure_target
@property
def is_PSA_secure_target(self):
return 'SPE_Target' in self.labels
@ -408,6 +434,9 @@ class Target(namedtuple(
hook_data = self.post_binary_hook
except AttributeError:
return None
# If hook is null, also return
if hook_data is None:
return None
# A hook was found. The hook's name is in the format
# "classname.functionname"
temp = hook_data["function"].split(".")

32
tools/toolchains/arm.py
View File

@ -25,7 +25,6 @@ from tempfile import mkstemp
from shutil import rmtree
from distutils.version import LooseVersion
from tools.targets import CORE_ARCH
from tools.toolchains.mbed_toolchain import mbedToolchain, TOOLCHAIN_PATHS
from tools.utils import mkdir, NotSupportedException, run_cmd
from tools.resources import FileRef
@ -521,25 +520,25 @@ class ARMC6(ARM_STD):
if "--library_type=microlib" not in self.flags['asm']:
self.flags['asm'].append("--library_type=microlib")
core = target.core
if CORE_ARCH[target.core] == 8:
if ((not target.core.endswith("-NS")) and
kwargs.get('build_dir', False)):
# Create Secure library
if target.is_TrustZone_secure_target:
if kwargs.get('build_dir', False):
# Output secure import library
build_dir = kwargs['build_dir']
secure_file = join(build_dir, "cmse_lib.o")
self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file]
# Add linking time preprocessor macro DOMAIN_NS
if target.core.endswith("-NS"):
define_string = self.make_ld_define("DOMAIN_NS", "0x1")
self.flags["ld"].append(define_string)
core = target.core[:-3]
else:
# Add secure build flag
self.flags['cxx'].append("-mcmse")
self.flags['c'].append("-mcmse")
# Enable compiler security extensions
self.flags['cxx'].append("-mcmse")
self.flags['c'].append("-mcmse")
if target.is_TrustZone_non_secure_target:
# Add linking time preprocessor macro DOMAIN_NS
# (DOMAIN_NS is passed to compiler and assembler via CORTEX_SYMBOLS
# in mbedToolchain.get_symbols)
define_string = self.make_ld_define("DOMAIN_NS", "0x1")
self.flags["ld"].append(define_string)
core = target.core_without_NS
cpu = {
"Cortex-M0+": "cortex-m0plus",
"Cortex-M4F": "cortex-m4",
@ -681,6 +680,9 @@ class ARMC6(ARM_STD):
# Build main assemble command
cmd = self.asm + ["-o", object, tempfile]
if self.is_mbed_studio_armc6:
# NOTE: the --ide=mbed argument is only for use with Mbed OS
cmd.insert(1, "--ide=mbed")
# Return command array, don't execute
return [cmd_pre, cmd]

28
tools/toolchains/gcc.py
View File

@ -20,7 +20,6 @@ from os import getenv
from distutils.spawn import find_executable
from distutils.version import LooseVersion
from tools.targets import CORE_ARCH
from tools.toolchains.mbed_toolchain import mbedToolchain, TOOLCHAIN_PATHS
from tools.utils import run_cmd
@ -59,20 +58,23 @@ class GCC(mbedToolchain):
self.flags["common"].append("-DMBED_RTOS_SINGLE_THREAD")
self.flags["ld"].append("--specs=nano.specs")
core = target.core
self.cpu = []
if CORE_ARCH[target.core] == 8:
# Add linking time preprocessor macro DOMAIN_NS
if target.core.endswith("-NS"):
self.flags["ld"].append("-DDOMAIN_NS=1")
core = target.core[:-3]
else:
self.cpu.append("-mcmse")
self.flags["ld"].extend([
"-Wl,--cmse-implib",
"-Wl,--out-implib=%s" % join(build_dir, "cmse_lib.o")
])
if target.is_TrustZone_secure_target:
# Enable compiler security extensions
self.cpu.append("-mcmse")
# Output secure import library
self.flags["ld"].extend([
"-Wl,--cmse-implib",
"-Wl,--out-implib=%s" % join(build_dir, "cmse_lib.o")
])
if target.is_TrustZone_non_secure_target:
# Add linking time preprocessor macro DOMAIN_NS
# (DOMAIN_NS is passed to compiler and assembler via CORTEX_SYMBOLS
# in mbedToolchain.get_symbols)
self.flags["ld"].append("-DDOMAIN_NS=1")
core = target.core_without_NS
cpu = {
"Cortex-M0+": "cortex-m0plus",
"Cortex-M4F": "cortex-m4",

30
tools/toolchains/iar.py
View File

@ -19,7 +19,6 @@ from os import remove
from os.path import join, splitext, exists
from distutils.version import LooseVersion
from tools.targets import CORE_ARCH
from tools.toolchains.mbed_toolchain import mbedToolchain, TOOLCHAIN_PATHS
from tools.utils import run_cmd
@ -54,20 +53,23 @@ class IAR(mbedToolchain):
build_dir=build_dir,
build_profile=build_profile
)
core = target.core
if CORE_ARCH[target.core] == 8:
# Add linking time preprocessor macro DOMAIN_NS
if target.core.endswith("-NS"):
define_string = self.make_ld_define("DOMAIN_NS", "0x1")
self.flags["ld"].append(define_string)
core = target.core[:-3]
else:
# Create Secure library
self.flags["asm"] += ["--cmse"]
self.flags["common"] += ["--cmse"]
secure_file = join(build_dir, "cmse_lib.o")
self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file]
if target.is_TrustZone_secure_target:
# Enable compiler security extensions
self.flags["asm"] += ["--cmse"]
self.flags["common"] += ["--cmse"]
# Output secure import library
secure_file = join(build_dir, "cmse_lib.o")
self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file]
if target.is_TrustZone_non_secure_target:
# Add linking time preprocessor macro DOMAIN_NS
# (DOMAIN_NS is passed to compiler and assembler via CORTEX_SYMBOLS
# in mbedToolchain.get_symbols)
define_string = self.make_ld_define("DOMAIN_NS", "0x1")
self.flags["ld"].append(define_string)
core = target.core_without_NS
cpu = {
"Cortex-M7F": "Cortex-M7.fp.sp",
"Cortex-M7FD": "Cortex-M7.fp.dp",

8
tools/toolchains/mbed_toolchain.py
View File

@ -255,6 +255,7 @@ class mbedToolchain:
"COMPONENT_" + data + "=1"
for data in self.target.components
]
# Add extra symbols passed via 'macros' parameter
self.cxx_symbols += self.macros
@ -946,6 +947,13 @@ class mbedToolchain:
self.ld.append(define_string)
self.flags["ld"].append(define_string)
if hasattr(self.target, 'post_binary_hook'):
if self.target.post_binary_hook is None:
define_string = self.make_ld_define(
"DISABLE_POST_BINARY_HOOK", 1)
self.ld.append(define_string)
self.flags["ld"].append(define_string)
# Set the configuration data
def set_config_data(self, config_data):
self.config_data = config_data