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Add peripheral interface files 

Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>
pull/15263/head
Sadik.Ozer 2022-02-28 15:56:54 +03:00
parent f40887acdd
commit 704bfc786a
24 changed files with 1780 additions and 1108 deletions
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185
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h Normal file
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@ -0,0 +1,185 @@
/**
* @file crc.h
* @brief cyclic redundancy check driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _CRC_H_
#define _CRC_H_
/***** Includes *****/
#include "crc_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup crc CRC
* @ingroup periphlibs
* @{
*/
/***** CRC Definitions *****/
/**
* @brief Structure used to set up CRC request
*
*/
typedef struct _mxc_crc_req_t {
uint32_t* dataBuffer; ///< Pointer to the data
uint32_t dataLen; ///< Length of the data
uint32_t resultCRC; ///< Calculated CRC value
} mxc_crc_req_t;
/**
* @brief CRC data bit order
*
*/
typedef enum {
CRC_LSB_FIRST,
CRC_MSB_FIRST
} mxc_crc_bitorder_t;
/***** Function Prototypes *****/
/* ************************************************************************* */
/* Global Control/Configuration functions */
/* ************************************************************************* */
/**
* @brief Enable portions of the CRC
*
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_CRC_Init (void);
/**
* @brief Disable and reset portions of the CRC
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_CRC_Shutdown (void);
/**
* @brief This function should be called from the CRC ISR Handler
* when using Async functions
* @param ch DMA channel
* @param error error
*/
void MXC_CRC_Handler (int ch, int error);
/**
* @brief Set the bit-order of CRC calculation
*
* @param bitOrder The direction to perform CRC calculation in
*/
void MXC_CRC_SetDirection (mxc_crc_bitorder_t bitOrder);
/**
* @brief Set the bit-order of CRC calculation
*
* @return The direction of calculation, 1 for MSB first, 0 for LSB first
*/
mxc_crc_bitorder_t MXC_CRC_GetDirection (void);
/**
* @brief Byte Swap CRC Data Input
*
* @param bitOrder The direction to perform CRC calculation in
*/
void MXC_CRC_SwapDataIn (mxc_crc_bitorder_t bitOrder);
/**
* @brief Byte Swap CRC Data output
*
* @param bitOrder The direction to perform CRC calculation in
*/
void MXC_CRC_SwapDataOut (mxc_crc_bitorder_t bitOrder);
/**
* @brief Set the Polynomial for CRC calculation
*
* @param poly The polynomial to use for CRC calculation
*/
void MXC_CRC_SetPoly (uint32_t poly);
/**
* @brief Get the polynomial for CRC calculation
*
* @return The polynomial used in calculation
*/
uint32_t MXC_CRC_GetPoly (void);
/**
* @brief Get the result of a CRC calculation
*
* @return The calculated CRC value
*/
uint32_t MXC_CRC_GetResult (void);
/*******************************/
/* High Level Functions */
/*******************************/
/**
* @brief Perform a CRC computation
* @note The result of the CRC calculation will be placed in the
* mxc_crc_req_t structure
*
* @param req Structure containing the data for calculation
*
* @return see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_CRC_Compute (mxc_crc_req_t* req);
/**
* @brief Perform a CRC computation using DMA
* @note The result of the CRC calculation will be placed in the
* mxc_crc_req_t structure. The user must call
* MXC_DMA_Handler() in the ISR
*
* @param req Structure containing the data for calculation
*
* @return see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_CRC_ComputeAsync (mxc_crc_req_t* req);
#ifdef __cplusplus
}
#endif
/**@} end of group crc */
#endif /* _CRC_H_ */

87
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h
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@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -42,7 +42,6 @@
/* **** Includes **** */
#include <stdbool.h>
#include "mxc_device.h"
#include "mxc_errors.h"
#include "dma_regs.h"
#ifdef __cplusplus
@ -57,53 +56,65 @@ extern "C" {
/* **** Definitions **** */
/**
* @brief Enumeration for the DMA Channel's priority level.
*
*/
typedef enum {
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */
MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority */
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority */
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority */
MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority */
} mxc_dma_priority_t;
/** @brief DMA request select */
typedef enum {
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection
MXC_DMA_REQUEST_UART2RX = MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection
MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection
MXC_DMA_REQUEST_UART3RX = MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection
MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection
MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection
MXC_DMA_REQUEST_UART2TX = MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection
MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection
MXC_DMA_REQUEST_UART3TX = MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection
} mxc_dma_reqsel_t;
/** @brief Enumeration for the DMA prescaler */
typedef enum {
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216
} mxc_dma_prescale_t;
/** @brief Enumeration for the DMA timeout value */
typedef enum {
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks
} mxc_dma_timeout_t;
/** @brief DMA transfer data width */
@ -111,9 +122,9 @@ typedef enum {
/* Using the '_V_' define instead of the '_S_' since these same values will be used to
specify the DSTWD also. The API functions will shift the value the correct amount
prior to writing the cfg register. */
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words
} mxc_dma_width_t;
/**
@ -246,7 +257,7 @@ int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst);
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst);
/**
* @brief Set channel reload source, destination, and count for the transfer
@ -266,7 +277,7 @@ int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload);
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload);
/**
* @brief Set channel interrupt callback
@ -302,7 +313,7 @@ int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
* @param ctz Enable channel count to zero interrupt.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz);
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
/**
* @brief Enable channel interrupt

3
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h
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@ -5,7 +5,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -43,7 +43,6 @@
/* **** Includes **** */
#include "flc_regs.h"
#include "mxc_sys.h"
#include "mxc_errors.h"
#ifdef __cplusplus
extern "C" {

63
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h
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@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -63,6 +63,9 @@ extern "C" {
* @{
*/
#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define
#define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) ///< Port 1 Define
#define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) ///< Port 2 Define
#define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) ///< Port 3 Define
/**@} end of gpio_port group*/
/**
* @defgroup gpio_pin Pin Definitions
@ -82,7 +85,25 @@ extern "C" {
#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define
#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define
#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define
#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define
#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define
#define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) ///< Pin 14 Define
#define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) ///< Pin 15 Define
#define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) ///< Pin 16 Define
#define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) ///< Pin 17 Define
#define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) ///< Pin 18 Define
#define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) ///< Pin 19 Define
#define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) ///< Pin 20 Define
#define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) ///< Pin 21 Define
#define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) ///< Pin 22 Define
#define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) ///< Pin 23 Define
#define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) ///< Pin 24 Define
#define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) ///< Pin 25 Define
#define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) ///< Pin 26 Define
#define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) ///< Pin 27 Define
#define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) ///< Pin 28 Define
#define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) ///< Pin 29 Define
#define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) ///< Pin 30 Define
#define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) ///< Pin 31 Define
/**@} end of gpio_pin group */
/**@} end of gpio_port_pin group */
@ -187,30 +208,30 @@ int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg);
/**
* @brief Gets the pin(s) input state.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to read
* @param port Pointer to GPIO port.
* @param mask Mask of the pin to read
* @return The requested pin state.
*/
uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Sets the pin(s) to a high level output.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to set
* @param port Pointer to GPIO port.
* @param mask Mask of the pin to set
*/
void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Clears the pin(s) to a low level output.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to clear
* @param port Pointer to GPIO port.
* @param mask Mask of the pin to clear
*/
void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Gets the pin(s) output state.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to read the output state of
* @param port Pointer to GPIO port.
* @param mask Mask of the pin to read the output state of
* @return The state of the requested pin.
*
*/
@ -218,8 +239,8 @@ uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Write the pin(s) to a desired output level.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to set output level of
* @param port Pointer to GPIO port.
* @param mask Mask of the pin to set output level of
* @param val Desired output level of the pin(s). This will be masked
* with the configuration mask.
*/
@ -227,8 +248,8 @@ void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val);
/**
* @brief Toggles the the pin(s) output level.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to toggle
* @param port Pointer to GPIO port.
* @param mask Mask of the pin to toggle the output
*/
void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask);
@ -242,23 +263,23 @@ int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
/**
* @brief Enables the specified GPIO interrupt
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to enable interrupts for
* @param port Pointer to GPIO port.
* @param mask mask of the pin to enable interrupt
*
*/
void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Disables the specified GPIO interrupt.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to disable interrupts for
* @param port Pointer to GPIO port.
* @param mask mask of the pin to disable interrupt
*/
void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Gets the interrupt(s) status on a GPIO port
*
* @param port Pointer to the port requested
* @param port Pointer to GPIO port.
*
* @return The requested interrupt status.
*/
@ -267,7 +288,7 @@ uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port);
/**
* @brief Gets the interrupt(s) status on a GPIO port
*
* @param port Pointer to the port requested
* @param port Pointer to GPIO port.
* @param flags The flags to clear
*/
void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
@ -285,7 +306,7 @@ void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
* interrupt, the callback function will be called.
*
* @param port Number of the port that generated the interrupt service routine.
* @param port number of the port that generated the interrupt service routine.
*
*/
void MXC_GPIO_Handler (unsigned int port);

219
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -42,7 +42,7 @@
/* **** Includes **** */
#include "mxc_sys.h"
#include "dma.h"
#include "spimss_regs.h"
#include "i2s_regs.h"
#ifdef __cplusplus
extern "C" {
@ -56,133 +56,188 @@ extern "C" {
/* **** Definitions **** */
/** @brief I2S stereo mode select */
typedef enum {
I2S_MAP_A = 0,
I2S_MAP_B = 1,
} mxc_i2s_sys_map_t;
MXC_I2S_MONO_LEFT_CH = 2,
MXC_I2S_MONO_RIGHT_CH = 3
} mxc_i2s_stereo_t;
/** @brief I2S polarity configuration */
typedef enum {
LEFT_JUSTIFIED= 0,
RIGHT_JUSTIFIED = 1,
MXC_I2S_POL_NORMAL,
MXC_I2S_POL_INVERSE
} mxc_i2s_polarity_t;
/** @brief I2S transaction bit order */
typedef enum {
MXC_I2S_MSB_FIRST,
MXC_I2S_LSB_FIRST
} mxc_i2s_bitorder_t;
/** @brief I2S transaction justify order */
typedef enum {
MXC_I2S_MSB_JUSTIFY,
MXC_I2S_LSB_JUSTIFY
} mxc_i2s_justify_t;
/** @brief I2S transaction word size */
typedef enum {
STEREO_MODE = 0,
MONO_MODE = 1,
} mxc_i2s_audio_mode_t;
MXC_I2S_DATASIZE_BYTE,
MXC_I2S_DATASIZE_HALFWORD,
MXC_I2S_DATASIZE_WORD
} mxc_i2s_wsize_t;
/** @brief I2S audio directions */
/** @brief I2S transaction sample size */
typedef enum {
AUDIO_OUT = 1,
AUDIO_IN = 2,
} mxc_i2s_direction_t;
MXC_I2S_SAMPLESIZE_EIGHT,
MXC_I2S_SAMPLESIZE_SIXTEEN,
MXC_I2S_SAMPLESIZE_TWENTY,
MXC_I2S_SAMPLESIZE_TWENTYFOUR,
MXC_I2S_SAMPLESIZE_THIRTYTWO,
} mxc_i2s_samplesize_t;
/** @brief I2S channel mode */
typedef enum {
MXC_I2S_INTERNAL_SCK_WS_0,
MXC_I2S_INTERNAL_SCK_WS_1,
MXC_I2S_EXTERNAL_SCK_INTERNAL_WS,
MXC_I2S_EXTERNAL_SCK_EXTERNAL_WS,
} mxc_i2s_ch_mode_t;
/** @brief I2S Configuration Struct */
typedef struct {
mxc_i2s_sys_map_t map;
mxc_i2s_ch_mode_t channelMode;
mxc_i2s_stereo_t stereoMode;
mxc_i2s_wsize_t wordSize;
mxc_i2s_justify_t justify;
mxc_i2s_audio_mode_t audio_mode;
mxc_i2s_direction_t audio_direction;
uint16_t sample_rate;
unsigned int start_immediately;
unsigned int dma_reload_en;
void *src_addr;
void *dst_addr;
mxc_i2s_bitorder_t bitOrder;
mxc_i2s_polarity_t wsPolarity;
mxc_i2s_samplesize_t sampleSize;
uint16_t clkdiv;
void *rawData;
void *txData;
void *rxData;
uint32_t length;
} mxc_i2s_config_t;
} mxc_i2s_req_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize I2S resources
*
* @param config see \ref mxc_i2s_config_t I2S Config Struct
* @param dma_ctz_cb Function pointer to Count-to-Zero callback function.
* @param req see \ref mxc_i2s_req_t I2S Request Struct
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int));
int MXC_I2S_Init(mxc_i2s_req_t *req);
/**
* @brief Release I2S
* @details De-configures the I2S protocol and stops DMA request
* @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
* @brief Release I2S, clear configuration and flush FIFOs
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_Shutdown(void);
/**
* @brief Mute I2S Output
* @details Sets I2S data to zero, continues sending clock and accessing DMA
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Mute(void);
* @brief Configure data to be transmitted based on word and sample size
*
* @param req see \ref mxc_i2s_req_t I2S Request Struct
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_ConfigData(mxc_i2s_req_t *req);
/**
* @brief Unmute I2S Output
* @details Restores I2S data
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Unmute(void);
* @brief Enable TX channel
*/
void MXC_I2S_TXEnable(void);
/**
* @brief Pause I2S Output
* @details Similar to mute, but stops FIFO and DMA access, clocks continue
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Pause(void);
* @brief Disable TX channel
*/
void MXC_I2S_TXDisable(void);
/**
* @brief Unpause I2S Output
* @details Similar to mute, but restarts FIFO and DMA access
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Unpause(void);
* @brief Enable RX channel
*/
void MXC_I2S_RXEnable(void);
/**
* @brief Stops I2S Output
* @details Similar to pause, but also halts clock
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Stop(void);
* @brief Disable RX channel
*/
void MXC_I2S_RXDisable(void);
/**
* @brief Starts I2S Output
* @details Starts I2S Output, automatically called by configure if requested
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Start(void);
* @brief Set threshold for RX FIFO
*
* @param threshold RX FIFO interrupt threshold.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_SetRXThreshold(uint8_t threshold);
/**
* @brief Clears DMA Interrupt Flags
* @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
* @return \c #E_NO_ERROR
* @brief Set I2S Frequency, automatically called by I2S_Init
*
* @param mode Channel mode to select clock
* @param clkdiv clock divider to set baudrate
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_DMA_ClearFlags(void);
int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv);
/**
* @brief Set DMA Addr (Source or Dest) and bytes to transfer
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details Sets the address to read/write data in memory and the length of
* the transfer. The unused addr parameter is ignored.
* @return \c #E_NO_ERROR
* @brief Flush I2S FIFO
*
*/
int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
void MXC_I2S_Flush(void);
/**
* @brief Sets the DMA reload address and count
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details If DMA reload is enabled, when the DMA has transfered $count bytes
* (a CTZ event occurs) the src, dst, and count registers will be
* set to these. The DMA reload flag clears after a reload occurs.
* @return \c #E_NO_ERROR
*/
int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
/**@} end of group i2s */
* @brief Enable Interrupts
*
* @param flags Interrupt mask
*/
void MXC_I2S_EnableInt(uint32_t flags);
/**
* @brief Disable Interrupt
*
* @param flags Interrupt mask
*/
void MXC_I2S_DisableInt(uint32_t flags);
/**
* @brief Get the set interrupt flags
*
* @return int return the mask of the set interrupt flags
*/
int MXC_I2S_GetFlags(void);
/**
* @brief Clears Interrupt Flags
*
* @param flags Interrupt flags to be cleared
*/
void MXC_I2S_ClearFlags(uint32_t flags);
/**
* @brief Configure TX DMA transaction
*
* @param src_addr source address of data
* @param len length od the data to be transmitted
*/
void MXC_I2S_TXDMAConfig(void *src_addr, int len);
/**
* @brief Configure RX DMA transaction
*
* @param dest_addr destination address
* @param len length of the data to be received
*/
void MXC_I2S_RXDMAConfig(void *dest_addr, int len);
/**
* @brief Set the callback function pointer for I2S DMA transactions
*
* @param callback Function pointer to the DMA callback function
*/
void MXC_I2S_RegisterDMACallback(void(*callback)(int, int));
#ifdef __cplusplus
}

2
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

579
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h
View File

@ -1,11 +1,10 @@
/**
* @file lp.h
* @brief Low power function prototypes and data types.
* @brief Low Power(LP) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,17 +34,19 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
* $Revision: 38105 $
*
*************************************************************************** */
// Define to prevent redundant inclusion
/* Define to prevent redundant inclusion */
#ifndef _LP_H_
#define _LP_H_
/***** Includes *****/
/* **** Includes **** */
#include <stdint.h>
#include "pwrseq_regs.h"
#include "mcr_regs.h"
#include "gcr_regs.h"
#include "gpio.h"
#include "tmr.h"
#ifdef __cplusplus
extern "C" {
@ -57,286 +58,480 @@ extern "C" {
* @{
*/
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
/**
* @brief Enumeration type for voltage selection
*
*/
typedef enum {
MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */
MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */
MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */
MXC_LP_V0_9 = 0,
MXC_LP_V1_0,
MXC_LP_V1_1
} mxc_lp_ovr_t;
/**
* @brief Clears the low power wakeup flags
* @brief Enumeration type for PM Mode
*
*/
void MXC_LP_ClearWakeStatus(void);
typedef enum {
MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD,
MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD,
MXC_LP_XRFO = MXC_F_GCR_PM_ERFO_PD
} mxc_lp_cfg_ds_pd_t;
/**
* @brief Enables power to RAM addresses 0x20010000-0x20017FFF.
* @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur.
*/
void MXC_LP_EnableSRAM3(void);
/**
* @brief Enables power to RAM addresses 0x20008000-0x2000FFFF.
*/
void MXC_LP_EnableSRAM2(void);
/**
* @brief Enables power to RAM addresses 0x20004000-0x20007FFF.
*/
void MXC_LP_EnableSRAM1(void);
/**
* @brief Enables power to RAM addresses 0x20000000-0x20003FFF.
*/
void MXC_LP_EnableSRAM0(void);
/**
* @brief Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM3(void);
/**
* @brief Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM2(void);
/**
* @brief Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM1(void);
/**
* @brief Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM0(void);
/**
* @brief Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM0LightSleep(void);
/**
* @brief Places the instruction cache in active mode.
*/
void MXC_LP_DisableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM0LightSleep(void);
/**
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
*/
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
/**
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
*/
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);
/**
* @brief Enables the RTC alarm to wake up the device from any low power mode.
*/
void MXC_LP_EnableRTCAlarmWakeup(void);
/**
* @brief Disables the RTC alarm from waking up the device.
*/
void MXC_LP_DisableRTCAlarmWakeup(void);
/**
* @brief Places the device into SLEEP mode. This function returns once any interrupt occurs.
* @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void MXC_LP_EnterSleepMode(void);
void MXC_LP_EnterSleepMode (void);
/**
* @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur.
* @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void MXC_LP_EnterDeepSleepMode(void);
*/
void MXC_LP_EnterDeepSleepMode (void);
/**
* @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur.
* @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void MXC_LP_EnterBackupMode(void);
void MXC_LP_EnterBackupMode (void);
/**
* @brief Places the device into Storage mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur.
*/
void MXC_LP_EnterStorageMode (void);
/**
* @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur.
*/
void MXC_LP_EnterShutDownMode(void);
void MXC_LP_EnterShutDownMode (void);
/**
* @brief Set operating voltage and change the clock to match the new voltage.
* @param system reset configuration struct
* @brief Set ovr bits to set the voltage the micro will run at.
*
* @param[in] ovr The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t
*/
int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr);
void MXC_LP_SetOVR (mxc_lp_ovr_t ovr);
/**
* @brief Enables Data Retention to RAM addresses 0x20000000-0x20003FFF.
* @brief Enable retention regulator
*/
void MXC_LP_EnableSRamRet0(void);
void MXC_LP_RetentionRegEnable (void);
/**
* @brief Disables Data Retention to RAM addresses 0x20000000-0x20003FFF.
* @brief Disable retention regulator
*/
void MXC_LP_DisableSRamRet0(void);
void MXC_LP_RetentionRegDisable (void);
/**
* @brief Enables Data Retention to RAM addresses 0x20004000-0x20007FFF.
* @brief Is the retention regulator enabled
*
* @return 1 = enabled 0 = disabled
*/
void MXC_LP_EnableSRamRet1(void);
int MXC_LP_RetentionRegIsEnabled (void);
/**
* @brief Disables Data Retention to RAM addresses 0x20004000-0x20007FFF.
* @brief Turn bandgap on
*/
void MXC_LP_DisableSRamRet1(void);
void MXC_LP_BandgapOn (void);
/**
* @brief Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
* @brief Turn bandgap off
*/
void MXC_LP_EnableSRamRet2(void);
void MXC_LP_BandgapOff (void);
/**
* @brief Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
* @brief Is the bandgap on or off
*
* @return 1 = bandgap on , 0 = bandgap off
*/
void MXC_LP_DisableSRamRet2(void);
int MXC_LP_BandgapIsOn (void);
/**
* @brief Enables Data Retention to RAM addresses 0x20010000-0x20017FFF.
* @brief Enable Power on Reset VDD Core Monitor
*/
void MXC_LP_EnableSRamRet3(void);
void MXC_LP_PORVCOREoreMonitorEnable (void);
/**
* @brief Disables Data Retention to RAM addresses 0x20010000-0x20017FFF.
* @brief Disable Power on Reset VDD Core Monitor
*/
void MXC_LP_DisableSRamRet3(void);
void MXC_LP_PORVCOREoreMonitorDisable (void);
/**
* @brief Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time.
* @brief Is Power on Reset VDD Core Monitor enabled
*
* @return 1 = enabled , 0 = disabled
*/
void MXC_LP_EnableBlockDetect(void);
int MXC_LP_PORVCOREoreMonitorIsEnabled (void);
/**
* @brief Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time
* @brief Enable LDO
*/
void MXC_LP_DisableBlockDetect(void);
void MXC_LP_LDOEnable (void);
/**
* @brief RAM Retention Regulator Enable for BACKUP Mode
* @brief Disable LDO
*/
void MXC_LP_EnableRamRetReg(void);
void MXC_LP_LDODisable (void);
/**
* @brief RAM Retention Regulator Disabels for BACKUP Mode
* @brief Is LDO enabled
*
* @return 1 = enabled , 0 = disabled
*/
void MXC_LP_DisableRamRetReg(void);
int MXC_LP_LDOIsEnabled (void);
/**
* @brief Enables Fast wake up from deepsleep
* @brief Enable Fast wakeup
*/
void MXC_LP_EnableFastWk(void);
void MXC_LP_FastWakeupEnable (void);
/**
* @brief Disables Fast wake up from deepsleep
* @brief Disable Fast wakeup
*/
void MXC_LP_DisableFastWk(void);
void MXC_LP_FastWakeupDisable (void);
/**
* @brief Turns on band gap during deepsleep and backup mode.
* @brief Is Fast wake up is Enabled
*
* @return 1 = enabled , 0 = disabled
*/
void MXC_LP_EnableBandGap(void);
int MXC_LP_FastWakeupIsEnabled (void);
/**
* @brief Turns off band gap during deepsleep and backup mode.
* @brief clear all wake up status
*/
void MXC_LP_DisableBandGap(void);
void MXC_LP_ClearWakeStatus (void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored. \ref mxc_gpio_cfg_t
*/
void MXC_LP_EnableVCorePORSignal(void);
void MXC_LP_EnableGPIOWakeup (mxc_gpio_cfg_t *wu_pins);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored. \ref mxc_gpio_cfg_t
*/
void MXC_LP_DisableVCorePORSignal(void);
void MXC_LP_DisableGPIOWakeup (mxc_gpio_cfg_t *wu_pins);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
* @brief Enables the RTC alarm to wake up the device from any low power mode.
*/
void MXC_LP_EnableLDO(void);
void MXC_LP_EnableRTCAlarmWakeup (void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
* @brief Disables the RTC alarm from waking up the device.
*/
void MXC_LP_DisableLDO(void);
void MXC_LP_DisableRTCAlarmWakeup (void);
/**
* @brief Enables V CORE Supply Voltage Monitor
* @brief Enables Timer to wakeup from any low power mode.
*
* @param tmr Pointer to timer module.
*/
void MXC_LP_EnableVCoreSVM(void);
void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr);
/**
* @brief Disables V CORE Supply Voltage Monitor
* @brief Disables Timer from waking up device.
*
* @param tmr Pointer to timer module.
*/
void MXC_LP_DisableVCoreSVM(void);
void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t* tmr);
/**
* @brief Enables VDDIO Power-On-Reset Monitor
* @brief Enables the USB to wake up the device from any low power mode.
*/
void MXC_LP_EnableVDDIOPorMonitor(void);
void MXC_LP_EnableUSBWakeup (void);
/**
* @brief Disables VDDIO Power-On-Reset Monitor
* @brief Disables the USB from waking up the device.
*/
void MXC_LP_DisableVDDIOPorMonitor(void);
void MXC_LP_DisableUSBWakeup (void);
/**
* @brief Enables the HA0 to wake up the device from any low power mode.
*/
void MXC_LP_EnableHA0Wakeup (void);
/**
* @brief Disables the HA)0 from waking up the device.
*/
void MXC_LP_DisableHA0Wakeup (void);
/**
* @brief Enables the HA1 to wake up the device from any low power mode.
*/
void MXC_LP_EnableHA1Wakeup (void);
/**
* @brief Disables the HA1 from waking up the device.
*/
void MXC_LP_DisableHA1Wakeup (void);
/**
* @brief Configure which clocks are powered down at deep sleep and which are not affected.
*
* @note Need to configure all clocks at once any clock not passed in the mask will be unaffected by Deepsleep. This will
* always overwrite the previous settings of ALL clocks.
*
* @param[in] mask The mask of the clocks to power down when part goes into deepsleep
*
* @return #E_NO_ERROR or error based on \ref MXC_Error_Codes
*/
int MXC_LP_ConfigDeepSleepClocks (uint32_t mask);
/**
* @brief Enable NFC Oscilator Bypass
*/
void MXC_LP_NFCOscBypassEnable (void);
/**
* @brief Disable NFC Oscilator Bypass
*/
void MXC_LP_NFCOscBypassDisable (void);
/**
* @brief Is NFC Oscilator Bypass Enabled
*
* @return 1 = enabled, 0 = disabled
*/
int MXC_LP_NFCOscBypassIsEnabled (void);
/**
* @brief Enable System Ram 0 in light sleep
*/
void MXC_LP_SysRam0LightSleepEnable (void);
/**
* @brief Enable System Ram 1 in light sleep
*/
void MXC_LP_SysRam1LightSleepEnable (void);
/**
* @brief Enable System Ram 2 in light sleep
*/
void MXC_LP_SysRam2LightSleepEnable (void);
/**
* @brief Enable System Ram 3 in light sleep
*/
void MXC_LP_SysRam3LightSleepEnable (void);
/**
* @brief Enable System Ram 4 in light sleep
*/
void MXC_LP_SysRam4LightSleepEnable (void);
/**
* @brief Enable System Ram 5 in light sleep
*/
void MXC_LP_SysRam5LightSleepEnable (void);
/**
* @brief Enable Icache 0 in light sleep
*/
void MXC_LP_ICache0LightSleepEnable (void);
/**
* @brief Enable Icache XIP in light sleep
*/
void MXC_LP_ICacheXIPLightSleepEnable (void);
/**
* @brief Enable System Cache in light sleep
*/
void MXC_LP_SRCCLightSleepEnable (void);
/**
* @brief Enable Crypto in light sleep
*/
void MXC_LP_CryptoLightSleepEnable (void);
/**
* @brief Enable USB in light sleep
*/
void MXC_LP_USBFIFOLightSleepEnable (void);
/**
* @brief Enable ROM 0 in light sleep
*/
void MXC_LP_ROMLightSleepEnable (void);
/**
* @brief Disable System Ram 0 in light sleep
*/
void MXC_LP_SysRam0LightSleepDisable (void);
/**
* @brief Disable System Ram 1 in light sleep
*/
void MXC_LP_SysRam1LightSleepDisable (void);
/**
* @brief Disable System Ram 2 in light sleep
*/
void MXC_LP_SysRam2LightSleepDisable (void);
/**
* @brief Disable System Ram 3 in light sleep
*/
void MXC_LP_SysRam3LightSleepDisable (void);
/**
* @brief Disable System Ram 4 in light sleep
*/
void MXC_LP_SysRam4LightSleepDisable (void);
/**
* @brief Disable System Ram 5 in light sleep
*/
void MXC_LP_SysRam5LightSleepDisable (void);
/**
* @brief Disable Icache 0 in light sleep
*/
void MXC_LP_ICache0LightSleepDisable (void);
/**
* @brief Disable Icache XIP in light sleep
*/
void MXC_LP_ICacheXIPLightSleepDisable (void);
/**
* @brief Disable System Cache in light sleep
*/
void MXC_LP_SRCCLightSleepDisable (void);
/**
* @brief Disable Crypto in light sleep
*/
void MXC_LP_CryptoLightSleepDisable (void);
/**
* @brief Disable USB in light sleep
*/
void MXC_LP_USBFIFOLightSleepDisable (void);
/**
* @brief Disable ROM 0 in light sleep
*/
void MXC_LP_ROMLightSleepDisable (void);
/**
* @brief Shutdown System Ram 0
*/
void MXC_LP_SysRam0Shutdown (void);
/**
* @brief Wakeup System Ram 0
*/
void MXC_LP_SysRam0PowerUp (void);
/**
* @brief Shutdown System Ram 1
*/
void MXC_LP_SysRam1Shutdown (void);
/**
* @brief PowerUp System Ram 1
*/
void MXC_LP_SysRam1PowerUp (void);
/**
* @brief Shutdown System Ram 2
*/
void MXC_LP_SysRam2Shutdown (void);
/**
* @brief PowerUp System Ram 2
*/
void MXC_LP_SysRam2PowerUp (void);
/**
* @brief Shutdown System Ram 3
*/
void MXC_LP_SysRam3Shutdown (void);
/**
* @brief PowerUp System Ram 3
*/
void MXC_LP_SysRam3PowerUp (void);
/**
* @brief Shutdown System Ram 4
*/
void MXC_LP_SysRam4Shutdown (void);
/**
* @brief PowerUp System Ram 4
*/
void MXC_LP_SysRam4PowerUp (void);
/**
* @brief Shutdown System Ram 5
*/
void MXC_LP_SysRam5Shutdown (void);
/**
* @brief PowerUp System Ram 5
*/
void MXC_LP_SysRam5PowerUp (void);
/**
* @brief Shutdown Internal Cache
*/
void MXC_LP_ICache0Shutdown (void);
/**
* @brief PowerUp Internal Cache
*/
void MXC_LP_ICache0PowerUp (void);
/**
* @brief Shutdown Internal Cache XIP
*/
void MXC_LP_ICacheXIPShutdown (void);
/**
* @brief PowerUp Internal Cache XIP
*/
void MXC_LP_ICacheXIPPowerUp (void);
/**
* @brief Shutdown SRCC
*/
void MXC_LP_SRCCShutdown (void);
/**
* @brief PowerUp SRCC
*/
void MXC_LP_SRCCPowerUp (void);
/**
* @brief Shutdown USB FIFO
*/
void MXC_LP_USBFIFOShutdown (void);
/**
* @brief PowerUp USB FIFO
*/
void MXC_LP_USBFIFOPowerUp (void);
/**
* @brief Shutdown ROM
*/
void MXC_LP_ROMShutdown (void);
/**
* @brief PowerUp ROM
*/
void MXC_LP_ROMPowerUp (void);
/**@} end of group pwrseq */
#ifdef __cplusplus

173
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/msr.h
View File

@ -1,173 +0,0 @@
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
********************************************************************************
*/
/**
* \file
* \brief Magnetic Stripe Reader driver
* \details This driver can be used to configure and operate the Magnetic Stripe
* Reader. It reads and decodes magnetic stripe data that is encoded
* according to the ISO/IEC standard 7811.
* \details This file defines the driver API including data types and function
* prototypes.
*/
#ifndef _MSR_H_
#define _MSR_H_
/***** Definitions *****/
/// Number of tracks on a card
#ifndef MSR_NUM_TRACKS
#define MSR_NUM_TRACKS 3
#endif
#define MSR_MAX_SAMPLES 1536
// Assuming nominal bit density of 210 bpi and 3.375 inch length
#define MSR_MAX_RAW_LEN_BITS (709)
#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8)
#define MSR_MAX_RAW_LEN_HALFWORDS ((MSR_MAX_RAW_LEN_BITS + 15) / 16)
/// Maximum size in bytes of decoded track characters (5-bit min to 8-bit max)
#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5)
/// Swipe direction: the card was swiped in the forward direction
#define MSR_FORWARD 0
/// Swipe direction: the card was swiped in the reverse direction
#define MSR_REVERSE 1
/// Error codes
#define MSR_ERR_OK 0x00
#define MSR_ERR_BAD_LEN 0x01
#define MSR_ERR_START_SEN 0x02
#define MSR_ERR_END_SEN 0x04
#define MSR_ERR_OUTLIER 0x08
#define MSR_ERR_PARAM 0x10
#define MSR_ERR_LRC 0x40
#define MSR_ERR_PARITY 0x80
/// Structure to contain result of a track decode
typedef struct {
uint8_t error_code; /**< Error code value */
uint8_t parity_errs; /**< Number of characters with parity errors */
uint8_t lrc; /**< LRC check value. A value of '0' indicates a
successful LRC check. Any other value should be
considered a failure. */
uint8_t direction; /**< Swipe direction determined from decode */
uint8_t len; /**< Number or decoded characters. This does not include
the sentinels or the LRC. */
uint16_t speed;
uint8_t data[MSR_MAX_DEC_LEN]; /**< The decoded data */
} msr_decoded_track_t;
/// MSR sample fields
typedef union {
struct {
uint16_t time : 9;
uint16_t amp : 7;
};
uint16_t value;
} msr_sample_t;
/// Structure to contain raw MSR samples
typedef struct {
uint16_t len;
msr_sample_t data[MSR_MAX_SAMPLES];
} msr_samples_t;
/***** Function Prototypes *****/
/**
* \brief Initializes magnetic card reader hardware
* \returns #E_NO_ERROR if everything is successful
*/
int msr_init (void);
/**
* \brief Initializes specified track
* \param track track number (1 to 3)
*/
void msr_init_track (unsigned int track);
/**
* \brief Enables magnetic card reader
* \pre The reader should be initialized by calling msr_init() and then
* waiting at least 100 us before calling this function.
*/
void msr_enable (void);
/**
* \brief Disables magnetic card reader
*/
void msr_disable (void);
/**
* \brief Task used to execute driver functionality.
* \details This function executes the internal driver functionality that
* processes MSR events and reads stripe data. This function is used
* when MSR interrupt servicing is disabled.
* \returns 1 if all tracking reading is complete, 0 otherwise
*/
int msr_task (void);
/**
* \brief Decodes the specified track of data
* \param track track number (1 to 3)
* \param decoded_track track decode results
* \returns number of characters decoded
* \note This function has significant stack usage.
*/
unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded_track);
/**
* \brief Registers an application callback function
* \details The callback function will be called after completion of the read
* of all enabled card tracks
* \details Unregistering of the callback can be performed by calling this
* function function with a NULL parameter.
* \param func application callback function
*/
void msr_set_complete_callback (void (*func) (void));
/**
* \brief Retrieves the raw (undecoded) sample data for the specified track
* of data
* \param track track number (1 to 3)
* \param samples pointer to where the sample data will be copied
* \returns number of samples retrieved
*/
unsigned int mcr_get_track_samples (unsigned int track, msr_samples_t * samples);
#endif /* _MSR_H_ */

318
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h Normal file
View File

@ -0,0 +1,318 @@
/**
* @file
* @brief Trust Protection Unit driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _MXC_AES_H_
#define _MXC_AES_H_
/***** Includes *****/
#include "aes_regs.h"
#include "aes_key_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup aes AES
* @ingroup periphlibs
* @{
*/
/*@} end of group aes */
/***** Definitions *****/
typedef void (*mxc_aes_complete_t) (void* req, int result);
/* ************************************************************************* */
/* Cipher Definitions */
/* ************************************************************************* */
/**
* @brief Enumeration type to select AES key
*
*/
typedef enum {
MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key
MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key
MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key
} mxc_aes_keys_t;
/**
* @brief Enumeration type to select AES key source and encryption type
*
*/
typedef enum {
MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key
MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key
MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key
} mxc_aes_enc_type_t;
/**
* @brief Structure used to set up AES request
*
*/
typedef struct _mxc_aes_cipher_req_t {
uint32_t length; ///< Length of the data
uint32_t *inputData; ///< Pointer to input data
uint32_t *resultData; ///< Pointer to encrypted data
mxc_aes_keys_t keySize; ///< Size of AES key
mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t
mxc_aes_complete_t callback; ///< Callback function
} mxc_aes_req_t;
/***** Function Prototypes *****/
/* ************************************************************************* */
/* Global Control/Configuration functions */
/* ************************************************************************* */
/**
* @brief Enable portions of the AES
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_Init (void);
/**
* @brief Enable AES Interrupts
*
* @param interrupt interrupt to enable
*/
void MXC_AES_EnableInt (uint32_t interrupt);
/**
* @brief Disable AES Interrupts
*
* @param interrupt interrupt to disable
*/
void MXC_AES_DisableInt (uint32_t interrupt);
/**
* @brief Checks the global AES Busy Status
*
* @return E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_IsBusy (void);
/**
* @brief Disable and reset portions of the AES
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_Shutdown (void);
/**
* @brief This function should be called from the DMA Handler
* when using Async functions
*/
void MXC_AES_DMACallback (int ch, int error);
/**
* @brief This function should be called before encryption to genrate external key
*/
void MXC_AES_GenerateKey (void);
/**
* @brief Set Key size for encryption or decryption
*
* @param key Key size, see \ref mxc_aes_keys_t for a list of keys
*/
void MXC_AES_SetKeySize (mxc_aes_keys_t key);
/**
* @brief Get the currently set key size
*
* @return mxc_aes_keys_t see \ref mxc_aes_keys_t
*/
mxc_aes_keys_t MXC_AES_GetKeySize (void);
/**
* @brief Flush Input Data FIFO
*
*/
void MXC_AES_FlushInputFIFO (void);
/**
* @brief Flush Output Data FIFO
*
*/
void MXC_AES_FlushOutputFIFO (void);
/**
* @brief Start AES Calculations
*
*/
void MXC_AES_Start (void);
/**
* @brief Get Interrupt flags set
*
* @return return the flags set in intfl register
*/
uint32_t MXC_AES_GetFlags (void);
/**
* @brief Clear the interrupts
*
* @param flags flags to be cleared
*/
void MXC_AES_ClearFlags (uint32_t flags);
/**
* @brief
* @note The result will be stored in the req structure
*
* @param req Structure containing data for the encryption
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_Generic (mxc_aes_req_t* req);
/**
* @brief Perform an encryption
* @note The result will be stored in the req structure
*
* @param req Structure containing data for the encryption
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_Encrypt (mxc_aes_req_t* req);
/**
* @brief Perform a decryption
* @note The result will be stored in the req structure
*
* @param req Structure containing data for the decryption
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_Decrypt (mxc_aes_req_t* req);
/**
* @brief Perform AES TX using DMA. Configures DMA request and starts the transmission.
*
* @param src_addr source address
* @param len number of words of data
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_TXDMAConfig (void *src_addr, int len);
/**
* @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO.
*
* @param dest_addr destination address
* @param len number of words of data
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_RXDMAConfig (void *dest_addr, int len);
/**
* @brief Perform encryption or decryption using DMA
*
* @param req The result will be stored in the req structure. The user needs
* to call MXC_AES_Handler() in the ISR
* @param enc 0 for encryption and 1 for decryption
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_GenericAsync (mxc_aes_req_t* req, uint8_t enc);
/**
* @brief Perform an encryption using Interrupt
* @note The result will be stored in the req structure. The user needs
* to call MXC_AES_Handler() in the ISR
*
* @param req Structure containing data for the encryption
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_EncryptAsync (mxc_aes_req_t* req);
/**
* @brief Perform a decryption using Interrupt
* @note The result will be stored in the req structure. The user needs
* to call MXC_AES_Handler() in the ISR
*
* @param req Structure containing data for the decryption
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_DecryptAsync (mxc_aes_req_t* req);
/**
* @brief Set the external key
* @param key Buffer for the key.
* @param len Key size.
*/
void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len);
/**
* @brief Set the key that will be loaded into the AES key registers on a POR event.
* @param key Buffer for the key.
* @param len Key size.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len);
/**
* @brief Clears the key that will be loaded into the AES key registers on a POR event.
* On subsequent POR events after this function is called, the AES key registers
* will be loaded with all zeroes.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_AES_ClearPORKey();
/**
* @brief Transfers the POR key from the storage memory to the AES key registers.
* This happens automatically after each POR. This function should be used
* if application code overwrites the key registers and wants to switch back
* to the POR value.
* @param len Key size.
*/
void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len);
/**
* @brief Checks to see if a POR key has been programmed.
* @return 1 if a key has been installed, 0 if not.
*/
int MXC_AES_HasPORKey();
#ifdef __cplusplus
}
#endif
/**@} end of group aes */
#endif /* _MXC_AES_H_ */

2
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

6
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -98,8 +98,8 @@ int MXC_Delay (unsigned long us);
* running, it will be started.
* @note MXC_Delay_handler() must be called from the SysTick interrupt service
* routine or at a rate greater than the SysTick overflow rate.
* @param us microseconds to delay
* @param callback Function pointer to the function called once the delay expires.
* @param us microseconds to delay
* @param callback Function pointer to function called upon delay completion.
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request.
*/

34
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h
View File

@ -1,5 +1,10 @@
/**
* @file mxc_device.h
* @brief Device specific header file.
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,23 +34,21 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
/**
* @file mxc_device.h
* @brief contains device and revision specific definitions
*/
#ifndef _MXC_DEVICE_H_
#define _MXC_DEVICE_H_
#include "max32660.h"
#include "max32670.h"
#include "mxc_errors.h"
#include "mxc_pins.h"
#if defined ( __ICCARM__ ) || (__CC_ARM)
#include "RTE_Components.h"
#endif
#ifndef TARGET
#error TARGET NOT DEFINED
#error TARGET NOT DEFINED
#endif
// Create a string definition for the TARGET
@ -57,18 +60,17 @@
// Define which revisions of the IP we are using
#ifndef TARGET_REV
#error TARGET_REV NOT DEFINED
#error TARGET_REV NOT DEFINED
#endif
#if(TARGET_REV == 0x4131)
// A1
#define MXC_PBM_REV 0
#define MXC_TMR_REV 0
#define MXC_UART_REV 1
#if(TARGET_REV == 0x4131)
// A1
#define MXC_TMR_REV 0
#define MXC_UART_REV 0
#else
#error TARGET_REV NOT SUPPORTED
#endif // if(TARGET_REV == ...)
#endif /* if(TARGET_REV == ...) */
#endif /* _MXC_DEVICE_H_ */

2
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

30
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -191,14 +191,14 @@ typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr);
/**
* @brief Set slave address for I2C instances acting as slaves on the bus.
* @note Set idx to zero, multiple I2C instances acting as slaves on the
* bus is not yet supported.
* @brief Initialize and enable I2C peripheral.
* @note Set idx to 0, multiple I2C instances acting as slaves is not yet
* supported.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param slaveAddr 7-bit or 10-bit address to use when in slave mode.
* This parameter is ignored when masterMode is non-zero.
* @param idx Index of the I2C slave.
* @param idx Index of the I2C slave instance.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
@ -213,6 +213,16 @@ int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx);
*/
int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c);
/**
* @brief Reset the I2C peripheral.
* @note The peripheral will need to be initialized with MXC_I2C_Init() before use
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Reset (mxc_i2c_regs_t* i2c);
/**
* @brief Set the frequency of the I2C interface.
*
@ -481,8 +491,8 @@ void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c);
* @brief Get the presently set interrupt flags.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param flags0 Pointer to the variable to store the current status of the interrupt flags in intfl0.
* @param flags1 Pointer to the variable to store the current status of the interrupt flags in intfl0.
* @param flags0 Pointer to store flags currently set in interrupt register intfl0.
* @param flags1 Pointer to store flags currently set in interrupt register intfl1.
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
@ -492,8 +502,8 @@ int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *f
* @brief Clears the Interrupt Flags.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param flags0 Flags to clear in the intfl0 interrupt register.
* @param flags1 Flags to clear in the intfl1 interrupt register.
* @param flags0 Flags to be cleared in interrupt register intfl0.
* @param flags1 Flags to be cleared in interrupt register intfl1.
*/
void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
@ -722,7 +732,7 @@ int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callb
*
* Performs a non-blocking I2C transaction. This request will remain active
* until a complete transaction with this slave has been performed. A
* transaction begins with the masterMXC_I2C_MasterTransactionDMA addressing the
* transaction begins with the master begins with the master addressing the
* slave and ends with a repeated start condition, a stop condition, or a bus
* error. The provided callback function will be called for these events:
* - A slave address match occurs with the master requesting a write to

2
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

60
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h
View File

@ -4,7 +4,7 @@
*/
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -43,43 +43,59 @@
#include "gpio.h"
/***** Global Variables *****/
typedef enum {
MAP_A,
MAP_B,
MAP_C
} sys_map_t;
// Predefined GPIO Configurations
extern const mxc_gpio_cfg_t gpio_cfg_swda;
extern const mxc_gpio_cfg_t gpio_cfg_swdb;
extern const mxc_gpio_cfg_t gpio_cfg_extclk;
extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2b;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2c;
extern const mxc_gpio_cfg_t gpio_cfg_uart0;
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart1a;
extern const mxc_gpio_cfg_t gpio_cfg_uart1b;
extern const mxc_gpio_cfg_t gpio_cfg_uart1c;
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable;
extern const mxc_gpio_cfg_t gpio_cfg_uart1;
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable;
extern const mxc_gpio_cfg_t gpio_cfg_uart2;
extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable;
extern const mxc_gpio_cfg_t gpio_cfg_uart3;
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable;
extern const mxc_gpio_cfg_t gpio_cfg_spi0;
extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss;
extern const mxc_gpio_cfg_t gpio_cfg_spi1a;
extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss;
extern const mxc_gpio_cfg_t gpio_cfg_spi1b;
extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss;
// NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself.
extern const mxc_gpio_cfg_t gpio_cfg_spi1;
// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2
extern const mxc_gpio_cfg_t gpio_cfg_spi2;
extern const mxc_gpio_cfg_t gpio_cfg_spi2b;
// NOTE: SPI3 defined here with SS0 only, and NOT SS1, SS2, or SS3
extern const mxc_gpio_cfg_t gpio_cfg_spi3;
// Timers are only defined once, depending on package, each timer could be mapped to other pins
extern const mxc_gpio_cfg_t gpio_cfg_tmr0;
extern const mxc_gpio_cfg_t gpio_cfg_32kcal;
extern const mxc_gpio_cfg_t gpio_cfg_tmr1;
extern const mxc_gpio_cfg_t gpio_cfg_tmr2;
extern const mxc_gpio_cfg_t gpio_cfg_tmr3;
extern const mxc_gpio_cfg_t gpio_cfg_tmr4;
extern const mxc_gpio_cfg_t gpio_cfg_tmr5;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0a;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0b;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0;
extern const mxc_gpio_cfg_t gpio_cfg_rtcsqw;
extern const mxc_gpio_cfg_t gpio_cfg_rtcsqwb;
extern const mxc_gpio_cfg_t gpio_cfg_lc1;
extern const mxc_gpio_cfg_t gpio_cfg_mon_lc1;
extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc1;
extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc1;
extern const mxc_gpio_cfg_t gpio_cfg_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_mon_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2;
#endif /* _MXC_PINS_H_ */

48
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -46,8 +46,9 @@
#include "mxc_pins.h"
#include "mxc_lock.h"
/***** Definitions *****/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spi SPI
@ -55,6 +56,8 @@
* @{
*/
/***** Definitions *****/
/**
* @brief The list of SPI Widths supported
*
@ -114,26 +117,26 @@ typedef void (*spi_complete_cb_t) (void * req, int result);
* @brief The information required to perform a complete SPI transaction
*
* This structure is used by blocking, async, and DMA based transactions.
* @param "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions.
* @note "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions.
*/
struct _mxc_spi_req_t {
mxc_spi_regs_t* spi; ///<Point to SPI registers
int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode)
int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
mxc_spi_regs_t* spi; ///<Point to SPI registers
int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode)
int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint8_t *rxData; ///< Buffer to store received data For character sizes
uint8_t *rxData; ///< Buffer to store received data For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData
uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData
spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete
spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete
};
/* ************************************************************************* */
@ -165,15 +168,12 @@ struct _mxc_spi_req_t {
* @param hz The requested clock frequency. The actual clock frequency
* will be returned by the function if successful. Used in
* master mode only.
* @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is
* To upper layer firmware drive it.
* 1:Driver will drive SS pin, 0:Driver will NOT drive it
*
* @return If successful, the actual clock frequency is returned. Otherwise, see
* \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
unsigned ssPolarity, unsigned int hz);
/**
* @brief Disable and shutdown SPI peripheral.
@ -198,6 +198,15 @@ int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
*/
int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
/**
* @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Frequency of the clock used as the bit rate generator
*/
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
/**
* @brief Set the frequency of the SPI interface.
*
@ -211,8 +220,6 @@ int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
*/
int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz);
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
/**
* @brief Get the frequency of the SPI interface.
*
@ -639,6 +646,7 @@ void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi);
* @param spi Pointer to SPI registers (selects the SPI block used.)
*/
void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
/**@} end of group spi */
#ifdef __cplusplus

85
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h
View File

@ -4,7 +4,7 @@
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -41,6 +41,7 @@
#include "mxc_device.h"
#include "gcr_regs.h"
#include "mcr_regs.h"
#ifdef __cplusplus
extern "C" {
@ -51,50 +52,90 @@ typedef enum {
MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */
MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */
MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */
MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */
MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TIMER0 */
MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TIMER1 */
MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TIMER2 */
MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TIMER3 */
MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */
MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */
MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */
MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset */
MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset */
/* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0_POS + 64), /**< Reset TMR4 */
MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1_POS + 64), /**< Reset TMR5 */
MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0_POS + 64), /**< Reset UART3 */
} mxc_sys_reset_t;
/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
typedef enum {
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
/* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
MXC_SYS_PERIPH_CLOCK_FLCD = (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
MXC_SYS_PERIPH_CLOCK_UART2 = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
MXC_SYS_PERIPH_CLOCK_WDT0 = (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
MXC_SYS_PERIPH_CLOCK_WDT1 = (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */
MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
MXC_SYS_PERIPH_CLOCK_I2S = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
/* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
MXC_SYS_PERIPH_CLOCK_TMR5 = (MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
MXC_SYS_PERIPH_CLOCK_UART3 = (MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
} mxc_sys_periph_clock_t;
/** @brief Enumeration to select System Clock source */
typedef enum {
MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO,
MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO,
MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO,
MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO,
MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO,
MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
} mxc_sys_system_clock_t;
#define MXC_SYS_USN_CHECKSUM_LEN 16
/***** Function Prototypes *****/
/**
* @brief Reads the device USN.
* @param usn Pointer to store the USN.
* @param checksum Optional pointer to store the AES checksum.
* @returns E_NO_ERROR if everything is successful.
*/
int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
/**
* @brief Determines if the selected peripheral clock is enabled.
* @param clock Enumeration for desired clock.

44
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -61,9 +61,9 @@ extern "C" {
* @brief Bitmasks for each of the RTC's Frequency.
*/
typedef enum {
MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated)
MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, ///< 512Hz (Compensated)
MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz
MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, ///< 1Hz (Compensated)
MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, ///< 512Hz (Compensated)
MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, ///< 4Khz
MXC_RTC_F_32KHZ = 32, ///< 32Khz
} mxc_rtc_freq_sel_t;
@ -71,17 +71,17 @@ typedef enum {
* @brief Bitmasks for each of the RTC's interrupt enables.
*/
typedef enum {
MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable
MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable
MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable
MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, ///< Long-interval alarm interrupt enable
MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IE, ///< Short-interval alarm interrupt enable
MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, ///< Timer ready interrupt enable
} mxc_rtc_int_en_t;
/**
* @brief Bitmasks for each of the RTC's interrupt flags.
*/
typedef enum {
MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag
MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag
MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, ///< Long-interval alarm interrupt flag
MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, ///< Short-interval alarm interrupt flag
MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag
} mxc_rtc_int_fl_t;
@ -101,18 +101,18 @@ int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
int MXC_RTC_SetSubsecondAlarm (uint32_t rssa);
/**
* @brief Start the Real Time Clock
* @brief Start the Real Time Clock (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Start (void);
/**
* @brief Stop the Real Time Clock
* @brief Stop the Real Time Clock (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Stop (void);
/**
* @brief Initialize the sec and ssec registers and enable RTC
* @brief Initialize the sec and ssec registers and enable RTC (Blocking function)
* @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
@ -120,27 +120,27 @@ int MXC_RTC_Stop (void);
int MXC_RTC_Init (uint32_t sec, uint8_t ssec);
/**
* @brief Allow generation of Square Wave on the SQW pin
* @brief Allow generation of Square Wave on the SQW pin (Blocking function)
* @param fq Frequency output selection
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq);
/**
* @brief Stop the generation of square wave
* @brief Stop the generation of square wave (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SquareWaveStop (void);
/**
* @brief Set Trim register value
* @brief Set Trim register value (Blocking function)
* @param trm set the RTC Trim (8-bit, +/- 127)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Trim (int8_t trm);
/**
* @brief Enable Interurpts
* @brief Enable Interurpts (Blocking function)
* @param mask The bitwise OR of interrupts to enable.
* See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
@ -148,7 +148,7 @@ int MXC_RTC_Trim (int8_t trm);
int MXC_RTC_EnableInt (uint32_t mask);
/**
* @brief Disable Interurpts
* @brief Disable Interurpts (Blocking function)
* @param mask The mask of interrupts to disable.
* See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
@ -173,13 +173,13 @@ int MXC_RTC_ClearFlags (int flags);
/**
* @brief Get SubSecond
* @retval Returns subsecond value
* @retval Returns subsecond value or E_BUSY, see /ref MXC_ERROR_CODES
*/
int MXC_RTC_GetSubSecond (void);
/**
* @brief Get Second
* @retval returns second value
* @retval returns second value or E_BUSY, see /ref MXC_ERROR_CODES
*/
int MXC_RTC_GetSecond (void);
@ -191,6 +191,12 @@ int MXC_RTC_GetSecond (void);
*/
int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec);
/**
* @brief Get RTC busy flag.
* @retval returns Success or E_BUSY, see /ref MXC_ERROR_CODES
*/
int MXC_RTC_GetBusyFlag(void);
/**@} end of group rtc */
#ifdef __cplusplus
}

210
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/spimss.h
View File

@ -1,210 +0,0 @@
/**
* @file spimss.h
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPIMSS_H_
#define _SPIMSS_H_
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#include "gpio.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spimss SPIMSS
* @ingroup spimss
* @{
*/
/* **** Definitions **** */
/**
* @brief Enumeration type for setting the number data lines to use for communication.
*/
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
DUMMY_1, /**< NOT USED */
DUMMY_2, /**< NOT USED */
DUMMY_3, /**< NOT USED */
} mxc_spimss_width_t;
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct mxc_spimss_req mxc_spimss_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
*/
typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
*/
struct mxc_spimss_req {
uint8_t ssel; /**< Not Used*/
uint8_t deass; /**< Not Used*/
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
mxc_spimss_width_t width; /**< Not Used */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi Pointer to spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
* @param drv_ssel 1 SSEL will be drive by driver
* 0 SSEL will NOT be drive by driver
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel);
/**
* @brief Shutdown SPI module.
* @param spi Pointer to SPI regs.
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
/**
* @brief Execute a master transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Execute SPI transaction based on interrupt handler
* @param spi The spi
*
*/
void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi);
/**
* @brief Execute a slave transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Sets the TX data to transmit as a 'dummy' byte
*
* In single wire master mode, this data is transmitted on MOSI when performing
* an RX (MISO) only transaction. This defaults to 0.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param defaultTXData Data to shift out in RX-only transactions
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData);
/**
* @brief Aborts an Asynchronous request
*
* @param req Pointer to spi request
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req);
/**@} end of group spimss */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_H_ */

83
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -42,10 +42,11 @@
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "tmr_regs.h"
#include "mxc_sys.h"
#include "gcr_regs.h"
#include "mcr_regs.h"
#include "stdbool.h"
#ifdef __cplusplus
extern "C" {
@ -61,34 +62,33 @@ extern "C" {
* @brief Timer prescaler values
*/
typedef enum {
TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1
TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2
TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4
TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8
TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16
TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32
TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64
TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128
TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256, ///< Divide input clock by 256
TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512, ///< Divide input clock by 512
TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024, ///< Divide input clock by 1024
TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048, ///< Divide input clock by 2048
TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096, ///< Divide input clock by 4096
TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 ///< Divide input clock by 8192
TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, ///< Divide input clock by 1
TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, ///< Divide input clock by 2
TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, ///< Divide input clock by 4
TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, ///< Divide input clock by 8
TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, ///< Divide input clock by 16
TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, ///< Divide input clock by 32
TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, ///< Divide input clock by 64
TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, ///< Divide input clock by 128
TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, ///< Divide input clock by 256
TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, ///< Divide input clock by 512
TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, ///< Divide input clock by 1024
TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, ///< Divide input clock by 2048
TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ///< Divide input clock by 4096
} mxc_tmr_pres_t;
/**
* @brief Timer modes
*/
typedef enum {
TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT
TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS
TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER
TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM
TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE
TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE
TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED
TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE
TMR_MODE_ONESHOT = MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT
TMR_MODE_CONTINUOUS = MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS
TMR_MODE_COUNTER = MXC_S_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER
TMR_MODE_PWM = MXC_S_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM
TMR_MODE_CAPTURE = MXC_S_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE
TMR_MODE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE
TMR_MODE_GATED = MXC_S_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED
TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_CAPCOMP ///< Timer Mode CAPTURECOMPARE
} mxc_tmr_mode_t;
/**
@ -117,9 +117,12 @@ typedef enum {
* 32K and 80K clocks can only be used for Timers 4 and 5
*/
typedef enum {
MXC_TMR_HFIO_CLK, ///< HFIO Clock
MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock
MXC_TMR_EXT_CLK, ///< External Clock
MXC_TMR_APB_CLK, ///< PCLK CLock
MXC_TMR_EXT_CLK, ///< External Clock
MXC_TMR_8M_CLK , ///< 8MHz Clock
MXC_TMR_32M_CLK, ///< 32MHz Clock
MXC_TMR_32K_CLK, ///< 32KHz Clock
MXC_TMR_80K_CLK, ///< 80KHz Clock
} mxc_tmr_clock_t;
/**
@ -143,10 +146,12 @@ typedef void (*mxc_tmr_complete_t) (int error);
* @brief Initialize timer module clock.
* @param tmr Pointer to timer module to initialize.
* @param cfg System configuration object
*
* @param init_pins True will initialize pins corresponding to the TMR and False will not if pins are pinned out otherwise it will not
* be used
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg);
int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg, bool init_pins);
/**
* @brief Shutdown timer module clock.
@ -222,17 +227,33 @@ uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr);
/**
* @brief enable interupt
*
* @param tmr The timer
* @param tmr Pointer to timer module to initialize.
*/
void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr);
/**
* @brief disable interupt
*
* @param tmr The timer
* @param tmr Pointer to timer module to initialize.
*/
void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr);
/**
* @brief Enable wakeup from sleep
*
* @param tmr Pointer to timer module to initialize.
* @param cfg System configuration object
*/
void MXC_TMR_EnableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg);
/**
* @brief Disable wakeup from sleep
*
* @param tmr Pointer to timer module to initialize.
* @param cfg System configuration object
*/
void MXC_TMR_DisableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg);
/**
* @brief Set the timer compare count.
* @param tmr Pointer to timer module to initialize.

137
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h Normal file
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@ -0,0 +1,137 @@
/**
* @file trng.h
* @brief Random number generator driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _TRNG_H_
#define _TRNG_H_
/***** Includes *****/
#include "trng_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup trng TRNG
* @ingroup periphlibs
* @{
*/
/***** Function Prototypes *****/
typedef void (*mxc_trng_complete_t) (void* req, int result);
/* ************************************************************************* */
/* Global Control/Configuration functions */
/* ************************************************************************* */
/**
* @brief Enable portions of the TRNG
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TRNG_Init (void);
/**
* @brief Enable TRNG Interrupts
*
*/
void MXC_TRNG_EnableInt ();
/**
* @brief Disable TRNG Interrupts
*
*/
void MXC_TRNG_DisableInt ();
/**
* @brief Disable and reset portions of the TRNG
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TRNG_Shutdown (void);
/**
* @brief This function should be called from the TRNG ISR Handler
* when using Async functions
*/
void MXC_TRNG_Handler (void);
/* ************************************************************************* */
/* True Random Number Generator (TRNG) functions */
/* ************************************************************************* */
/**
* @brief Get a random number
*
* @return A random 32-bit number
*/
int MXC_TRNG_RandomInt (void);
/**
* @brief Get a random number of length len
*
* @param data Pointer to a location to store the number
* @param len Length of random number in bytes
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TRNG_Random (uint8_t* data, uint32_t len);
/**
* @brief Get a random number of length len, do not block while generating data
* @note The user must call MXC_TRNG_Handler() in the ISR
*
* @param data Pointer to a location to store the number
* @param len Length of random number in bytes
* @param callback Function that will be called when all data has been generated
*
*/
void MXC_TRNG_RandomAsync (uint8_t* data, uint32_t len, mxc_trng_complete_t callback);
/**
* @brief Generate an AES key and transfer to the AES block
*/
void MXC_TRNG_GenerateKey(void);
#ifdef __cplusplus
}
#endif
/**@} end of group trng */
#endif /* _TRNG_H_ */

409
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h
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@ -1,10 +1,10 @@
/**
* @file uart.h
* @brief (UART) communications driver.
* @brief Serial Peripheral Interface (UART) communications driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,15 +35,14 @@
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
/* Define to prevent redundant inclusion */
#ifndef _MXC_UART_H_
#define _MXC_UART_H_
/***** Definitions *****/
#include "uart_regs.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#ifdef __cplusplus
extern "C" {
@ -58,80 +57,84 @@ extern "C" {
typedef struct _mxc_uart_req_t mxc_uart_req_t;
/**
* @brief The list of UART stop bit lengths supported
*
*
*/
typedef enum {
MXC_UART_STOP_1, ///< UART Stop 1 clock cycle
MXC_UART_STOP_1, ///< UART Stop 1 clock cycle
MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters)
} mxc_uart_stop_t;
/**
* @brief The list of UART Parity options supported
*
*
*/
typedef enum {
MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled
MXC_UART_PARITY_EVEN, ///< UART Parity Even
MXC_UART_PARITY_ODD, ///< UART Parity Odd
MXC_UART_PARITY_MARK, ///< UART Parity Mark
MXC_UART_PARITY_SPACE, ///< UART Parity Space
MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based
MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based
MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based
MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based
MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based
MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based
MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based
MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based
} mxc_uart_parity_t;
/**
* @brief The list of UART flow control options supported
*
*
*/
typedef enum {
MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled
MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low
MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High
MXC_UART_FLOW_EN, ///< UART Flow Control Enabled
} mxc_uart_flow_t;
/**
* @brief Clock settings */
typedef enum {
MXC_UART_APB_CLK = 0,
MXC_UART_EXT_CLK = 1,
/*8M (IBRO) and 32M (EFRO) clocks can be used for UARTs 0,1 and 2*/
MXC_UART_IBRO_CLK = 2,
MXC_UART_ERFO_CLK = 3,
/*32K (ERTCO) and INRO clocks can only be used for UART3*/
MXC_UART_ERTCO_CLK = 4,
MXC_UART_INRO_CLK = 5,
} mxc_uart_clock_t;
/**
* @brief The callback routine used to indicate the transaction has terminated.
*
* @param req The details of the transaction.
* @param result See \ref MXC_Error_Codes for the list of error codes.
* @param req The details of the transaction.
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result);
typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t* req, int result);
/**
* @brief The callback routine used to indicate the transaction has terminated.
*
* @param req The details of the transaction.
* @param num The number of characters actually copied
* @param result See \ref MXC_Error_Codes for the list of error codes.
* @param req The details of the transaction.
* @param num The number of characters actually copied
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int result);
typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t* req, int num, int result);
/**
* @brief The information required to perform a complete UART transaction
*
* @note This structure is used by blocking, async, and DMA based transactions.
* This structure is used by blocking, async, and DMA based transactions.
* @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions.
*/
struct _mxc_uart_req_t {
mxc_uart_regs_t* uart; ///<Point to UART registers
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
mxc_uart_regs_t* uart; ///<Point to UART registers
const uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint8_t *rxData; ///< Buffer to store received data For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData
volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData
volatile uint32_t rxCnt; ///< Number of bytes stored in rxData
mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete
};
@ -144,26 +147,24 @@ struct _mxc_uart_req_t {
/**
* @brief Initialize and enable UART peripheral.
*
*
* This function initializes everything necessary to call a UART transaction function.
* Some parameters are set to defaults as follows:
* UART Data Size - 8 bits
* UART Stop Bits - 1 bit
* UART Parity - None
* UART Flow Control - None
* UART Clock - 7.37MHz Clock (for baud > 7372800, PCLK is used)
*
*
* These parameters can be modified after initialization using low level functions
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param baud The requested clock frequency. The actual clock frequency
* will be returned by the function if successful.
* @param clock Clock source
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param baud The requested clock frequency. The actual clock frequency
* will be returned by the function if successful.
* @param map Selects which pin map to use.
*
* @return If successful, the actual clock frequency is returned. Otherwise, see
* \ref MXC_Error_Codes for a list of return codes.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map);
int MXC_UART_Init(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock);
/**
* @brief Disable and shutdown UART peripheral.
@ -172,7 +173,7 @@ int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map);
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Shutdown (mxc_uart_regs_t* uart);
int MXC_UART_Shutdown(mxc_uart_regs_t* uart);
/**
* @brief Checks if the given UART bus can be placed in sleep more.
@ -186,20 +187,19 @@ int MXC_UART_Shutdown (mxc_uart_regs_t* uart);
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart);
int MXC_UART_ReadyForSleep(mxc_uart_regs_t* uart);
/**
* @brief Set the frequency of the UART interface.
*
*
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param baud The desired baud rate
* @param uart Pointer to UART registers (selects the UART block used.)
* @param baud The desired baud rate
* @param clock Clock source
*
* @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud);
int MXC_UART_SetFrequency(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock);
/**
* @brief Get the frequency of the UART interface.
@ -210,97 +210,74 @@ int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud);
*
* @return The UART baud rate
*/
int MXC_UART_GetFrequency (mxc_uart_regs_t* uart);
int MXC_UART_GetFrequency(mxc_uart_regs_t* uart);
/**
* @brief Sets the number of bits per character
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param dataSize The number of bits per character (5-8 bits/character are valid)
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param dataSize The number of bits per character (5-8 bits/character are valid)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize);
int MXC_UART_SetDataSize(mxc_uart_regs_t* uart, int dataSize);
/**
* @brief Sets the number of stop bits sent at the end of a character
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param stopBits The number of stop bits used
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param stopBits The number of stop bits used
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
int MXC_UART_SetStopBits(mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
/**
* @brief Sets the type of parity generation used
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param parity see \ref mxc_uart_parity_t UART Parity Types for details
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param parity see \ref UART Parity Types for details
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
int MXC_UART_SetParity(mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
/**
* @brief Sets the flow control used
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param flowCtrl see \ref mxc_uart_flow_t UART Flow Control Types for details
* @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param flowCtrl see \ref UART Flow Control Types for details
* @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
int MXC_UART_SetFlowCtrl(mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
/**
* @brief Sets the clock source for the baud rate generator
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param clock Clock source
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param usePCLK Non-zero values will use the PCLK as the bit clock instead
* of the default 7.37MHz clock source. The baud rate generator
* will automatically be reconfigured to the closest possible
* baud rate.
*
* @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes
* @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes
* for a list of return codes.
*/
int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK);
/**
* @brief Enables or Disables the built-in null modem
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param nullModem Non-zero values will enable the null modem function,
* which swaps TXD/RXD and also swaps RTS/CTS, if used.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem);
int MXC_UART_SetClockSource(mxc_uart_regs_t* uart, mxc_uart_clock_t clock);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
/**
* @brief Transmits a Break Frame (all bits 0)
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SendBreak (mxc_uart_regs_t* uart);
/**
* @brief Checks the UART Peripheral for an ongoing transmission
*
* @note This function is applicable in Master mode only
*
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_GetActive (mxc_uart_regs_t* uart);
int MXC_UART_GetActive(mxc_uart_regs_t* uart);
/**
* @brief Aborts an ongoing UART Transmission
@ -309,28 +286,7 @@ int MXC_UART_GetActive (mxc_uart_regs_t* uart);
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart);
/**
* @brief Reads the next available character. This function will block until a character
* is available or a UART error occurs.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart);
/**
* @brief Writes a character on the UART. This function will block until the character
* has been placed in the TX FIFO or a UART error occurs.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param character The character to write
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);
int MXC_UART_AbortTransmission(mxc_uart_regs_t* uart);
/**
* @brief Reads the next available character. If no character is available, this function
@ -340,7 +296,7 @@ int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart);
int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t* uart);
/**
* @brief Writes a character on the UART. If the character cannot be written because the
@ -353,6 +309,25 @@ int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart);
*/
int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
/**
* @brief Reads the next available character
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_ReadCharacter(mxc_uart_regs_t* uart);
/**
* @brief Writes a character on the UART
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param character The character to write
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character);
/**
* @brief Reads the next available character
* @note This function blocks until len characters are received
@ -360,48 +335,48 @@ int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param buffer Buffer to store data in
* @param len Number of characters
* @param len Number of characters
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
int MXC_UART_Read(mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
/**
* @brief Writes a byte on the UART
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param byte The buffer of characters to write
* @param byte The buffer of characters to write
* @param len The number of characters to write
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len);
int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len);
/**
* @brief Unloads bytes from the receive FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
*
* @return The number of bytes actually read.
*/
unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO user DMA for longer reads.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
* @param callback The function to call when the read is complete
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
* @param callback The function to call when the read is complete
*
* @return See \ref MXC_Error_Codes for a list of return values
* @return See \ref MXC_ERROR_CODES for a list of return values
*/
int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
*
@ -409,33 +384,33 @@ int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
*
* @return The number of bytes available.
*/
unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart);
unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t* uart);
/**
* @brief Loads bytes into the transmit FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
*
* @return The number of bytes actually written.
*/
unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* bytes,
unsigned int len);
/**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
* @param callback The function to call when the write is complete
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
* @param callback The function to call when the write is complete
*
* @return See \ref MXC_Error_Codes for a list of return values
* @return See \ref MXC_ERROR_CODES for a list of return values
*/
int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
*
@ -443,7 +418,7 @@ int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
*
* @return The number of bytes available.
*/
unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart);
unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t* uart);
/**
* @brief Removes and discards all bytes currently in the receive FIFO.
@ -452,7 +427,7 @@ unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart);
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart);
int MXC_UART_ClearRXFIFO(mxc_uart_regs_t* uart);
/**
* @brief Removes and discards all bytes currently in the transmit FIFO.
@ -461,93 +436,93 @@ int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart);
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart);
int MXC_UART_ClearTXFIFO(mxc_uart_regs_t* uart);
/**
* @brief Set the receive threshold level.
*
*
* @note RX FIFO Receive threshold. Smaller values will cause
* interrupts to occur more often, but reduce the possibility
* of losing data because of a FIFO overflow. Larger values
* will reduce the time required by the ISR, but increase the
* will reduce the time required by the ISR, but increase the
* possibility of data loss. Passing an invalid value will
* cause the driver to use the value already set in the
* cause the driver to use the value already set in the
* appropriate register.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
int MXC_UART_SetRXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes);
/**
* @brief Get the current receive threshold level.
*
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
*
* @return The receive threshold value (in bytes).
*/
unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart);
unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t* uart);
/**
* @brief Set the transmit threshold level.
*
*
* @note TX FIFO threshold. Smaller values will cause interrupts
* to occur more often, but reduce the possibility of terminating
* a transaction early in master mode, or transmitting invalid data
* in slave mode. Larger values will reduce the time required by
* the ISR, but increase the possibility errors occurring. Passing
* an invalid value will cause the driver to use the value already
* the ISR, but increase the possibility errors occurring. Passing
* an invalid value will cause the driver to use the value already
* set in the appropriate register.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
int MXC_UART_SetTXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes);
/**
* @brief Get the current transmit threshold level.
*
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
*
* @return The transmit threshold value (in bytes).
*/
unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart);
unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t* uart);
/**
* @brief Gets the interrupt flags that are currently set
*
* @note These functions should not be used while using non-blocking Transaction Level
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The interrupt flags
*
* @return The interrupt flags
*/
unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart);
unsigned int MXC_UART_GetFlags(mxc_uart_regs_t* uart);
/**
* @brief Clears the interrupt flags that are currently set
*
* @note These functions should not be used while using non-blocking Transaction Level
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param flags mask of flags to clear
*
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags);
int MXC_UART_ClearFlags(mxc_uart_regs_t* uart, unsigned int flags);
/**
* @brief Enables specific interrupts
*
* @note These functions should not be used while using non-blocking Transaction Level
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
@ -555,12 +530,12 @@ int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags);
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask);
int MXC_UART_EnableInt(mxc_uart_regs_t* uart, unsigned int mask);
/**
* @brief Disables specific interrupts
*
* @note These functions should not be used while using non-blocking Transaction Level
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
@ -568,62 +543,60 @@ int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask);
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask);
int MXC_UART_DisableInt(mxc_uart_regs_t* uart, unsigned int mask);
/**
* @brief Gets the status flags that are currently set
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
*
* @return The status flags
*/
unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart);
int MXC_UART_Busy(mxc_uart_regs_t* uart);
unsigned int MXC_UART_GetStatus(mxc_uart_regs_t* uart);
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
/**
* @brief Performs a blocking UART transaction.
*
* @brief Performs a blocking UART transaction.
*
* @note Performs a blocking UART transaction as follows.
* If tx_len is non-zero, transmit TX data
* Once tx_len has been sent, if rx_len is non-zero, receive data
*
* @param req Pointer to details of the transaction
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_Transaction (mxc_uart_req_t* req);
int MXC_UART_Transaction(mxc_uart_req_t* req);
/**
* @brief Setup an interrupt-driven UART transaction
*
*
* @note The TX FIFO will be filled with txData if necessary
* Relevant interrupts will be enabled
*
* @param req Pointer to details of the transaction
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_TransactionAsync (mxc_uart_req_t* req);
int MXC_UART_TransactionAsync(mxc_uart_req_t* req);
/**
* @brief Setup a DMA driven UART transaction
*
*
* @note The TX FIFO will be filled with txData if necessary
* Relevant interrupts will be enabled.
* The DMA channel indicated by the request will be set up to load/unload the FIFOs
* with as few interrupt-based events as possible. The channel will be reset and
* Relevant interrupts will be enabled
* The DMA channel indicated by the request will be set up to load/unload the FIFOs
* with as few interrupt-based events as possible. The channel will be reset and
* returned to the system at the end of the transaction.
*
* @param req Pointer to details of the transaction
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_TransactionDMA (mxc_uart_req_t* req);
int MXC_UART_TransactionDMA(mxc_uart_req_t* req);
/**
* @brief The processing function for DMA transactions.
@ -637,10 +610,10 @@ int MXC_UART_TransactionDMA (mxc_uart_req_t* req);
void MXC_UART_DMACallback (int ch, int error);
/**
* @brief Async callback
* @brief Async callback
*
* @param uart The uart
* @param[in] retVal The ret value
* @param uart The uart
* @param retVal The ret value
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
@ -649,7 +622,7 @@ int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
/**
* @brief stop any async callbacks
*
* @param uart The uart
* @param uart The uart
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
@ -666,7 +639,7 @@ int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AbortAsync (mxc_uart_regs_t* uart);
int MXC_UART_AbortAsync(mxc_uart_regs_t* uart);
/**
* @brief The processing function for asynchronous transactions.
@ -679,7 +652,25 @@ int MXC_UART_AbortAsync (mxc_uart_regs_t* uart);
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart);
int MXC_UART_AsyncHandler(mxc_uart_regs_t* uart);
/**
* @brief Provide TXCount for asynchronous transactions..
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Returns transmit bytes (in FIFO).
*/
uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t* req);
/**
* @brief Provide RXCount for asynchronous transactions..
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Returns receive bytes (in FIFO).
*/
uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req);
/**@} end of group uart */

107
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h
View File

@ -4,7 +4,7 @@
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -40,6 +40,10 @@
#ifndef _WDT_H_
#define _WDT_H_
#ifdef __CC_ARM
#pragma diag_suppress 66 // enumeration value is out of “int” range
#endif
/* **** Includes **** */
#include <stdint.h>
#include "mxc_device.h"
@ -50,42 +54,77 @@ extern "C" {
#endif
/**
* @defgroup wdt Watchdog Timer (WDT)
* @defgroup wdt WDT
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/** @brief Watchdog period enumeration.
/** @brief Watchdog upper limit period enumeration.
Used to configure the period of the watchdog interrupt */
typedef enum {
MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31
MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30
MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29
MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28
MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27
MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26
MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25
MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24
MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23
MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22
MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21
MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20
MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19
MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18
MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17
MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16
MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31, ///< Period 2^31
MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30, ///< Period 2^30
MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29, ///< Period 2^29
MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28, ///< Period 2^28
MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27, ///< Period 2^27
MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26, ///< Period 2^26
MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25, ///< Period 2^25
MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24, ///< Period 2^24
MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23, ///< Period 2^23
MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22, ///< Period 2^22
MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21, ///< Period 2^21
MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20, ///< Period 2^20
MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19, ///< Period 2^19
MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18, ///< Period 2^18
MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17, ///< Period 2^17
MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16, ///< Period 2^16
} mxc_wdt_period_t;
/**
* @brief Watchdog interrupt flag enumeration
*/
typedef enum {
MXC_WDT_INT_TOO_LATE = MXC_F_WDT_CTRL_INT_LATE,
MXC_WDT_INT_TOO_SOON = MXC_F_WDT_CTRL_INT_EARLY,
} mxc_wdt_int_t;
/**
* @brief Watchdog reset flag enumeration
*/
typedef enum {
MXC_WDT_RST_TOO_LATE = MXC_F_WDT_CTRL_RST_LATE,
MXC_WDT_RST_TOO_SOON = MXC_F_WDT_CTRL_RST_EARLY,
} mxc_wdt_rst_t;
/**
* @brief Watchdog mode enumeration
*/
typedef enum {
MXC_WDT_COMPATIBILITY = 0,
MXC_WDT_WINDOWED = 1,
} mxc_wdt_mode_t;
/**
* @brief Timer Configuration
*/
typedef struct {
mxc_wdt_mode_t mode; ///< WDT mode
mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit
mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit
mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit
mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit
} mxc_wdt_cfg_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize the Watchdog Timer
* @param wdt Pointer to the watchdog registers
* @brief Initialize the Watchdog Timer
* @param wdt Pointer to the watchdog registers
* @param cfg watchdog configuration
* @return See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_WDT_Init (mxc_wdt_regs_t* wdt);
int MXC_WDT_Init (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg);
/**
* @brief Shutdown the Watchdog Timer
@ -97,16 +136,16 @@ int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt);
/**
* @brief Set the period of the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
* @param period Enumeration of the desired watchdog period.
* @param cfg watchdog configuration.
*/
void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period);
void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg);
/**
* @brief Set the period of the watchdog reset.
* @param wdt Pointer to watchdog registers.
* @param period Enumeration of the desired watchdog period.
* @param cfg watchdog configuration.
*/
void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period);
void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg);
/**
* @brief Enable the watchdog timer.
@ -127,13 +166,7 @@ void MXC_WDT_Disable (mxc_wdt_regs_t* wdt);
void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt);
/**
* @brief Enable the watchdog reset.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt);
/**
* @brief Enable the watchdog interrupt.
* @brief Disable the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt);
@ -142,6 +175,12 @@ void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt);
* @brief Enable the watchdog reset.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt);
/**
* @brief Disable the watchdog reset.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt);
/**
@ -182,4 +221,4 @@ void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
}
#endif
#endif /* _WDT_H_ */
#endif /* _WDT_H_ */