mirror of https://github.com/ARMmbed/mbed-os.git
Remove __R because of confliction
Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>pull/15263/head
Sadik.Ozer
parent
fc90e9a64e
commit
f40887acdd
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -103,7 +100,7 @@ typedef struct {
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typedef struct {
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__IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */
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__I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */
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__R uint32_t rsv_0x8_0xff[62];
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__I uint32_t rsv_0x8_0xff[62];
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__IO mxc_dma_ch_regs_t ch[8]; /**< <tt>\b 0x100:</tt> DMA CH Register */
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} mxc_dma_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -86,7 +83,7 @@ extern "C" {
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* Structure type to access the ECC Registers.
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*/
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typedef struct {
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__R uint32_t rsv_0x0_0x7[2];
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__I uint32_t rsv_0x0_0x7[2];
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__IO uint32_t en; /**< <tt>\b 0x08:</tt> ECC EN Register */
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} mxc_ecc_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -88,9 +85,9 @@ extern "C" {
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typedef struct {
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__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> EMCC CACHE_ID Register */
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__I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> EMCC MEMCFG Register */
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__R uint32_t rsv_0x8_0xff[62];
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__I uint32_t rsv_0x8_0xff[62];
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__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> EMCC CACHE_CTRL Register */
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__R uint32_t rsv_0x104_0x6ff[383];
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__I uint32_t rsv_0x104_0x6ff[383];
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__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> EMCC INVALIDATE Register */
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} mxc_emcc_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -89,19 +86,19 @@ typedef struct {
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__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
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__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
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__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
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__R uint32_t rsv_0xc_0x23[6];
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__I uint32_t rsv_0xc_0x23[6];
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__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
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__IO uint32_t eccdata; /**< <tt>\b 0x028:</tt> FLC ECCDATA Register */
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__R uint32_t rsv_0x2c;
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__I uint32_t rsv_0x2c;
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__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
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__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
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__R uint32_t rsv_0x44_0x7f[15];
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__I uint32_t rsv_0x44_0x7f[15];
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__IO uint32_t welr0; /**< <tt>\b 0x80:</tt> FLC WELR0 Register */
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__R uint32_t rsv_0x84;
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__I uint32_t rsv_0x84;
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__IO uint32_t welr1; /**< <tt>\b 0x88:</tt> FLC WELR1 Register */
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__R uint32_t rsv_0x8c;
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__I uint32_t rsv_0x8c;
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__IO uint32_t rlr0; /**< <tt>\b 0x90:</tt> FLC RLR0 Register */
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__R uint32_t rsv_0x94;
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__I uint32_t rsv_0x94;
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__IO uint32_t rlr1; /**< <tt>\b 0x98:</tt> FLC RLR1 Register */
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} mxc_flc_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -90,20 +87,20 @@ typedef struct {
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__IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */
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__IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */
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__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
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__R uint32_t rsv_0x10_0x17[2];
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__I uint32_t rsv_0x10_0x17[2];
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__IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */
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__R uint32_t rsv_0x1c_0x23[2];
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__I uint32_t rsv_0x1c_0x23[2];
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__IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */
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__IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */
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__IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */
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__R uint32_t rsv_0x30_0x3f[4];
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__I uint32_t rsv_0x30_0x3f[4];
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__IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */
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__IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */
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__IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */
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__IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */
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__I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */
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__IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */
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__R uint32_t rsv_0x58_0x63[3];
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__I uint32_t rsv_0x58_0x63[3];
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__IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */
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__IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */
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__IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -103,12 +100,12 @@ typedef struct {
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__IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */
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__IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */
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__I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO INTFL Register */
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__R uint32_t rsv_0x44;
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__I uint32_t rsv_0x44;
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__IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */
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__IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */
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__IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */
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__IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
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__R uint32_t rsv_0x58;
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__I uint32_t rsv_0x58;
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__IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
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__IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
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__IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
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@ -118,7 +115,7 @@ typedef struct {
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__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
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__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
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__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
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__R uint32_t rsv_0x80_0xa7[10];
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__I uint32_t rsv_0x80_0xa7[10];
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__IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */
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__IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */
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__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -87,13 +84,13 @@ extern "C" {
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*/
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typedef struct {
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__IO uint32_t ctrl0ch0; /**< <tt>\b 0x00:</tt> I2S CTRL0CH0 Register */
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__R uint32_t rsv_0x4_0xf[3];
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__I uint32_t rsv_0x4_0xf[3];
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__IO uint32_t ctrl1ch0; /**< <tt>\b 0x10:</tt> I2S CTRL1CH0 Register */
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__R uint32_t rsv_0x14_0x2f[7];
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__I uint32_t rsv_0x14_0x2f[7];
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__IO uint32_t dmach0; /**< <tt>\b 0x30:</tt> I2S DMACH0 Register */
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__R uint32_t rsv_0x34_0x3f[3];
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__I uint32_t rsv_0x34_0x3f[3];
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__IO uint32_t fifoch0; /**< <tt>\b 0x40:</tt> I2S FIFOCH0 Register */
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__R uint32_t rsv_0x44_0x4f[3];
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__I uint32_t rsv_0x44_0x4f[3];
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__IO uint32_t intfl; /**< <tt>\b 0x50:</tt> I2S INTFL Register */
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__IO uint32_t inten; /**< <tt>\b 0x54:</tt> I2S INTEN Register */
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__IO uint32_t extsetup; /**< <tt>\b 0x58:</tt> I2S EXTSETUP Register */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -88,9 +85,9 @@ extern "C" {
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typedef struct {
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__I uint32_t info; /**< <tt>\b 0x0000:</tt> ICC INFO Register */
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__I uint32_t sz; /**< <tt>\b 0x0004:</tt> ICC SZ Register */
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__R uint32_t rsv_0x8_0xff[62];
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__I uint32_t rsv_0x8_0xff[62];
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__IO uint32_t ctrl; /**< <tt>\b 0x0100:</tt> ICC CTRL Register */
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__R uint32_t rsv_0x104_0x6ff[383];
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__I uint32_t rsv_0x104_0x6ff[383];
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__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
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} mxc_icc_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -86,9 +83,9 @@ extern "C" {
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* Structure type to access the MCR Registers.
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*/
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typedef struct {
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__R uint32_t rsv_0x0;
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__I uint32_t rsv_0x0;
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__IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */
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__R uint32_t rsv_0x8_0x23[7];
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__I uint32_t rsv_0x8_0x23[7];
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__IO uint32_t clkdis; /**< <tt>\b 0x24:</tt> MCR CLKDIS Register */
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} mxc_mcr_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -91,10 +88,10 @@ typedef struct {
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__IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */
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__IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */
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__IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */
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__R uint32_t rsv_0x14_0x2f[7];
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__I uint32_t rsv_0x14_0x2f[7];
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__IO uint32_t lppwkst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKST Register */
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__IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */
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__R uint32_t rsv_0x38_0x3f[2];
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__I uint32_t rsv_0x38_0x3f[2];
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__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
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} mxc_pwrseq_regs_t;
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -96,7 +93,7 @@ typedef struct {
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__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
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__IO uint32_t sstime; /**< <tt>\b 0x10:</tt> SPI SSTIME Register */
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__IO uint32_t clkctrl; /**< <tt>\b 0x14:</tt> SPI CLKCTRL Register */
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__R uint32_t rsv_0x18;
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__I uint32_t rsv_0x18;
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__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
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__IO uint32_t intfl; /**< <tt>\b 0x20:</tt> SPI INTFL Register */
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__IO uint32_t inten; /**< <tt>\b 0x24:</tt> SPI INTEN Register */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -67,9 +67,6 @@ extern "C" {
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#ifndef __O
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#define __O volatile
|
||||
#endif
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
|
|||
|
|
@ -67,9 +67,6 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -95,7 +92,7 @@ typedef struct {
|
|||
__IO uint32_t txpeek; /**< <tt>\b 0x0018:</tt> UART TXPEEK Register */
|
||||
__IO uint32_t pnr; /**< <tt>\b 0x001C:</tt> UART PNR Register */
|
||||
__IO uint32_t fifo; /**< <tt>\b 0x0020:</tt> UART FIFO Register */
|
||||
__R uint32_t rsv_0x24_0x2f[3];
|
||||
__I uint32_t rsv_0x24_0x2f[3];
|
||||
__IO uint32_t dma; /**< <tt>\b 0x0030:</tt> UART DMA Register */
|
||||
__IO uint32_t wken; /**< <tt>\b 0x0034:</tt> UART WKEN Register */
|
||||
__IO uint32_t wkfl; /**< <tt>\b 0x0038:</tt> UART WKFL Register */
|
||||
|
|
|
|||
|
|
@ -67,9 +67,6 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
|
|||
Loading…
Reference in New Issue