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Unify the __CORTEX_A macro in the files containing cmsis.h

pull/14718/head
Meano 2021-06-03 00:17:40 +08:00
parent d8917a47e5
commit 6feca90589
5 changed files with 8 additions and 8 deletions
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4
cmsis/device/rtos/source/mbed_boot.c
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@ -128,7 +128,7 @@ static void mbed_cpy_nvic(void)
VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
responsible for correctly handling the vectors. responsible for correctly handling the vectors.
*/ */
#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9) #if !defined(__CORTEX_M0) && !defined(__CORTEX_A)
#ifdef NVIC_RAM_VECTOR_ADDRESS #ifdef NVIC_RAM_VECTOR_ADDRESS
uint32_t *old_vectors = (uint32_t *)SCB->VTOR; uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
@ -137,5 +137,5 @@ static void mbed_cpy_nvic(void)
} }
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
#endif /* NVIC_RAM_VECTOR_ADDRESS */ #endif /* NVIC_RAM_VECTOR_ADDRESS */
#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */ #endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A) */
} }

2
hal/source/mbed_critical_section_api.c
View File

@ -26,7 +26,7 @@ static bool state_saved = false;
static bool are_interrupts_enabled(void) static bool are_interrupts_enabled(void)
{ {
#if defined(__CORTEX_A9) #if defined(__CORTEX_A)
return ((__get_CPSR() & 0x80) == 0); return ((__get_CPSR() & 0x80) == 0);
#else #else
return ((__get_PRIMASK() & 0x1) == 0); return ((__get_PRIMASK() & 0x1) == 0);

2
hal/tests/TESTS/mbed_hal/critical_section/main.cpp
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@ -29,7 +29,7 @@ using utest::v1::Case;
bool test_are_interrupts_enabled(void) bool test_are_interrupts_enabled(void)
{ {
#if defined(__CORTEX_A9) #if defined(__CORTEX_A)
return ((__get_CPSR() & 0x80) == 0); return ((__get_CPSR() & 0x80) == 0);
#else #else
return ((__get_PRIMASK() & 0x1) == 0); return ((__get_PRIMASK() & 0x1) == 0);

4
platform/source/mbed_critical.c
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@ -27,7 +27,7 @@ static uint32_t critical_section_reentrancy_counter = 0;
bool core_util_are_interrupts_enabled(void) bool core_util_are_interrupts_enabled(void)
{ {
#if defined(__CORTEX_A9) #if defined(__CORTEX_A)
return ((__get_CPSR() & 0x80) == 0); return ((__get_CPSR() & 0x80) == 0);
#else #else
return ((__get_PRIMASK() & 0x1) == 0); return ((__get_PRIMASK() & 0x1) == 0);
@ -36,7 +36,7 @@ bool core_util_are_interrupts_enabled(void)
bool core_util_is_isr_active(void) bool core_util_is_isr_active(void)
{ {
#if defined(__CORTEX_A9) #if defined(__CORTEX_A)
switch (__get_CPSR() & 0x1FU) { switch (__get_CPSR() & 0x1FU) {
case CPSR_M_USR: case CPSR_M_USR:
case CPSR_M_SYS: case CPSR_M_SYS:

4
platform/source/mbed_sdk_boot.c
View File

@ -63,7 +63,7 @@ void mbed_copy_nvic(void)
VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
responsible for correctly handling the vectors. responsible for correctly handling the vectors.
*/ */
#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9) #if !defined(__CORTEX_M0) && !defined(__CORTEX_A)
#ifdef NVIC_RAM_VECTOR_ADDRESS #ifdef NVIC_RAM_VECTOR_ADDRESS
uint32_t *old_vectors = (uint32_t *)SCB->VTOR; uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
@ -72,7 +72,7 @@ void mbed_copy_nvic(void)
} }
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
#endif /* NVIC_RAM_VECTOR_ADDRESS */ #endif /* NVIC_RAM_VECTOR_ADDRESS */
#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */ #endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A) */
} }
void mbed_init(void) void mbed_init(void)