diff --git a/cmsis/device/rtos/source/mbed_boot.c b/cmsis/device/rtos/source/mbed_boot.c
index dcaf7fdb23..4142816d25 100644
--- a/cmsis/device/rtos/source/mbed_boot.c
+++ b/cmsis/device/rtos/source/mbed_boot.c
@@ -128,7 +128,7 @@ static void mbed_cpy_nvic(void)
     VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
     responsible for correctly handling the vectors.
     */
-#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
+#if !defined(__CORTEX_M0) && !defined(__CORTEX_A)
 #ifdef NVIC_RAM_VECTOR_ADDRESS
     uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
     uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
@@ -137,5 +137,5 @@ static void mbed_cpy_nvic(void)
     }
     SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
 #endif /* NVIC_RAM_VECTOR_ADDRESS */
-#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
+#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A) */
 }
diff --git a/hal/source/mbed_critical_section_api.c b/hal/source/mbed_critical_section_api.c
index d9bbc7bc3b..bb1e6dce4f 100644
--- a/hal/source/mbed_critical_section_api.c
+++ b/hal/source/mbed_critical_section_api.c
@@ -26,7 +26,7 @@ static bool state_saved = false;
 
 static bool are_interrupts_enabled(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A)
     return ((__get_CPSR() & 0x80) == 0);
 #else
     return ((__get_PRIMASK() & 0x1) == 0);
diff --git a/hal/tests/TESTS/mbed_hal/critical_section/main.cpp b/hal/tests/TESTS/mbed_hal/critical_section/main.cpp
index 0741b0fccb..f1c5e85b13 100644
--- a/hal/tests/TESTS/mbed_hal/critical_section/main.cpp
+++ b/hal/tests/TESTS/mbed_hal/critical_section/main.cpp
@@ -29,7 +29,7 @@ using utest::v1::Case;
 
 bool test_are_interrupts_enabled(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A)
     return ((__get_CPSR() & 0x80) == 0);
 #else
     return ((__get_PRIMASK() & 0x1) == 0);
diff --git a/platform/source/mbed_critical.c b/platform/source/mbed_critical.c
index 8d2ded8699..8456030075 100644
--- a/platform/source/mbed_critical.c
+++ b/platform/source/mbed_critical.c
@@ -27,7 +27,7 @@ static uint32_t critical_section_reentrancy_counter = 0;
 
 bool core_util_are_interrupts_enabled(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A)
     return ((__get_CPSR() & 0x80) == 0);
 #else
     return ((__get_PRIMASK() & 0x1) == 0);
@@ -36,7 +36,7 @@ bool core_util_are_interrupts_enabled(void)
 
 bool core_util_is_isr_active(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A)
     switch (__get_CPSR() & 0x1FU) {
         case CPSR_M_USR:
         case CPSR_M_SYS:
diff --git a/platform/source/mbed_sdk_boot.c b/platform/source/mbed_sdk_boot.c
index d77c7d1995..0d0f3b664e 100644
--- a/platform/source/mbed_sdk_boot.c
+++ b/platform/source/mbed_sdk_boot.c
@@ -63,7 +63,7 @@ void mbed_copy_nvic(void)
     VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
     responsible for correctly handling the vectors.
     */
-#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
+#if !defined(__CORTEX_M0) && !defined(__CORTEX_A)
 #ifdef NVIC_RAM_VECTOR_ADDRESS
     uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
     uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
@@ -72,7 +72,7 @@ void mbed_copy_nvic(void)
     }
     SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
 #endif /* NVIC_RAM_VECTOR_ADDRESS */
-#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
+#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A) */
 }
 
 void mbed_init(void)