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TARGET_STM32F3 astyle

pull/7351/head
jeromecoutant 2018-06-27 14:32:10 +02:00
parent f9bd4768a5
commit 6df23ee841
22 changed files with 327 additions and 320 deletions
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18
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h
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@ -54,14 +54,14 @@ typedef enum {
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT0 = PA_7 | ALT0,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT0 = PA_11 | ALT0,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT0 = PA_12 | ALT0,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
@ -81,10 +81,10 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_1 = 0x21,
@ -169,17 +169,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

24
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h
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@ -53,33 +53,33 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT0 = PA_11 | ALT0,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT0 = PA_12 | ALT0,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT0 = PB_1 | ALT0,
PB_3 = 0x13,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT0 = PB_4 | ALT0,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT0 = PB_5 | ALT0,
PB_6 = 0x16,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT0 = PB_7 | ALT0,
PF_0 = 0x50,
PF_1 = 0x51,
@ -148,11 +148,11 @@ typedef enum {
SPI_CS = PA_11,
PWM_OUT = PA_8,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

102
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h
View File

@ -51,88 +51,88 @@ typedef enum {
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_13_ALT0 = PA_13|ALT0,
PA_13_ALT0 = PA_13 | ALT0,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT1 = PB_6|ALT1,
PB_6_ALT0 = PB_6 | ALT0,
PB_6_ALT1 = PB_6 | ALT1,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -149,15 +149,15 @@ typedef enum {
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_10_ALT0 = PD_10|ALT0,
PD_10_ALT0 = PD_10 | ALT0,
PD_11 = 0x3B,
PD_11_ALT0 = PD_11|ALT0,
PD_11_ALT0 = PD_11 | ALT0,
PD_12 = 0x3C,
PD_12_ALT0 = PD_12|ALT0,
PD_12_ALT0 = PD_12 | ALT0,
PD_13 = 0x3D,
PD_13_ALT0 = PD_13|ALT0,
PD_13_ALT0 = PD_13 | ALT0,
PD_14 = 0x3E,
PD_14_ALT0 = PD_14|ALT0,
PD_14_ALT0 = PD_14 | ALT0,
PD_15 = 0x3F,
PE_0 = 0x40,
@ -169,7 +169,7 @@ typedef enum {
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_8_ALT0 = PE_8|ALT0,
PE_8_ALT0 = PE_8 | ALT0,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
@ -181,7 +181,7 @@ typedef enum {
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,
PF_2_ALT0 = PF_2|ALT0,
PF_2_ALT0 = PF_2 | ALT0,
PF_3 = 0x53,
PF_4 = 0x54,
PF_5 = 0x55,
@ -271,17 +271,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c
View File

@ -66,7 +66,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -129,7 +129,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

90
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h
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@ -51,89 +51,89 @@ typedef enum {
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_13_ALT0 = PA_13|ALT0,
PA_13_ALT0 = PA_13 | ALT0,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT1 = PB_6|ALT1,
PB_6_ALT0 = PB_6 | ALT0,
PB_6_ALT1 = PB_6 | ALT1,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_11_ALT0 = PB_11|ALT0,
PB_11_ALT0 = PB_11 | ALT0,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -213,17 +213,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c
View File

@ -62,7 +62,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -125,7 +125,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h
View File

@ -59,7 +59,7 @@ typedef enum {
SPI_1 = (int)SPI1_BASE,
SPI_2 = (int)SPI2_BASE,
SPI_3 = (int)SPI3_BASE,
SPI_4 = (int)SPI4_BASE
SPI_4 = (int)SPI4_BASE
} SPIName;
@ -78,7 +78,7 @@ typedef enum {
PWM_15 = (int)TIM15_BASE,
PWM_16 = (int)TIM16_BASE,
PWM_17 = (int)TIM17_BASE,
PWM_20 = (int)TIM20_BASE
PWM_20 = (int)TIM20_BASE
} PWMName;
typedef enum {

112
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h
View File

@ -50,87 +50,87 @@ typedef enum {
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT0 = PA_3 | ALT0,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_13_ALT0 = PA_13|ALT0,
PA_13_ALT0 = PA_13 | ALT0,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT1 = PB_6|ALT1,
PB_6_ALT0 = PB_6 | ALT0,
PB_6_ALT1 = PB_6 | ALT1,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_11_ALT0 = PB_11|ALT0,
PB_11_ALT0 = PB_11 | ALT0,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
@ -149,32 +149,32 @@ typedef enum {
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_10_ALT0 = PD_10|ALT0,
PD_10_ALT0 = PD_10 | ALT0,
PD_11 = 0x3B,
PD_11_ALT0 = PD_11|ALT0,
PD_11_ALT0 = PD_11 | ALT0,
PD_12 = 0x3C,
PD_12_ALT0 = PD_12|ALT0,
PD_12_ALT0 = PD_12 | ALT0,
PD_13 = 0x3D,
PD_13_ALT0 = PD_13|ALT0,
PD_13_ALT0 = PD_13 | ALT0,
PD_14 = 0x3E,
PD_14_ALT0 = PD_14|ALT0,
PD_14_ALT0 = PD_14 | ALT0,
PD_15 = 0x3F,
PE_0 = 0x40,
PE_1 = 0x41,
PE_1_ALT0 = PE_1|ALT0,
PE_1_ALT0 = PE_1 | ALT0,
PE_2 = 0x42,
PE_2_ALT0 = PE_2|ALT0,
PE_2_ALT0 = PE_2 | ALT0,
PE_3 = 0x43,
PE_3_ALT0 = PE_3|ALT0,
PE_3_ALT0 = PE_3 | ALT0,
PE_4 = 0x44,
PE_4_ALT0 = PE_4|ALT0,
PE_4_ALT0 = PE_4 | ALT0,
PE_5 = 0x45,
PE_5_ALT0 = PE_5|ALT0,
PE_5_ALT0 = PE_5 | ALT0,
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_8_ALT0 = PE_8|ALT0,
PE_8_ALT0 = PE_8 | ALT0,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
@ -186,7 +186,7 @@ typedef enum {
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,
PF_2_ALT0 = PF_2|ALT0,
PF_2_ALT0 = PF_2 | ALT0,
PF_3 = 0x53,
PF_4 = 0x54,
PF_5 = 0x55,
@ -291,17 +291,17 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c
View File

@ -62,7 +62,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -125,7 +125,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

46
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h
View File

@ -53,42 +53,42 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
@ -96,10 +96,10 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -174,13 +174,13 @@ typedef enum {
SPI_CS = PA_4,
PWM_OUT = PB_6,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

54
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h
View File

@ -53,42 +53,42 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
@ -96,19 +96,19 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
@ -191,13 +191,13 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

6
targets/TARGET_STM/TARGET_STM32F3/analogin_device.c
View File

@ -170,8 +170,7 @@ uint16_t adc_read(analogin_t *obj)
if ((ADCName)obj->handle.Instance == ADC_1) {
sConfig.Channel = ADC_CHANNEL_VOPAMP1;
sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5;
}
else {
} else {
sConfig.Channel = ADC_CHANNEL_15;
}
break;
@ -179,8 +178,7 @@ uint16_t adc_read(analogin_t *obj)
if ((ADCName)obj->handle.Instance == ADC_1) {
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5;
}
else {
} else {
sConfig.Channel = ADC_CHANNEL_16;
}
break;

16
targets/TARGET_STM/TARGET_STM32F3/analogout_device.c
View File

@ -39,7 +39,8 @@
static int pa4_used = 0;
static int pa5_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -85,7 +86,7 @@ void analogout_init(dac_t *obj, PinName pin) {
obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
obj->handle.State = HAL_DAC_STATE_RESET;
if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
error("HAL_DAC_Init failed");
}
@ -115,10 +116,15 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->pin == PA_4) pa4_used = 0;
if (obj->pin == PA_5) pa5_used = 0;
if (obj->pin == PA_4) {
pa4_used = 0;
}
if (obj->pin == PA_5) {
pa5_used = 0;
}
if ((pa4_used == 0) && (pa5_used == 0)) {
__HAL_RCC_DAC1_FORCE_RESET();

2
targets/TARGET_STM/TARGET_STM32F3/flash_api.c
View File

@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
} else { /* case where data is aligned, so let's avoid any copy */
while ((address < (StartAddress + size)) && (status == 0)) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) {
address = address + MIN_PROG_SIZE;
data = data + MIN_PROG_SIZE;
} else {

7
targets/TARGET_STM/TARGET_STM32F3/pin_device.h
View File

@ -57,14 +57,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
}
}
static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

124
targets/TARGET_STM/TARGET_STM32F3/serial_device.c
View File

@ -33,9 +33,9 @@
#include "serial_api_hal.h"
#if defined (TARGET_STM32F302x8) || defined (TARGET_STM32F303x8) || defined (TARGET_STM32F334x8)
#define UART_NUM (3)
#define UART_NUM (3)
#else
#define UART_NUM (5) // max value
#define UART_NUM (5) // max value
#endif
uint32_t serial_irq_ids[UART_NUM] = {0};
@ -55,12 +55,12 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
irq_handler(serial_irq_ids[id], TxIrq);
}
irq_handler(serial_irq_ids[id], TxIrq);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
@ -115,7 +115,7 @@ static void uart5_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -246,7 +246,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -266,7 +266,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -288,7 +288,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -296,9 +296,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -356,7 +356,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -370,28 +370,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -401,14 +401,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -429,18 +429,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -450,8 +450,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -463,10 +463,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -479,20 +479,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
}
@ -517,49 +519,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -567,7 +569,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -581,11 +583,11 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
return return_event;
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -595,17 +597,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -622,20 +624,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -665,9 +667,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -697,7 +699,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

11
targets/TARGET_STM/TARGET_STM32F3/spi_api.c
View File

@ -39,20 +39,21 @@
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
int spi_hz = 0;
/* Get source clock depending on SPI instance */
/* Get source clock depending on SPI instance */
switch ((int)spiobj->spi) {
#if defined SPI1_BASE
case SPI_1: