Merge pull request #12615 from jeromecoutant/PR_FPGA_UART

FPGA UART test cases addition with 7 and 9 bits data length

TESTS/configs/fpga.json

@@ -13,7 +13,8 @@
         },
         "K64F": {
             "target.macros_add": [
-                "UART_7BITS_PARITY_NONE_NOT_SUPPORTED"
+                "UART_7BITS_NOT_SUPPORTED",
+                "UART_9BITS_NOT_SUPPORTED"
             ]
         },
         "STM": {

TESTS/mbed_hal_fpga_ci_test_shield/README.md

@@ -0,0 +1,51 @@
+# Testing with FPGA CI TEST shield
+
+## Setup
+
+![30% center](fpga_test_shield.jpg)
+
+```
+mbed test -n tests*fpga* --app-config tests/configs/fpga.json
+```
+
+FPGA_CI_TEST_SHIELD needed macro  
+and specific test capabilities per target  
+are defined in:  
+https://github.com/ARMmbed/mbed-os/blob/master/TESTS/configs/fpga.json
+
+
+
+## MBED-OS
+
+Tested from factor is defined by MBED_CONF_TARGET_DEFAULT_FORM_FACTOR  
+"default-form-factor" default value is null.
+
+When "default-form-factor" is not set, ARDUINO form factor is used.
+
+Default ff_arduino_pins is defined in:
+https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L28-L32
+
+Default ff_arduino_names is defined in:
+https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L34-L38
+
+Default empty_gpio_pinmap is defined in:
+https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_gpio.c#L89-L114
+
+Some pins are restricted:
+https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L69-L73
+
+Some peripherals are restricted:
+https://github.com/ARMmbed/mbed-os/blob/master/hal/mbed_pinmap_default.cpp#L94-L100
+
+
+## Known issues
+
+
+## LINKS
+
+https://github.com/ARMmbed/fpga-ci-test-shield
+
+https://github.com/ARMmbed/fpga-ci-test-shield-updater
+
+https://github.com/ARMmbed/fpga-ci-test-shield-terminal
+

TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp

@@ -86,16 +86,37 @@ static void test_irq_handler(uint32_t id, SerialIrq event)
 static void uart_test_common(int baudrate, int data_bits, SerialParity parity, int stop_bits, bool init_direct, PinName tx, PinName rx, PinName cts, PinName rts)
 {
     // The FPGA CI shield only supports None, Odd & Even.
-    // Forced parity is not supported on Atmel, Freescale, Nordic & STM targets.
+    // Forced parity is not supported on many targets
     MBED_ASSERT(parity != ParityForced1 && parity != ParityForced0);
 
-    // STM-specific constraints
-    // Only 7, 8 & 9 data bits.
-    MBED_ASSERT(data_bits >= 7 && data_bits <= 9);
-    // Only Odd or Even parity for 7 data bits.
-    if (data_bits == 7) {
-        MBED_ASSERT(parity != ParityNone);
+// See TESTS/configs/fpga.json to check which target supports what
+#if defined(UART_9BITS_NOT_SUPPORTED)
+    if (data_bits == 9) {
+        utest_printf(" UART_9BITS_NOT_SUPPORTED set ... ");
+        return;
     }
+#endif
+
+#if defined(UART_9BITS_PARITY_NOT_SUPPORTED)
+    if ((data_bits == 9) && (parity != ParityNone)) {
+        utest_printf(" UART_9BITS_PARITY_NOT_SUPPORTED set ... ");
+        return;
+    }
+#endif
+
+#if defined(UART_7BITS_NOT_SUPPORTED)
+    if (data_bits == 7) {
+        utest_printf(" UART_7BITS_NOT_SUPPORTED set ... ");
+        return;
+    }
+#endif
+
+#if defined(UART_7BITS_PARITY_NONE_NOT_SUPPORTED)
+    if ((data_bits == 7) && (parity == ParityNone)) {
+        utest_printf(" UART_7BITS_PARITY_NONE_NOT_SUPPORTED set ... ");
+        return;
+    }
+#endif
 
     // Limit the actual TX & RX chars to 8 bits for this test.
     int test_buff_bits = data_bits < 8 ? data_bits : 8;
@@ -333,6 +354,10 @@ Case cases[] = {
     Case("basic, 9600, 8N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 1, false> >),
     Case("basic (direct init), 9600, 8N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 1, true> >),
 
+    // same test with 7 and 9 bits data length
+    Case("basic, 9600, 7N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 7, ParityNone, 1, false> >),
+    Case("basic, 9600, 9N1, FC off", all_peripherals<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 9, ParityNone, 1, false> >),
+
     // One set of pins from one peripheral.
     // baudrate
     Case("19200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<19200, 8, ParityNone, 1, false> >),
@@ -351,6 +376,10 @@ Case cases[] = {
     Case("basic, 9600, 8N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 1, false> >),
     Case("basic (direct init), 9600, 8N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 1, true> >),
 
+    // same test with 7 and 9 bits data length
+    Case("basic, 9600, 7N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 7, ParityNone, 1, false> >),
+    Case("basic, 9600, 9N1, FC on", all_peripherals<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 9, ParityNone, 1, false> >),
+
     // One set of pins from one peripheral.
     // baudrate
     Case("19200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<19200, 8, ParityNone, 1, false> >),
@@ -360,8 +389,17 @@ Case cases[] = {
     // parity
 #if !defined(UART_ODD_PARITY_NOT_SUPPORTED)
     Case("9600, 8O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityOdd, 1, false> >),
+
+    // same test with 7 and 9 bits data length
+    Case("9600, 7O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 7, ParityOdd, 1, false> >),
+    Case("9600, 9O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 9, ParityOdd, 1, false> >),
 #endif
     Case("9600, 8E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityEven, 1, false> >),
+
+    // same test with 7 and 9 bits data length
+    Case("9600, 7E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 7, ParityEven, 1, false> >),
+    Case("9600, 9E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 9, ParityEven, 1, false> >),
+
     // stop bits
 #if !defined(UART_TWO_STOP_BITS_NOT_SUPPORTED)
     Case("9600, 8N2, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 2, false> >),

targets/targets.json

@@ -5640,9 +5640,7 @@
             "WSF_MAX_HANDLERS=10",
             "MBED_MPU_CUSTOM",
             "SWI_DISABLE0",
-            "NRF52_PAN_20",
-            "UART_TWO_STOP_BITS_NOT_SUPPORTED",
-            "UART_ODD_PARITY_NOT_SUPPORTED"
+            "NRF52_PAN_20"
         ],
         "features": [
             "CRYPTOCELL310",