mirror of https://github.com/ARMmbed/mbed-os.git
Resolved merge conflict
akhilpanayam
Karthik Purushothaman
parent
f5f1c96d2b
commit
6798b87180
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include <compiler.h>
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#include "cmsis.h"
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#include "PinNames.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _SERCOM_SPI_NAME(n, unused) \
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SPI##n,
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#define _SERCOM_PAD_NAME(n, pad) \
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SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
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#define _SERCOM_I2C_NAME(n, unused) \
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I2C##n,
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typedef enum {
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UART_0 = (int)0x42000800UL, // Base address of SERCOM0
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UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
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UART_2 = (int)0x42001000UL, // Base address of SERCOM2
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UART_3 = (int)0x42001400UL, // Base address of SERCOM3
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UART_4 = (int)0x42001800UL, // Base address of SERCOM4
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UART_5 = (int)0x42001C00UL // Base address of SERCOM5
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} UARTName;
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typedef enum { // for each input control mux 4,5,6,7,16,17,10,11 used in R21
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ADC_2 = 0x2ul,
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ADC_3 = 0x3ul,
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ADC_4 = 0x4ul,
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ADC_5 = 0x5ul,
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ADC_6 = 0x6ul,
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ADC_7 = 0x7ul,
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ADC_8 = 0x8ul,
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ADC_10 = 0xAul,
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ADC_11 = 0xBul,
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ADC_16 = 0x10ul,
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ADC_17 = 0x11ul,
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ADC_18 = 0x12ul,
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ADC_19 = 0x13ul
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} ADCName;
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typedef enum { // for each channel
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EXTINT_0 = 0,
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EXTINT_1,
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EXTINT_2,
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EXTINT_3,
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EXTINT_4,
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EXTINT_5,
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EXTINT_6,
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EXTINT_7,
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EXTINT_8,
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EXTINT_9,
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EXTINT_10,
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EXTINT_11,
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EXTINT_12,
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EXTINT_13,
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EXTINT_14,
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EXTINT_15
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} EXTINTName;
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typedef enum {
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MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
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} SPIName;
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typedef enum {
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MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
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} I2CName;
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typedef enum {
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/* Pad 0 definitions */
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MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
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/* Pad 1 definitions */
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MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
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/* Pad 2 definitions */
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MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
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/* Pad 3 definitions */
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MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
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} SercomPadName;
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typedef enum {
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PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
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PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
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PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
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} PWMName;
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struct pwm_pin_channel {
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PinName pin;
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PWMName pwm;
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uint8_t channel_index;
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};
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#define STDIO_UART_TX USBTX
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#define STDIO_UART_RX USBRX
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#define STDIO_UART UART_0
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// Default peripherals
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#define MBED_SPI0 PB22, PB02, PB23, PA14
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#define MBED_UART0 PA04, PA05
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#define MBED_UARTUSB USBTX, USBRX
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#define MBED_I2C0 PA16, PA17
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#define MBED_ANALOGIN0 PA04
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#define MBED_ANALOGIN1 PA05
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#define MBED_ANALOGIN2 PA06
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#define MBED_ANALOGIN3 PA07
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#define MBED_ANALOGIN4 PB02
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#define MBED_ANALOGIN5 PB03
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#define MBED_ANALOGIN7 PA08
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#define MBED_ANALOGIN8 PA09
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#define MBED_PWMOUT0 PA18
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#define MBED_PWMOUT1 PA19
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,225 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "PeripheralPins.h"
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/************ADC***************/
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const PinMap PinMap_ADC[] = {
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{PB08, ADC_2, 1},
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{PB09, ADC_3, 1},
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{PA04, ADC_4, 1},
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{PA05, ADC_5, 1},
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{PA06, ADC_6, 1},
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{PA07, ADC_7, 1},
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{PB00, ADC_8, 1},
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{PB02, ADC_10, 1},
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{PB03, ADC_11, 1},
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{PA08, ADC_16, 1},
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{PA09, ADC_17, 1},
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{PA10, ADC_18, 1},
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{PA11, ADC_19, 1},
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/* Not connected */
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{NC , NC , NC}
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};
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/************SERCOM Pins***********/
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const PinMap PinMap_SERCOM_PAD[] = {
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{PA00, SERCOM1_PAD0, 3},
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{PA01, SERCOM1_PAD1, 3},
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{PA04, SERCOM0_PAD0, 3},
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{PA05, SERCOM0_PAD1, 3},
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{PA06, SERCOM0_PAD2, 3},
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{PA07, SERCOM0_PAD3, 3},
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{PA08, SERCOM0_PAD0, 2},
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{PA09, SERCOM0_PAD1, 2},
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{PA12, SERCOM2_PAD0, 2},
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{PA13, SERCOM2_PAD1, 2},
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{PA14, SERCOM2_PAD2, 2},
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{PA15, SERCOM2_PAD3, 2},
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{PA16, SERCOM1_PAD0, 2},
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{PA17, SERCOM1_PAD1, 2},
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{PA18, SERCOM1_PAD2, 2},
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{PA19, SERCOM1_PAD3, 2},
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{PA22, SERCOM3_PAD0, 2},
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{PA23, SERCOM3_PAD1, 2},
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{PA24, SERCOM3_PAD2, 2},
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{PA25, SERCOM3_PAD3, 2},
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{PA27, SERCOM3_PAD0, 5},
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{PA28, SERCOM3_PAD1, 5},
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{PA30, SERCOM1_PAD2, 3},
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{PA31, SERCOM1_PAD3, 3},
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{PB02, SERCOM5_PAD0, 3},
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{PB03, SERCOM5_PAD1, 3},
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{PB22, SERCOM5_PAD2, 3},
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{PB23, SERCOM5_PAD3, 3},
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{PB30, SERCOM4_PAD2, 5},
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{PB31, SERCOM4_PAD1, 5},
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{PC18, SERCOM4_PAD3, 5},
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{PC19, SERCOM4_PAD0, 5},
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/* Not connected */
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{NC , NC , NC}
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};
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/*******SERCOM Pins extended*******/
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const PinMap PinMap_SERCOM_PADEx[] = {
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{PA08, SERCOM2_PAD0, 3},
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{PA09, SERCOM2_PAD1, 3},
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{PA16, SERCOM3_PAD0, 3},
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{PA17, SERCOM3_PAD1, 3},
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{PA18, SERCOM3_PAD2, 3},
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{PA19, SERCOM3_PAD3, 3},
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{PA22, SERCOM5_PAD0, 3},
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{PA23, SERCOM5_PAD1, 3},
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{PA24, SERCOM5_PAD2, 3},
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{PA25, SERCOM5_PAD3, 3},
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/* Not connected */
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{NC , NC , NC}
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};
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/************PWM***************/
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const PinMap PinMap_PWM[] = {
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{PA00, PWM_2, 4},
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{PA01, PWM_2, 4},
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{PA04, PWM_0, 4},
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{PA05, PWM_0, 4},
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{PA06, PWM_1, 4},
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{PA07, PWM_1, 4},
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{PA08, PWM_0, 4},
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{PA09, PWM_0, 4},
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{PA10, PWM_1, 4},
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{PA11, PWM_1, 4},
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{PA12, PWM_2, 4},
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{PA13, PWM_2, 4},
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{PA16, PWM_2, 4},
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{PA17, PWM_2, 4},
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{PA18, PWM_0, 5},
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{PA19, PWM_0, 5},
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{PA20, PWM_0, 5},
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{PA22, PWM_0, 5},
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{PA23, PWM_0, 5},
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{PA24, PWM_1, 5},
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{PA25, PWM_1, 5},
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{PA30, PWM_1, 4},
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{PA31, PWM_1, 4},
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{PB16, PWM_0, 5},
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{PB17, PWM_0, 5},
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{PB30, PWM_0, 4},
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{PB31, PWM_0, 4},
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/* Not connected */
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{NC , NC , NC}
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};
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/**********EXTINT*************/
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const PinMap PinMap_EXTINT[] = {
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{PA16, EXTINT_0, 0},
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{PB00, EXTINT_0, 0},
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{PB16, EXTINT_0, 0},
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{PA00, EXTINT_0, 0},
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{PA17, EXTINT_1, 0},
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{PB17, EXTINT_1, 0},
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{PA01, EXTINT_1, 0},
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{PA18, EXTINT_2, 0},
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{PB02, EXTINT_2, 0},
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{PA19, EXTINT_3, 0},
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{PB03, EXTINT_3, 0},
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{PA04, EXTINT_4, 0},
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{PA20, EXTINT_4, 0},
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{PA05, EXTINT_5, 0},
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{PA06, EXTINT_6, 0},
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{PA22, EXTINT_6, 0},
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{PB22, EXTINT_6, 0},
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{PA07, EXTINT_7, 0},
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{PA23, EXTINT_7, 0},
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{PB23, EXTINT_7, 0},
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{PA28, EXTINT_8, 0},
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{PB08, EXTINT_8, 0},
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{PA09, EXTINT_9, 0},
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{PB09, EXTINT_9, 0},
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{PA30, EXTINT_10, 0},
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{PA10, EXTINT_10, 0},
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{PA31, EXTINT_11, 0},
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{PA11, EXTINT_11, 0},
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{PA12, EXTINT_12, 0},
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{PA24, EXTINT_12, 0},
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{PA13, EXTINT_13, 0},
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{PA25, EXTINT_13, 0},
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{PB14, EXTINT_14, 0},
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{PB30, EXTINT_14, 0},
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{PA14, EXTINT_14, 0},
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{PA15, EXTINT_15, 0},
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{PA27, EXTINT_15, 0},
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{PB15, EXTINT_15, 0},
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{PB31, EXTINT_15, 0},
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/* Not connected */
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{NC , NC , NC}
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};
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const struct pwm_pin_channel pwn_pins[] = {
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{PA00, PWM_2, 0},
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{PA01, PWM_2, 1},
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{PA04, PWM_0, 0},
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{PA05, PWM_0, 1},
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{PA06, PWM_1, 0},
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{PA07, PWM_1, 1},
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{PA08, PWM_0, 0},
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{PA09, PWM_0, 1},
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{PA10, PWM_1, 0},
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{PA11, PWM_1, 1},
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{PA12, PWM_2, 0},
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{PA13, PWM_2, 1},
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{PA16, PWM_2, 0},
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{PA17, PWM_2, 1},
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{PA18, PWM_0, 2},
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{PA19, PWM_0, 3},
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{PA20, PWM_0, 6},
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{PA22, PWM_0, 4},
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{PA23, PWM_0, 5},
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{PA24, PWM_1, 2},
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{PA25, PWM_1, 3},
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{PA30, PWM_1, 0},
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{PA31, PWM_1, 1},
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{PB16, PWM_0, 4},
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{PB17, PWM_0, 5},
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{PB30, PWM_0, 0},
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{PB31, PWM_0, 1},
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/* Not connected */
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{NC , NC , NC}
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};
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@ -0,0 +1,37 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
|
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALPINS_H
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#define MBED_PERIPHERALPINS_H
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#include "pinmap.h"
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#include "PeripheralNames.h"
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/************ADC***************/
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extern const PinMap PinMap_ADC[];
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//*********SERCOM*************/
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extern const PinMap PinMap_SERCOM_PAD[];
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extern const PinMap PinMap_SERCOM_PADEx[];
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/************PWM***************/
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extern const PinMap PinMap_PWM[];
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/**********EXTINT*************/
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extern const PinMap PinMap_EXTINT[];
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#endif
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@ -0,0 +1,109 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2013 Nordic Semiconductor
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
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*
|
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PIN_INPUT,
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PIN_OUTPUT,
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PIN_INPUT_OUTPUT //pin state can be set and read back
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} PinDirection;
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typedef enum {
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PA00 = 0,
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PA01 = 1,
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PA02 = 2,
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PA03 = 3,
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PA04 = 4,
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PA05 = 5,
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PA06 = 6,
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PA07 = 7,
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PA08 = 8,
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PA09 = 9,
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PA10 = 10,
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PA11 = 11,
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PA12 = 12,
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PA13 = 13,
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PA14 = 14,
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PA15 = 15,
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PA16 = 16,
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PA17 = 17,
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PA18 = 18,
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PA19 = 19,
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PA20 = 20,
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PA21 = 21,
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PA22 = 22,
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PA23 = 23,
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PA24 = 24,
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PA25 = 25,
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PA27 = 27,
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PA28 = 28,
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PA30 = 30,
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PA31 = 31,
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PB00 = 32,
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PB01 = 33,
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PB02 = 34,
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PB03 = 35,
|
||||
PB04 = 36,
|
||||
PB05 = 37,
|
||||
PB06 = 38,
|
||||
PB07 = 39,
|
||||
PB08 = 40,
|
||||
PB09 = 41,
|
||||
PB10 = 42,
|
||||
PB11 = 43,
|
||||
PB12 = 44,
|
||||
PB13 = 45,
|
||||
PB14 = 46,
|
||||
PB15 = 47,
|
||||
PB16 = 48,
|
||||
PB17 = 49,
|
||||
PB22 = 54,
|
||||
PB23 = 55,
|
||||
PB30 = 62,
|
||||
PB31 = 63,
|
||||
|
||||
USBTX = PA22,
|
||||
USBRX = PA23,
|
||||
|
||||
LED1 = PB30,
|
||||
LED2 = PB30,
|
||||
LED3 = PB30,
|
||||
LED4 = PB30,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullUp = 1,
|
||||
PullDown = 2,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM D21 System Interrupt Driver
|
||||
*
|
||||
* Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
|
||||
#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* Generates a interrupt vector table enum list entry for a given module type
|
||||
and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
|
||||
# define _MODULE_IRQn(n, module) \
|
||||
SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
|
||||
|
||||
/* Generates interrupt vector table enum list entries for all instances of a
|
||||
given module type on the selected device. */
|
||||
# define _SYSTEM_INTERRUPT_MODULES(name) \
|
||||
MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
|
||||
|
||||
# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f
|
||||
# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003
|
||||
|
||||
# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0
|
||||
|
||||
# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_system_interrupt_group
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Table of possible system interrupt/exception vector numbers.
|
||||
*
|
||||
* Table of all possible interrupt and exception vector indexes within the
|
||||
* SAMD21 device. Check peripherals configuration in SAMD21 datasheet for
|
||||
* available vector index for specific device.
|
||||
*
|
||||
*/
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \note The actual enumeration name is "system_interrupt_vector". */
|
||||
enum system_interrupt_vector_samd21 {
|
||||
#else
|
||||
enum system_interrupt_vector {
|
||||
#endif
|
||||
/** Interrupt vector index for a NMI interrupt. */
|
||||
SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn,
|
||||
/** Interrupt vector index for a Hard Fault memory access exception. */
|
||||
SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn,
|
||||
/** Interrupt vector index for a Supervisor Call exception. */
|
||||
SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn,
|
||||
/** Interrupt vector index for a Pending Supervisor interrupt. */
|
||||
SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn,
|
||||
/** Interrupt vector index for a System Tick interrupt. */
|
||||
SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn,
|
||||
|
||||
/** Interrupt vector index for a Power Manager peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn,
|
||||
/** Interrupt vector index for a System Control peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn,
|
||||
/** Interrupt vector index for a Watch Dog peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn,
|
||||
/** Interrupt vector index for a Real Time Clock peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn,
|
||||
/** Interrupt vector index for an External Interrupt peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn,
|
||||
/** Interrupt vector index for a Non Volatile Memory Controller interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn,
|
||||
/** Interrupt vector index for a Direct Memory Access interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn,
|
||||
#if defined(__DOXYGEN__) || defined(ID_USB)
|
||||
/** Interrupt vector index for a Universal Serial Bus interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn,
|
||||
#endif
|
||||
/** Interrupt vector index for an Event System interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn,
|
||||
#if defined(__DOXYGEN__)
|
||||
/** Interrupt vector index for a SERCOM peripheral interrupt.
|
||||
*
|
||||
* Each specific device may contain several SERCOM peripherals; each module
|
||||
* instance will have its own entry in the table, with the instance number
|
||||
* substituted for "n" in the entry name (e.g.
|
||||
* \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
|
||||
*/
|
||||
SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn,
|
||||
|
||||
/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
|
||||
*
|
||||
* Each specific device may contain several TCC peripherals; each module
|
||||
* instance will have its own entry in the table, with the instance number
|
||||
* substituted for "n" in the entry name (e.g.
|
||||
* \c SYSTEM_INTERRUPT_MODULE_TCC0).
|
||||
*/
|
||||
SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn,
|
||||
|
||||
/** Interrupt vector index for a Timer/Counter peripheral interrupt.
|
||||
*
|
||||
* Each specific device may contain several TC peripherals; each module
|
||||
* instance will have its own entry in the table, with the instance number
|
||||
* substituted for "n" in the entry name (e.g.
|
||||
* \c SYSTEM_INTERRUPT_MODULE_TC3).
|
||||
*/
|
||||
SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn,
|
||||
#else
|
||||
_SYSTEM_INTERRUPT_MODULES(SERCOM)
|
||||
|
||||
_SYSTEM_INTERRUPT_MODULES(TCC)
|
||||
|
||||
SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn,
|
||||
SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn,
|
||||
SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn,
|
||||
# if defined(ID_TC6)
|
||||
SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn,
|
||||
# endif
|
||||
# if defined(ID_TC7)
|
||||
SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn,
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(__DOXYGEN__) || defined(ID_ADC)
|
||||
/** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn,
|
||||
#endif
|
||||
|
||||
#if defined(__DOXYGEN__) || defined(ID_AC)
|
||||
/** Interrupt vector index for an Analog Comparator peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn,
|
||||
#endif
|
||||
|
||||
#if defined(__DOXYGEN__) || defined(ID_DAC)
|
||||
/** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || defined(ID_PTC)
|
||||
/** Interrupt vector index for a Peripheral Touch Controller peripheral
|
||||
* interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || defined(ID_I2S)
|
||||
/** Interrupt vector index for a Inter-IC Sound Interface peripheral
|
||||
* interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || defined(ID_AC1)
|
||||
/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt. */
|
||||
SYSTEM_INTERRUPT_MODULE_AC1 = AC1_IRQn,
|
||||
#endif
|
||||
};
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
|
@ -29,8 +29,9 @@
|
|||
#define DEVICE_SERIAL_FC 1
|
||||
#define DEVICE_SERIAL_ASYNCH 1
|
||||
|
||||
#define DEVICE_I2C 0
|
||||
#define DEVICE_I2CSLAVE 0
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
#define DEVICE_I2C_ASYNCH 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
|
|
|||
|
|
@ -18,10 +18,14 @@
|
|||
#include "gpio_api.h"
|
||||
#include "port.h"
|
||||
|
||||
#if defined(TARGET_SAMR21G18A) // mask to be define for other targets
|
||||
#if defined(TARGET_SAMR21G18A)
|
||||
#define PORTA_MASK 0xDBDFFFF3 // mask for available pins in Port A
|
||||
#define PORTB_MASK 0xC0C3C30D // mask for available pins in Port B
|
||||
#define PORTC_MASK 0x000D0000 // mask for available pins in Port C
|
||||
#elif defined(TARGET_SAMD21J18A)
|
||||
#define PORTA_MASK 0xDBDFFFF3 // mask for available pins in Port A
|
||||
#define PORTB_MASK 0xC0C3C30D // mask for available pins in Port B
|
||||
#define PORTC_MASK 0x000D0000 // mask for available pins in Port C
|
||||
#endif
|
||||
|
||||
uint32_t start_pin(PortName port)
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ class GccArm(Exporter):
|
|||
'NZ32SC151',
|
||||
'SAMR21G18A',
|
||||
'TEENSY3_1',
|
||||
'SAMD21J18A',
|
||||
]
|
||||
|
||||
DOT_IN_RELATIVE_PATH = True
|
||||
|
|
|
|||
|
|
@ -1566,6 +1566,15 @@ class SAMR21G18A(Target):
|
|||
self.supported_toolchains = ["GCC_ARM"]
|
||||
self.default_toolchain = "GCC_ARM"
|
||||
|
||||
class SAMD21J18A(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
self.core = "Cortex-M0+"
|
||||
self.extra_labels = ['Atmel', 'SAM0', 'SAMD21']
|
||||
self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||
self.supported_toolchains = ["GCC_ARM"]
|
||||
self.default_toolchain = "GCC_ARM"
|
||||
|
||||
# Get a single instance for each target
|
||||
TARGETS = [
|
||||
|
||||
|
|
@ -1717,7 +1726,9 @@ TARGETS = [
|
|||
### WIZnet ###
|
||||
WIZWIKI_W7500(),
|
||||
|
||||
### Atmel ###
|
||||
SAMR21G18A(),
|
||||
SAMD21J18A(),
|
||||
]
|
||||
|
||||
# Map each target name to its unique instance
|
||||
|
|
|
|||
Loading…
Reference in New Issue