diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralNames.h new file mode 100644 index 0000000000..b549d22d70 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralNames.h @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define _SERCOM_SPI_NAME(n, unused) \ + SPI##n, + +#define _SERCOM_PAD_NAME(n, pad) \ + SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), + +#define _SERCOM_I2C_NAME(n, unused) \ + I2C##n, + + + +typedef enum { + UART_0 = (int)0x42000800UL, // Base address of SERCOM0 + UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 + UART_2 = (int)0x42001000UL, // Base address of SERCOM2 + UART_3 = (int)0x42001400UL, // Base address of SERCOM3 + UART_4 = (int)0x42001800UL, // Base address of SERCOM4 + UART_5 = (int)0x42001C00UL // Base address of SERCOM5 +} UARTName; + +typedef enum { // for each input control mux 4,5,6,7,16,17,10,11 used in R21 + ADC_2 = 0x2ul, + ADC_3 = 0x3ul, + ADC_4 = 0x4ul, + ADC_5 = 0x5ul, + ADC_6 = 0x6ul, + ADC_7 = 0x7ul, + ADC_8 = 0x8ul, + ADC_10 = 0xAul, + ADC_11 = 0xBul, + ADC_16 = 0x10ul, + ADC_17 = 0x11ul, + ADC_18 = 0x12ul, + ADC_19 = 0x13ul +} ADCName; + +typedef enum { // for each channel + EXTINT_0 = 0, + EXTINT_1, + EXTINT_2, + EXTINT_3, + EXTINT_4, + EXTINT_5, + EXTINT_6, + EXTINT_7, + EXTINT_8, + EXTINT_9, + EXTINT_10, + EXTINT_11, + EXTINT_12, + EXTINT_13, + EXTINT_14, + EXTINT_15 +} EXTINTName; + +typedef enum { + MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) +} SPIName; + +typedef enum { + MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) +} I2CName; + +typedef enum { + /* Pad 0 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) + + /* Pad 1 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) + + /* Pad 2 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) + + /* Pad 3 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) +} SercomPadName; + +typedef enum { + PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */ + PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */ + PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */ +} PWMName; + +struct pwm_pin_channel { + PinName pin; + PWMName pwm; + uint8_t channel_index; +}; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +// Default peripherals +#define MBED_SPI0 PB22, PB02, PB23, PA14 + +#define MBED_UART0 PA04, PA05 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 PA16, PA17 + +#define MBED_ANALOGIN0 PA04 +#define MBED_ANALOGIN1 PA05 +#define MBED_ANALOGIN2 PA06 +#define MBED_ANALOGIN3 PA07 +#define MBED_ANALOGIN4 PB02 +#define MBED_ANALOGIN5 PB03 +#define MBED_ANALOGIN7 PA08 +#define MBED_ANALOGIN8 PA09 + +#define MBED_PWMOUT0 PA18 +#define MBED_PWMOUT1 PA19 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralPins.c new file mode 100644 index 0000000000..ae018a9962 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralPins.c @@ -0,0 +1,225 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PB08, ADC_2, 1}, + {PB09, ADC_3, 1}, + {PA04, ADC_4, 1}, + {PA05, ADC_5, 1}, + {PA06, ADC_6, 1}, + {PA07, ADC_7, 1}, + {PB00, ADC_8, 1}, + {PB02, ADC_10, 1}, + {PB03, ADC_11, 1}, + {PA08, ADC_16, 1}, + {PA09, ADC_17, 1}, + {PA10, ADC_18, 1}, + {PA11, ADC_19, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************SERCOM Pins***********/ +const PinMap PinMap_SERCOM_PAD[] = { + {PA00, SERCOM1_PAD0, 3}, + {PA01, SERCOM1_PAD1, 3}, + {PA04, SERCOM0_PAD0, 3}, + {PA05, SERCOM0_PAD1, 3}, + {PA06, SERCOM0_PAD2, 3}, + {PA07, SERCOM0_PAD3, 3}, + {PA08, SERCOM0_PAD0, 2}, + {PA09, SERCOM0_PAD1, 2}, + {PA12, SERCOM2_PAD0, 2}, + {PA13, SERCOM2_PAD1, 2}, + {PA14, SERCOM2_PAD2, 2}, + {PA15, SERCOM2_PAD3, 2}, + {PA16, SERCOM1_PAD0, 2}, + {PA17, SERCOM1_PAD1, 2}, + {PA18, SERCOM1_PAD2, 2}, + {PA19, SERCOM1_PAD3, 2}, + {PA22, SERCOM3_PAD0, 2}, + {PA23, SERCOM3_PAD1, 2}, + {PA24, SERCOM3_PAD2, 2}, + {PA25, SERCOM3_PAD3, 2}, + {PA27, SERCOM3_PAD0, 5}, + {PA28, SERCOM3_PAD1, 5}, + {PA30, SERCOM1_PAD2, 3}, + {PA31, SERCOM1_PAD3, 3}, + {PB02, SERCOM5_PAD0, 3}, + {PB03, SERCOM5_PAD1, 3}, + {PB22, SERCOM5_PAD2, 3}, + {PB23, SERCOM5_PAD3, 3}, + {PB30, SERCOM4_PAD2, 5}, + {PB31, SERCOM4_PAD1, 5}, + {PC18, SERCOM4_PAD3, 5}, + {PC19, SERCOM4_PAD0, 5}, + + /* Not connected */ + {NC , NC , NC} +}; + +/*******SERCOM Pins extended*******/ +const PinMap PinMap_SERCOM_PADEx[] = { + {PA08, SERCOM2_PAD0, 3}, + {PA09, SERCOM2_PAD1, 3}, + {PA16, SERCOM3_PAD0, 3}, + {PA17, SERCOM3_PAD1, 3}, + {PA18, SERCOM3_PAD2, 3}, + {PA19, SERCOM3_PAD3, 3}, + {PA22, SERCOM5_PAD0, 3}, + {PA23, SERCOM5_PAD1, 3}, + {PA24, SERCOM5_PAD2, 3}, + {PA25, SERCOM5_PAD3, 3}, + + /* Not connected */ + {NC , NC , NC} +}; + + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA00, PWM_2, 4}, + {PA01, PWM_2, 4}, + {PA04, PWM_0, 4}, + {PA05, PWM_0, 4}, + {PA06, PWM_1, 4}, + {PA07, PWM_1, 4}, + {PA08, PWM_0, 4}, + {PA09, PWM_0, 4}, + {PA10, PWM_1, 4}, + {PA11, PWM_1, 4}, + {PA12, PWM_2, 4}, + {PA13, PWM_2, 4}, + {PA16, PWM_2, 4}, + {PA17, PWM_2, 4}, + {PA18, PWM_0, 5}, + {PA19, PWM_0, 5}, + {PA20, PWM_0, 5}, + {PA22, PWM_0, 5}, + {PA23, PWM_0, 5}, + {PA24, PWM_1, 5}, + {PA25, PWM_1, 5}, + {PA30, PWM_1, 4}, + {PA31, PWM_1, 4}, + {PB16, PWM_0, 5}, + {PB17, PWM_0, 5}, + {PB30, PWM_0, 4}, + {PB31, PWM_0, 4}, + + /* Not connected */ + {NC , NC , NC} +}; + +/**********EXTINT*************/ +const PinMap PinMap_EXTINT[] = { + {PA16, EXTINT_0, 0}, + {PB00, EXTINT_0, 0}, + {PB16, EXTINT_0, 0}, + {PA00, EXTINT_0, 0}, + + {PA17, EXTINT_1, 0}, + {PB17, EXTINT_1, 0}, + {PA01, EXTINT_1, 0}, + + {PA18, EXTINT_2, 0}, + {PB02, EXTINT_2, 0}, + + {PA19, EXTINT_3, 0}, + {PB03, EXTINT_3, 0}, + + {PA04, EXTINT_4, 0}, + {PA20, EXTINT_4, 0}, + + {PA05, EXTINT_5, 0}, + + {PA06, EXTINT_6, 0}, + {PA22, EXTINT_6, 0}, + {PB22, EXTINT_6, 0}, + + {PA07, EXTINT_7, 0}, + {PA23, EXTINT_7, 0}, + {PB23, EXTINT_7, 0}, + + {PA28, EXTINT_8, 0}, + {PB08, EXTINT_8, 0}, + + {PA09, EXTINT_9, 0}, + {PB09, EXTINT_9, 0}, + + {PA30, EXTINT_10, 0}, + {PA10, EXTINT_10, 0}, + + {PA31, EXTINT_11, 0}, + {PA11, EXTINT_11, 0}, + + {PA12, EXTINT_12, 0}, + {PA24, EXTINT_12, 0}, + + {PA13, EXTINT_13, 0}, + {PA25, EXTINT_13, 0}, + + {PB14, EXTINT_14, 0}, + {PB30, EXTINT_14, 0}, + {PA14, EXTINT_14, 0}, + + {PA15, EXTINT_15, 0}, + {PA27, EXTINT_15, 0}, + {PB15, EXTINT_15, 0}, + {PB31, EXTINT_15, 0}, + + /* Not connected */ + {NC , NC , NC} +}; + +const struct pwm_pin_channel pwn_pins[] = { + {PA00, PWM_2, 0}, + {PA01, PWM_2, 1}, + {PA04, PWM_0, 0}, + {PA05, PWM_0, 1}, + {PA06, PWM_1, 0}, + {PA07, PWM_1, 1}, + {PA08, PWM_0, 0}, + {PA09, PWM_0, 1}, + {PA10, PWM_1, 0}, + {PA11, PWM_1, 1}, + {PA12, PWM_2, 0}, + {PA13, PWM_2, 1}, + {PA16, PWM_2, 0}, + {PA17, PWM_2, 1}, + {PA18, PWM_0, 2}, + {PA19, PWM_0, 3}, + {PA20, PWM_0, 6}, + {PA22, PWM_0, 4}, + {PA23, PWM_0, 5}, + {PA24, PWM_1, 2}, + {PA25, PWM_1, 3}, + {PA30, PWM_1, 0}, + {PA31, PWM_1, 1}, + {PB16, PWM_0, 4}, + {PB17, PWM_0, 5}, + {PB30, PWM_0, 0}, + {PB31, PWM_0, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + + + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralPins.h new file mode 100644 index 0000000000..0571b092e6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PeripheralPins.h @@ -0,0 +1,37 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +//*********SERCOM*************/ +extern const PinMap PinMap_SERCOM_PAD[]; +extern const PinMap PinMap_SERCOM_PADEx[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/**********EXTINT*************/ +extern const PinMap PinMap_EXTINT[]; + + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PinNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PinNames.h new file mode 100644 index 0000000000..07466e407d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMD21J18A/PinNames.h @@ -0,0 +1,109 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INPUT_OUTPUT //pin state can be set and read back +} PinDirection; + +typedef enum { + PA00 = 0, + PA01 = 1, + PA02 = 2, + PA03 = 3, + PA04 = 4, + PA05 = 5, + PA06 = 6, + PA07 = 7, + PA08 = 8, + PA09 = 9, + PA10 = 10, + PA11 = 11, + PA12 = 12, + PA13 = 13, + PA14 = 14, + PA15 = 15, + PA16 = 16, + PA17 = 17, + PA18 = 18, + PA19 = 19, + PA20 = 20, + PA21 = 21, + PA22 = 22, + PA23 = 23, + PA24 = 24, + PA25 = 25, + PA27 = 27, + PA28 = 28, + PA30 = 30, + PA31 = 31, + + PB00 = 32, + PB01 = 33, + PB02 = 34, + PB03 = 35, + PB04 = 36, + PB05 = 37, + PB06 = 38, + PB07 = 39, + PB08 = 40, + PB09 = 41, + PB10 = 42, + PB11 = 43, + PB12 = 44, + PB13 = 45, + PB14 = 46, + PB15 = 47, + PB16 = 48, + PB17 = 49, + PB22 = 54, + PB23 = 55, + PB30 = 62, + PB31 = 63, + + USBTX = PA22, + USBRX = PA23, + + LED1 = PB30, + LED2 = PB30, + LED3 = PB30, + LED4 = PB30, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/system/interrupt/system_interrupt_SAMD21/system_interrupt_features.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/system/interrupt/system_interrupt_SAMD21/system_interrupt_features.h new file mode 100644 index 0000000000..1179b3e59c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/system/interrupt/system_interrupt_SAMD21/system_interrupt_features.h @@ -0,0 +1,195 @@ +/** + * \file + * + * \brief SAM D21 System Interrupt Driver + * + * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED +#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED + +#if !defined(__DOXYGEN__) + +/* Generates a interrupt vector table enum list entry for a given module type + and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */ +# define _MODULE_IRQn(n, module) \ + SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn, + +/* Generates interrupt vector table enum list entries for all instances of a + given module type on the selected device. */ +# define _SYSTEM_INTERRUPT_MODULES(name) \ + MREPEAT(name##_INST_NUM, _MODULE_IRQn, name) + +# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f +# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003 + +# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0 + +# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30 +#endif + +/** + * \addtogroup asfdoc_sam0_system_interrupt_group + * @{ + */ + +/** + * \brief Table of possible system interrupt/exception vector numbers. + * + * Table of all possible interrupt and exception vector indexes within the + * SAMD21 device. Check peripherals configuration in SAMD21 datasheet for + * available vector index for specific device. + * + */ +#if defined(__DOXYGEN__) +/** \note The actual enumeration name is "system_interrupt_vector". */ +enum system_interrupt_vector_samd21 { +#else +enum system_interrupt_vector { +#endif + /** Interrupt vector index for a NMI interrupt. */ + SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, + /** Interrupt vector index for a Hard Fault memory access exception. */ + SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, + /** Interrupt vector index for a Supervisor Call exception. */ + SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, + /** Interrupt vector index for a Pending Supervisor interrupt. */ + SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, + /** Interrupt vector index for a System Tick interrupt. */ + SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, + + /** Interrupt vector index for a Power Manager peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn, + /** Interrupt vector index for a System Control peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn, + /** Interrupt vector index for a Watch Dog peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, + /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, + /** Interrupt vector index for an External Interrupt peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, + /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ + SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, + /** Interrupt vector index for a Direct Memory Access interrupt. */ + SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, +#if defined(__DOXYGEN__) || defined(ID_USB) + /** Interrupt vector index for a Universal Serial Bus interrupt. */ + SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, +#endif + /** Interrupt vector index for an Event System interrupt. */ + SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, +#if defined(__DOXYGEN__) + /** Interrupt vector index for a SERCOM peripheral interrupt. + * + * Each specific device may contain several SERCOM peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). + */ + SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, + + /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. + * + * Each specific device may contain several TCC peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_TCC0). + */ + SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, + + /** Interrupt vector index for a Timer/Counter peripheral interrupt. + * + * Each specific device may contain several TC peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_TC3). + */ + SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, +#else + _SYSTEM_INTERRUPT_MODULES(SERCOM) + + _SYSTEM_INTERRUPT_MODULES(TCC) + + SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn, + SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, + SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn, +# if defined(ID_TC6) + SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn, +# endif +# if defined(ID_TC7) + SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn, +# endif +#endif + +#if defined(__DOXYGEN__) || defined(ID_ADC) + /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, +#endif + +#if defined(__DOXYGEN__) || defined(ID_AC) + /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, +#endif + +#if defined(__DOXYGEN__) || defined(ID_DAC) + /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, +#endif +#if defined(__DOXYGEN__) || defined(ID_PTC) + /** Interrupt vector index for a Peripheral Touch Controller peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, +#endif +#if defined(__DOXYGEN__) || defined(ID_I2S) + /** Interrupt vector index for a Inter-IC Sound Interface peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn, +#endif +#if defined(__DOXYGEN__) || defined(ID_AC1) + /** Interrupt vector index for an Analog Comparator 1 peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_AC1 = AC1_IRQn, +#endif +}; + +/** @} */ + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h index 2f8646162c..3fb36eb1eb 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h @@ -29,8 +29,9 @@ #define DEVICE_SERIAL_FC 1 #define DEVICE_SERIAL_ASYNCH 1 -#define DEVICE_I2C 0 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2C_ASYNCH 1 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c index 8befe4d8a2..a732d1254d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c @@ -18,10 +18,14 @@ #include "gpio_api.h" #include "port.h" -#if defined(TARGET_SAMR21G18A) // mask to be define for other targets +#if defined(TARGET_SAMR21G18A) #define PORTA_MASK 0xDBDFFFF3 // mask for available pins in Port A #define PORTB_MASK 0xC0C3C30D // mask for available pins in Port B #define PORTC_MASK 0x000D0000 // mask for available pins in Port C +#elif defined(TARGET_SAMD21J18A) +#define PORTA_MASK 0xDBDFFFF3 // mask for available pins in Port A +#define PORTB_MASK 0xC0C3C30D // mask for available pins in Port B +#define PORTC_MASK 0x000D0000 // mask for available pins in Port C #endif uint32_t start_pin(PortName port) diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index e086f88379..f03a18fbbc 100755 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -97,6 +97,7 @@ class GccArm(Exporter): 'NZ32SC151', 'SAMR21G18A', 'TEENSY3_1', + 'SAMD21J18A', ] DOT_IN_RELATIVE_PATH = True diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 68020ac617..bc7ae8365d 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1566,6 +1566,15 @@ class SAMR21G18A(Target): self.supported_toolchains = ["GCC_ARM"] self.default_toolchain = "GCC_ARM" +class SAMD21J18A(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Atmel', 'SAM0', 'SAMD21'] + self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] + self.supported_toolchains = ["GCC_ARM"] + self.default_toolchain = "GCC_ARM" + # Get a single instance for each target TARGETS = [ @@ -1717,7 +1726,9 @@ TARGETS = [ ### WIZnet ### WIZWIKI_W7500(), + ### Atmel ### SAMR21G18A(), + SAMD21J18A(), ] # Map each target name to its unique instance