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Set NANO130 CLK as 48 MHz for USBD support

pull/12176/head
cyliangtw 2019-11-20 18:00:02 +08:00
parent abf3eeed64
commit 6612ee8460
1 changed files with 3 additions and 3 deletions
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6
targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c
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@ -64,7 +64,7 @@ void mbed_sdk_init(void)
* T2. <1 ms with HIRC-clocked PLL as HCLK clock source
* T1 will fail Greentea test which requires max 10 ms wake-up time.
*
* If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz,
* If we just call CLK_SetCoreClock(FREQ_48MHZ) to configure HCLK to 48 MHz,
* it will go T1 with HXT already enabled in front. So we manually configure
* it to choose HXT/HIRC-clocked PLL.
*/
@ -76,10 +76,10 @@ void mbed_sdk_init(void)
#endif
#if (NU_CLOCK_PLL == NU_HXT_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2);
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_48MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#elif (NU_CLOCK_PLL == NU_HIRC_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2);
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_48MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#endif